LLVM  12.0.0git
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "AMDGPU.h"
11 #include "AMDGPUTargetMachine.h"
13 #include "SIRegisterInfo.h"
15 #include "llvm/IR/Function.h"
18 
19 using namespace llvm;
20 
21 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
22 
24  "Argument Register Usage Information Storage", false, true)
25 
27  const TargetRegisterInfo *TRI) const {
28  if (!isSet()) {
29  OS << "<not set>\n";
30  return;
31  }
32 
33  if (isRegister())
34  OS << "Reg " << printReg(getRegister(), TRI);
35  else
36  OS << "Stack offset " << getStackOffset();
37 
38  if (isMasked()) {
39  OS << " & ";
41  }
42 
43  OS << '\n';
44 }
45 
47 
49 
50 // Hardcoded registers from fixed function ABI
53 
55  return false;
56 }
57 
59  ArgInfoMap.clear();
60  return false;
61 }
62 
64  for (const auto &FI : ArgInfoMap) {
65  OS << "Arguments for " << FI.first->getName() << '\n'
66  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
67  << " DispatchPtr: " << FI.second.DispatchPtr
68  << " QueuePtr: " << FI.second.QueuePtr
69  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
70  << " DispatchID: " << FI.second.DispatchID
71  << " FlatScratchInit: " << FI.second.FlatScratchInit
72  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
73  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
74  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
75  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
76  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
77  << " PrivateSegmentWaveByteOffset: "
78  << FI.second.PrivateSegmentWaveByteOffset
79  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
80  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
81  << " WorkItemIDX " << FI.second.WorkItemIDX
82  << " WorkItemIDY " << FI.second.WorkItemIDY
83  << " WorkItemIDZ " << FI.second.WorkItemIDZ
84  << '\n';
85  }
86 }
87 
88 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
91  switch (Value) {
93  return std::make_tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer
94  : nullptr,
95  &AMDGPU::SGPR_128RegClass, LLT::vector(4, 32));
96  }
98  return std::make_tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
99  &AMDGPU::SGPR_64RegClass,
102  return std::make_tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
103  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
105  return std::make_tuple(WorkGroupIDY ? &WorkGroupIDY : nullptr,
106  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
108  return std::make_tuple(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
109  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
111  return std::make_tuple(
113  &AMDGPU::SGPR_32RegClass, LLT::scalar(32));
115  return std::make_tuple(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
116  &AMDGPU::SGPR_64RegClass,
119  return std::make_tuple(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
120  &AMDGPU::SGPR_64RegClass,
123  return std::make_tuple(DispatchID ? &DispatchID : nullptr,
124  &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
126  return std::make_tuple(FlatScratchInit ? &FlatScratchInit : nullptr,
127  &AMDGPU::SGPR_64RegClass, LLT::scalar(64));
129  return std::make_tuple(DispatchPtr ? &DispatchPtr : nullptr,
130  &AMDGPU::SGPR_64RegClass,
133  return std::make_tuple(QueuePtr ? &QueuePtr : nullptr,
134  &AMDGPU::SGPR_64RegClass,
137  return std::make_tuple(WorkItemIDX ? &WorkItemIDX : nullptr,
138  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
140  return std::make_tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
141  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
143  return std::make_tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
144  &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
145  }
146  llvm_unreachable("unexpected preloaded value type");
147 }
148 
152  = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
153  AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
154  AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
155 
156  // Do not pass kernarg segment pointer, only pass increment version in its
157  // place.
158  AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9);
159  AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11);
160 
161  // Skip FlatScratchInit/PrivateSegmentSize
162  AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12);
163  AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13);
164  AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14);
165 
166  const unsigned Mask = 0x3ff;
167  AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
168  AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
169  AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
170  return AI;
171 }
172 
173 const AMDGPUFunctionArgInfo &
175  auto I = ArgInfoMap.find(&F);
176  if (I == ArgInfoMap.end()) {
178  return FixedABIFunctionInfo;
179 
180  // Without the fixed ABI, we assume no function has special inputs.
181  assert(F.isDeclaration());
182  return ExternFunctionInfo;
183  }
184 
185  return I->second;
186 }
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Interface definition for SIRegisterInfo.
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static constexpr AMDGPUFunctionArgInfo fixedABILayout()
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
Address space for constant memory (VTX2).
Definition: AMDGPU.h:368
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
unsigned const TargetRegisterInfo * TRI
F(f)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset)
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
The AMDGPU TargetMachine interface definition for hw codgen targets.
const AMDGPUFunctionArgInfo & lookupFuncArgInfo(const Function &F) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Provides AMDGPU specific target descriptions.
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, Optional< size_t > Width=None)
static const AMDGPUFunctionArgInfo ExternFunctionInfo
#define I(x, y, z)
Definition: MD5.cpp:59
#define DEBUG_TYPE
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
LLVM Value Representation.
Definition: Value.h:75
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...