LLVM  11.0.0git
AMDGPUArgumentUsageInfo.cpp
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1 //===----------------------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPU.h"
11 #include "AMDGPUTargetMachine.h"
13 #include "SIRegisterInfo.h"
16 
17 using namespace llvm;
18 
19 #define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
20 
22  "Argument Register Usage Information Storage", false, true)
23 
25  const TargetRegisterInfo *TRI) const {
26  if (!isSet()) {
27  OS << "<not set>\n";
28  return;
29  }
30 
31  if (isRegister())
32  OS << "Reg " << printReg(getRegister(), TRI);
33  else
34  OS << "Stack offset " << getStackOffset();
35 
36  if (isMasked()) {
37  OS << " & ";
39  }
40 
41  OS << '\n';
42 }
43 
45 
47 
48 // Hardcoded registers from fixed function ABI
51 
53  return false;
54 }
55 
57  ArgInfoMap.clear();
58  return false;
59 }
60 
62  for (const auto &FI : ArgInfoMap) {
63  OS << "Arguments for " << FI.first->getName() << '\n'
64  << " PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
65  << " DispatchPtr: " << FI.second.DispatchPtr
66  << " QueuePtr: " << FI.second.QueuePtr
67  << " KernargSegmentPtr: " << FI.second.KernargSegmentPtr
68  << " DispatchID: " << FI.second.DispatchID
69  << " FlatScratchInit: " << FI.second.FlatScratchInit
70  << " PrivateSegmentSize: " << FI.second.PrivateSegmentSize
71  << " WorkGroupIDX: " << FI.second.WorkGroupIDX
72  << " WorkGroupIDY: " << FI.second.WorkGroupIDY
73  << " WorkGroupIDZ: " << FI.second.WorkGroupIDZ
74  << " WorkGroupInfo: " << FI.second.WorkGroupInfo
75  << " PrivateSegmentWaveByteOffset: "
76  << FI.second.PrivateSegmentWaveByteOffset
77  << " ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
78  << " ImplicitArgPtr: " << FI.second.ImplicitArgPtr
79  << " WorkItemIDX " << FI.second.WorkItemIDX
80  << " WorkItemIDY " << FI.second.WorkItemIDY
81  << " WorkItemIDZ " << FI.second.WorkItemIDZ
82  << '\n';
83  }
84 }
85 
86 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
89  switch (Value) {
91  return std::make_pair(
92  PrivateSegmentBuffer ? &PrivateSegmentBuffer : nullptr,
93  &AMDGPU::SGPR_128RegClass);
94  }
96  return std::make_pair(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
97  &AMDGPU::SGPR_64RegClass);
99  return std::make_pair(WorkGroupIDX ? &WorkGroupIDX : nullptr,
100  &AMDGPU::SGPR_32RegClass);
101 
103  return std::make_pair(WorkGroupIDY ? &WorkGroupIDY : nullptr,
104  &AMDGPU::SGPR_32RegClass);
106  return std::make_pair(WorkGroupIDZ ? &WorkGroupIDZ : nullptr,
107  &AMDGPU::SGPR_32RegClass);
109  return std::make_pair(
110  PrivateSegmentWaveByteOffset ? &PrivateSegmentWaveByteOffset : nullptr,
111  &AMDGPU::SGPR_32RegClass);
113  return std::make_pair(KernargSegmentPtr ? &KernargSegmentPtr : nullptr,
114  &AMDGPU::SGPR_64RegClass);
116  return std::make_pair(ImplicitArgPtr ? &ImplicitArgPtr : nullptr,
117  &AMDGPU::SGPR_64RegClass);
119  return std::make_pair(DispatchID ? &DispatchID : nullptr,
120  &AMDGPU::SGPR_64RegClass);
122  return std::make_pair(FlatScratchInit ? &FlatScratchInit : nullptr,
123  &AMDGPU::SGPR_64RegClass);
125  return std::make_pair(DispatchPtr ? &DispatchPtr : nullptr,
126  &AMDGPU::SGPR_64RegClass);
128  return std::make_pair(QueuePtr ? &QueuePtr : nullptr,
129  &AMDGPU::SGPR_64RegClass);
131  return std::make_pair(WorkItemIDX ? &WorkItemIDX : nullptr,
132  &AMDGPU::VGPR_32RegClass);
134  return std::make_pair(WorkItemIDY ? &WorkItemIDY : nullptr,
135  &AMDGPU::VGPR_32RegClass);
137  return std::make_pair(WorkItemIDZ ? &WorkItemIDZ : nullptr,
138  &AMDGPU::VGPR_32RegClass);
139  }
140  llvm_unreachable("unexpected preloaded value type");
141 }
142 
145  AI.PrivateSegmentBuffer = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
146  AI.DispatchPtr = AMDGPU::SGPR4_SGPR5;
147  AI.QueuePtr = AMDGPU::SGPR6_SGPR7;
148 
149  // Do not pass kernarg segment pointer, only pass increment version in its
150  // place.
151  AI.ImplicitArgPtr = AMDGPU::SGPR8_SGPR9;
152  AI.DispatchID = AMDGPU::SGPR10_SGPR11;
153 
154  // Skip FlatScratchInit/PrivateSegmentSize
155  AI.WorkGroupIDX = AMDGPU::SGPR12;
156  AI.WorkGroupIDY = AMDGPU::SGPR13;
157  AI.WorkGroupIDZ = AMDGPU::SGPR14;
158 
159  const unsigned Mask = 0x3ff;
160  AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask);
161  AI.WorkItemIDY = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 10);
162  AI.WorkItemIDZ = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask << 20);
163  return AI;
164 }
165 
166 const AMDGPUFunctionArgInfo &
168  auto I = ArgInfoMap.find(&F);
169  if (I == ArgInfoMap.end()) {
171  return FixedABIFunctionInfo;
172 
173  // Without the fixed ABI, we assume no function has special inputs.
174  assert(F.isDeclaration());
175  return ExternFunctionInfo;
176  }
177 
178  return I->second;
179 }
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Interface definition for SIRegisterInfo.
static constexpr ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static constexpr AMDGPUFunctionArgInfo fixedABILayout()
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:67
unsigned const TargetRegisterInfo * TRI
F(f)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset)
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
std::pair< const ArgDescriptor *, const TargetRegisterClass * > getPreloadedValue(PreloadedValue Value) const
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
The AMDGPU TargetMachine interface definition for hw codgen targets.
const AMDGPUFunctionArgInfo & lookupFuncArgInfo(const Function &F) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Provides AMDGPU specific target descriptions.
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, Optional< size_t > Width=None)
static const AMDGPUFunctionArgInfo ExternFunctionInfo
#define I(x, y, z)
Definition: MD5.cpp:59
#define DEBUG_TYPE
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
Definition: Globals.cpp:227
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...