20#define DEBUG_TYPE "amdgpu-argument-reg-usage-info"
23 "Argument Register Usage Information Storage",
false,
true)
64 for (
const auto &FI : ArgInfoMap) {
65 OS <<
"Arguments for " << FI.first->getName() <<
'\n'
66 <<
" PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
67 <<
" DispatchPtr: " << FI.second.DispatchPtr
68 <<
" QueuePtr: " << FI.second.QueuePtr
69 <<
" KernargSegmentPtr: " << FI.second.KernargSegmentPtr
70 <<
" DispatchID: " << FI.second.DispatchID
71 <<
" FlatScratchInit: " << FI.second.FlatScratchInit
72 <<
" PrivateSegmentSize: " << FI.second.PrivateSegmentSize
73 <<
" WorkGroupIDX: " << FI.second.WorkGroupIDX
74 <<
" WorkGroupIDY: " << FI.second.WorkGroupIDY
75 <<
" WorkGroupIDZ: " << FI.second.WorkGroupIDZ
76 <<
" WorkGroupInfo: " << FI.second.WorkGroupInfo
77 <<
" LDSKernelId: " << FI.second.LDSKernelId
78 <<
" PrivateSegmentWaveByteOffset: "
79 << FI.second.PrivateSegmentWaveByteOffset
80 <<
" ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
81 <<
" ImplicitArgPtr: " << FI.second.ImplicitArgPtr
82 <<
" WorkItemIDX " << FI.second.WorkItemIDX
83 <<
" WorkItemIDY " << FI.second.WorkItemIDY
84 <<
" WorkItemIDZ " << FI.second.WorkItemIDZ
89std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
99 &AMDGPU::SGPR_64RegClass,
122 &AMDGPU::SGPR_64RegClass,
126 &AMDGPU::SGPR_64RegClass,
136 &AMDGPU::SGPR_64RegClass,
172 const unsigned Mask = 0x3ff;
181 auto I = ArgInfoMap.find(&
F);
182 if (
I == ArgInfoMap.end())
static StackOffset getStackOffset(const MachineFunction &MF, int64_t ObjectOffset)
Provides AMDGPU specific target descriptions.
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Interface definition for SIRegisterInfo.
static const AMDGPUFunctionArgInfo ExternFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
const AMDGPUFunctionArgInfo & lookupFuncArgInfo(const Function &F) const
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
bool doInitialization(Module &M) override
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before ...
bool doFinalization(Module &M) override
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes...
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
A Module instance is used to store all the information related to an LLVM module.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
This is an optimization pass for GlobalISel generic memory operations.
void write_hex(raw_ostream &S, uint64_t N, HexPrintStyle Style, std::optional< size_t > Width=std::nullopt)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
@ PRIVATE_SEGMENT_WAVE_BYTE_OFFSET
ArgDescriptor PrivateSegmentBuffer
ArgDescriptor WorkGroupIDY
ArgDescriptor WorkGroupIDZ
ArgDescriptor PrivateSegmentSize
ArgDescriptor ImplicitArgPtr
ArgDescriptor PrivateSegmentWaveByteOffset
static AMDGPUFunctionArgInfo fixedABILayout()
ArgDescriptor WorkItemIDZ
ArgDescriptor WorkItemIDY
ArgDescriptor LDSKernelId
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
ArgDescriptor KernargSegmentPtr
ArgDescriptor WorkItemIDX
ArgDescriptor FlatScratchInit
ArgDescriptor DispatchPtr
ArgDescriptor ImplicitBufferPtr
ArgDescriptor WorkGroupIDX
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)