LLVM 18.0.0git
CallLowering.cpp
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1//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements some simple delegations needed for call lowering.
11///
12//===----------------------------------------------------------------------===//
13
23#include "llvm/IR/DataLayout.h"
24#include "llvm/IR/LLVMContext.h"
25#include "llvm/IR/Module.h"
27
28#define DEBUG_TYPE "call-lowering"
29
30using namespace llvm;
31
32void CallLowering::anchor() {}
33
34/// Helper function which updates \p Flags when \p AttrFn returns true.
35static void
37 const std::function<bool(Attribute::AttrKind)> &AttrFn) {
38 if (AttrFn(Attribute::SExt))
39 Flags.setSExt();
40 if (AttrFn(Attribute::ZExt))
41 Flags.setZExt();
42 if (AttrFn(Attribute::InReg))
43 Flags.setInReg();
44 if (AttrFn(Attribute::StructRet))
45 Flags.setSRet();
46 if (AttrFn(Attribute::Nest))
47 Flags.setNest();
48 if (AttrFn(Attribute::ByVal))
49 Flags.setByVal();
50 if (AttrFn(Attribute::Preallocated))
51 Flags.setPreallocated();
52 if (AttrFn(Attribute::InAlloca))
53 Flags.setInAlloca();
54 if (AttrFn(Attribute::Returned))
55 Flags.setReturned();
56 if (AttrFn(Attribute::SwiftSelf))
57 Flags.setSwiftSelf();
58 if (AttrFn(Attribute::SwiftAsync))
59 Flags.setSwiftAsync();
60 if (AttrFn(Attribute::SwiftError))
61 Flags.setSwiftError();
62}
63
65 unsigned ArgIdx) const {
66 ISD::ArgFlagsTy Flags;
67 addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
68 return Call.paramHasAttr(ArgIdx, Attr);
69 });
70 return Flags;
71}
72
75 ISD::ArgFlagsTy Flags;
76 addFlagsUsingAttrFn(Flags, [&Call](Attribute::AttrKind Attr) {
77 return Call.hasRetAttr(Attr);
78 });
79 return Flags;
80}
81
83 const AttributeList &Attrs,
84 unsigned OpIdx) const {
85 addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
86 return Attrs.hasAttributeAtIndex(OpIdx, Attr);
87 });
88}
89
91 ArrayRef<Register> ResRegs,
93 Register SwiftErrorVReg,
94 std::function<unsigned()> GetCalleeReg) const {
96 const DataLayout &DL = MIRBuilder.getDataLayout();
97 MachineFunction &MF = MIRBuilder.getMF();
99 bool CanBeTailCalled = CB.isTailCall() &&
101 (MF.getFunction()
102 .getFnAttribute("disable-tail-calls")
103 .getValueAsString() != "true");
104
105 CallingConv::ID CallConv = CB.getCallingConv();
106 Type *RetTy = CB.getType();
107 bool IsVarArg = CB.getFunctionType()->isVarArg();
108
110 getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
111 Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
112
113 Info.IsConvergent = CB.isConvergent();
114
115 if (!Info.CanLowerReturn) {
116 // Callee requires sret demotion.
117 insertSRetOutgoingArgument(MIRBuilder, CB, Info);
118
119 // The sret demotion isn't compatible with tail-calls, since the sret
120 // argument points into the caller's stack frame.
121 CanBeTailCalled = false;
122 }
123
124
125 // First step is to marshall all the function's parameters into the correct
126 // physregs and memory locations. Gather the sequence of argument types that
127 // we'll pass to the assigner function.
128 unsigned i = 0;
129 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
130 for (const auto &Arg : CB.args()) {
131 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i),
132 i < NumFixedArgs};
134
135 // If we have an explicit sret argument that is an Instruction, (i.e., it
136 // might point to function-local memory), we can't meaningfully tail-call.
137 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
138 CanBeTailCalled = false;
139
140 Info.OrigArgs.push_back(OrigArg);
141 ++i;
142 }
143
144 // Try looking through a bitcast from one function type to another.
145 // Commonly happens with calls to objc_msgSend().
146 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
147 if (const Function *F = dyn_cast<Function>(CalleeV))
148 Info.Callee = MachineOperand::CreateGA(F, 0);
149 else
150 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
151
152 Register ReturnHintAlignReg;
153 Align ReturnHintAlign;
154
155 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, getAttributesForReturn(CB)};
156
157 if (!Info.OrigRet.Ty->isVoidTy()) {
159
160 if (MaybeAlign Alignment = CB.getRetAlign()) {
161 if (*Alignment > Align(1)) {
162 ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
163 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
164 ReturnHintAlign = *Alignment;
165 }
166 }
167 }
168
169 auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi);
170 if (Bundle && CB.isIndirectCall()) {
171 Info.CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
172 assert(Info.CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
173 }
174
175 Info.CB = &CB;
176 Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
177 Info.CallConv = CallConv;
178 Info.SwiftErrorVReg = SwiftErrorVReg;
179 Info.IsMustTailCall = CB.isMustTailCall();
180 Info.IsTailCall = CanBeTailCalled;
181 Info.IsVarArg = IsVarArg;
182 if (!lowerCall(MIRBuilder, Info))
183 return false;
184
185 if (ReturnHintAlignReg && !Info.IsTailCall) {
186 MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg,
187 ReturnHintAlign);
188 }
189
190 return true;
191}
192
193template <typename FuncInfoTy>
195 const DataLayout &DL,
196 const FuncInfoTy &FuncInfo) const {
197 auto &Flags = Arg.Flags[0];
198 const AttributeList &Attrs = FuncInfo.getAttributes();
199 addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
200
201 PointerType *PtrTy = dyn_cast<PointerType>(Arg.Ty->getScalarType());
202 if (PtrTy) {
203 Flags.setPointer();
204 Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace());
205 }
206
207 Align MemAlign = DL.getABITypeAlign(Arg.Ty);
208 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
210 unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
211
212 Type *ElementTy = FuncInfo.getParamByValType(ParamIdx);
213 if (!ElementTy)
214 ElementTy = FuncInfo.getParamInAllocaType(ParamIdx);
215 if (!ElementTy)
216 ElementTy = FuncInfo.getParamPreallocatedType(ParamIdx);
217 assert(ElementTy && "Must have byval, inalloca or preallocated type");
218 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
219
220 // For ByVal, alignment should be passed from FE. BE will guess if
221 // this info is not there but there are cases it cannot get right.
222 if (auto ParamAlign = FuncInfo.getParamStackAlign(ParamIdx))
223 MemAlign = *ParamAlign;
224 else if ((ParamAlign = FuncInfo.getParamAlign(ParamIdx)))
225 MemAlign = *ParamAlign;
226 else
227 MemAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
228 } else if (OpIdx >= AttributeList::FirstArgIndex) {
229 if (auto ParamAlign =
230 FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
231 MemAlign = *ParamAlign;
232 }
233 Flags.setMemAlign(MemAlign);
234 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
235
236 // Don't try to use the returned attribute if the argument is marked as
237 // swiftself, since it won't be passed in x0.
238 if (Flags.isSwiftSelf())
239 Flags.setReturned(false);
240}
241
242template void
243CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
244 const DataLayout &DL,
245 const Function &FuncInfo) const;
246
247template void
248CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
249 const DataLayout &DL,
250 const CallBase &FuncInfo) const;
251
253 SmallVectorImpl<ArgInfo> &SplitArgs,
254 const DataLayout &DL,
255 CallingConv::ID CallConv,
256 SmallVectorImpl<uint64_t> *Offsets) const {
257 LLVMContext &Ctx = OrigArg.Ty->getContext();
258
259 SmallVector<EVT, 4> SplitVTs;
260 ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, Offsets, 0);
261
262 if (SplitVTs.size() == 0)
263 return;
264
265 if (SplitVTs.size() == 1) {
266 // No splitting to do, but we want to replace the original type (e.g. [1 x
267 // double] -> double).
268 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
269 OrigArg.OrigArgIndex, OrigArg.Flags[0],
270 OrigArg.IsFixed, OrigArg.OrigValue);
271 return;
272 }
273
274 // Create one ArgInfo for each virtual register in the original ArgInfo.
275 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
276
277 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
278 OrigArg.Ty, CallConv, false, DL);
279 for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
280 Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
281 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,
282 OrigArg.Flags[0], OrigArg.IsFixed);
283 if (NeedsRegBlock)
284 SplitArgs.back().Flags[0].setInConsecutiveRegs();
285 }
286
287 SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
288}
289
290/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
293 ArrayRef<Register> SrcRegs) {
294 MachineRegisterInfo &MRI = *B.getMRI();
295 LLT LLTy = MRI.getType(DstRegs[0]);
296 LLT PartLLT = MRI.getType(SrcRegs[0]);
297
298 // Deal with v3s16 split into v2s16
299 LLT LCMTy = getCoverTy(LLTy, PartLLT);
300 if (LCMTy == LLTy) {
301 // Common case where no padding is needed.
302 assert(DstRegs.size() == 1);
303 return B.buildConcatVectors(DstRegs[0], SrcRegs);
304 }
305
306 // We need to create an unmerge to the result registers, which may require
307 // widening the original value.
308 Register UnmergeSrcReg;
309 if (LCMTy != PartLLT) {
310 assert(DstRegs.size() == 1);
311 return B.buildDeleteTrailingVectorElements(
312 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs));
313 } else {
314 // We don't need to widen anything if we're extracting a scalar which was
315 // promoted to a vector e.g. s8 -> v4s8 -> s8
316 assert(SrcRegs.size() == 1);
317 UnmergeSrcReg = SrcRegs[0];
318 }
319
320 int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
321
322 SmallVector<Register, 8> PadDstRegs(NumDst);
323 std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
324
325 // Create the excess dead defs for the unmerge.
326 for (int I = DstRegs.size(); I != NumDst; ++I)
327 PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
328
329 if (PadDstRegs.size() == 1)
330 return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
331 return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
332}
333
334/// Create a sequence of instructions to combine pieces split into register
335/// typed values to the original IR value. \p OrigRegs contains the destination
336/// value registers of type \p LLTy, and \p Regs contains the legalized pieces
337/// with type \p PartLLT. This is used for incoming values (physregs to vregs).
339 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
340 const ISD::ArgFlagsTy Flags) {
341 MachineRegisterInfo &MRI = *B.getMRI();
342
343 if (PartLLT == LLTy) {
344 // We should have avoided introducing a new virtual register, and just
345 // directly assigned here.
346 assert(OrigRegs[0] == Regs[0]);
347 return;
348 }
349
350 if (PartLLT.getSizeInBits() == LLTy.getSizeInBits() && OrigRegs.size() == 1 &&
351 Regs.size() == 1) {
352 B.buildBitcast(OrigRegs[0], Regs[0]);
353 return;
354 }
355
356 // A vector PartLLT needs extending to LLTy's element size.
357 // E.g. <2 x s64> = G_SEXT <2 x s32>.
358 if (PartLLT.isVector() == LLTy.isVector() &&
359 PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
360 (!PartLLT.isVector() ||
361 PartLLT.getNumElements() == LLTy.getNumElements()) &&
362 OrigRegs.size() == 1 && Regs.size() == 1) {
363 Register SrcReg = Regs[0];
364
365 LLT LocTy = MRI.getType(SrcReg);
366
367 if (Flags.isSExt()) {
368 SrcReg = B.buildAssertSExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
369 .getReg(0);
370 } else if (Flags.isZExt()) {
371 SrcReg = B.buildAssertZExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
372 .getReg(0);
373 }
374
375 // Sometimes pointers are passed zero extended.
376 LLT OrigTy = MRI.getType(OrigRegs[0]);
377 if (OrigTy.isPointer()) {
378 LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits());
379 B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg));
380 return;
381 }
382
383 B.buildTrunc(OrigRegs[0], SrcReg);
384 return;
385 }
386
387 if (!LLTy.isVector() && !PartLLT.isVector()) {
388 assert(OrigRegs.size() == 1);
389 LLT OrigTy = MRI.getType(OrigRegs[0]);
390
391 unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
392 if (SrcSize == OrigTy.getSizeInBits())
393 B.buildMergeValues(OrigRegs[0], Regs);
394 else {
395 auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs);
396 B.buildTrunc(OrigRegs[0], Widened);
397 }
398
399 return;
400 }
401
402 if (PartLLT.isVector()) {
403 assert(OrigRegs.size() == 1);
404 SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
405
406 // If PartLLT is a mismatched vector in both number of elements and element
407 // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
408 // have the same elt type, i.e. v4s32.
409 if (PartLLT.getSizeInBits() > LLTy.getSizeInBits() &&
410 PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
411 Regs.size() == 1) {
412 LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
413 .changeElementCount(PartLLT.getElementCount() * 2);
414 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
415 PartLLT = NewTy;
416 }
417
418 if (LLTy.getScalarType() == PartLLT.getElementType()) {
419 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
420 } else {
421 unsigned I = 0;
422 LLT GCDTy = getGCDType(LLTy, PartLLT);
423
424 // We are both splitting a vector, and bitcasting its element types. Cast
425 // the source pieces into the appropriate number of pieces with the result
426 // element type.
427 for (Register SrcReg : CastRegs)
428 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0);
429 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
430 }
431
432 return;
433 }
434
435 assert(LLTy.isVector() && !PartLLT.isVector());
436
437 LLT DstEltTy = LLTy.getElementType();
438
439 // Pointer information was discarded. We'll need to coerce some register types
440 // to avoid violating type constraints.
441 LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
442
443 assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
444
445 if (DstEltTy == PartLLT) {
446 // Vector was trivially scalarized.
447
448 if (RealDstEltTy.isPointer()) {
449 for (Register Reg : Regs)
450 MRI.setType(Reg, RealDstEltTy);
451 }
452
453 B.buildBuildVector(OrigRegs[0], Regs);
454 } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
455 // Deal with vector with 64-bit elements decomposed to 32-bit
456 // registers. Need to create intermediate 64-bit elements.
457 SmallVector<Register, 8> EltMerges;
458 int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
459
460 assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
461
462 for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
463 auto Merge =
464 B.buildMergeLikeInstr(RealDstEltTy, Regs.take_front(PartsPerElt));
465 // Fix the type in case this is really a vector of pointers.
466 MRI.setType(Merge.getReg(0), RealDstEltTy);
467 EltMerges.push_back(Merge.getReg(0));
468 Regs = Regs.drop_front(PartsPerElt);
469 }
470
471 B.buildBuildVector(OrigRegs[0], EltMerges);
472 } else {
473 // Vector was split, and elements promoted to a wider type.
474 // FIXME: Should handle floating point promotions.
475 LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
476 auto BV = B.buildBuildVector(BVType, Regs);
477 B.buildTrunc(OrigRegs[0], BV);
478 }
479}
480
481/// Create a sequence of instructions to expand the value in \p SrcReg (of type
482/// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
483/// contain the type of scalar value extension if necessary.
484///
485/// This is used for outgoing values (vregs to physregs)
487 Register SrcReg, LLT SrcTy, LLT PartTy,
488 unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
489 // We could just insert a regular copy, but this is unreachable at the moment.
490 assert(SrcTy != PartTy && "identical part types shouldn't reach here");
491
492 const unsigned PartSize = PartTy.getSizeInBits();
493
494 if (PartTy.isVector() == SrcTy.isVector() &&
495 PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
496 assert(DstRegs.size() == 1);
497 B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
498 return;
499 }
500
501 if (SrcTy.isVector() && !PartTy.isVector() &&
502 PartSize > SrcTy.getElementType().getSizeInBits()) {
503 // Vector was scalarized, and the elements extended.
504 auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
505 for (int i = 0, e = DstRegs.size(); i != e; ++i)
506 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
507 return;
508 }
509
510 if (SrcTy.isVector() && PartTy.isVector() &&
511 PartTy.getScalarSizeInBits() == SrcTy.getScalarSizeInBits() &&
512 SrcTy.getNumElements() < PartTy.getNumElements()) {
513 // A coercion like: v2f32 -> v4f32.
514 Register DstReg = DstRegs.front();
515 B.buildPadVectorWithUndefElements(DstReg, SrcReg);
516 return;
517 }
518
519 LLT GCDTy = getGCDType(SrcTy, PartTy);
520 if (GCDTy == PartTy) {
521 // If this already evenly divisible, we can create a simple unmerge.
522 B.buildUnmerge(DstRegs, SrcReg);
523 return;
524 }
525
526 MachineRegisterInfo &MRI = *B.getMRI();
527 LLT DstTy = MRI.getType(DstRegs[0]);
528 LLT LCMTy = getCoverTy(SrcTy, PartTy);
529
530 if (PartTy.isVector() && LCMTy == PartTy) {
531 assert(DstRegs.size() == 1);
532 B.buildPadVectorWithUndefElements(DstRegs[0], SrcReg);
533 return;
534 }
535
536 const unsigned DstSize = DstTy.getSizeInBits();
537 const unsigned SrcSize = SrcTy.getSizeInBits();
538 unsigned CoveringSize = LCMTy.getSizeInBits();
539
540 Register UnmergeSrc = SrcReg;
541
542 if (!LCMTy.isVector() && CoveringSize != SrcSize) {
543 // For scalars, it's common to be able to use a simple extension.
544 if (SrcTy.isScalar() && DstTy.isScalar()) {
545 CoveringSize = alignTo(SrcSize, DstSize);
546 LLT CoverTy = LLT::scalar(CoveringSize);
547 UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
548 } else {
549 // Widen to the common type.
550 // FIXME: This should respect the extend type
551 Register Undef = B.buildUndef(SrcTy).getReg(0);
552 SmallVector<Register, 8> MergeParts(1, SrcReg);
553 for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
554 MergeParts.push_back(Undef);
555 UnmergeSrc = B.buildMergeLikeInstr(LCMTy, MergeParts).getReg(0);
556 }
557 }
558
559 if (LCMTy.isVector() && CoveringSize != SrcSize)
560 UnmergeSrc = B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
561
562 B.buildUnmerge(DstRegs, UnmergeSrc);
563}
564
566 ValueHandler &Handler, ValueAssigner &Assigner,
568 CallingConv::ID CallConv, bool IsVarArg,
569 ArrayRef<Register> ThisReturnRegs) const {
570 MachineFunction &MF = MIRBuilder.getMF();
571 const Function &F = MF.getFunction();
573
574 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
575 if (!determineAssignments(Assigner, Args, CCInfo))
576 return false;
577
578 return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
579 ThisReturnRegs);
580}
581
583 if (Flags.isSExt())
584 return TargetOpcode::G_SEXT;
585 if (Flags.isZExt())
586 return TargetOpcode::G_ZEXT;
587 return TargetOpcode::G_ANYEXT;
588}
589
592 CCState &CCInfo) const {
593 LLVMContext &Ctx = CCInfo.getContext();
594 const CallingConv::ID CallConv = CCInfo.getCallingConv();
595
596 unsigned NumArgs = Args.size();
597 for (unsigned i = 0; i != NumArgs; ++i) {
598 EVT CurVT = EVT::getEVT(Args[i].Ty);
599
600 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT);
601
602 // If we need to split the type over multiple regs, check it's a scenario
603 // we currently support.
604 unsigned NumParts =
605 TLI->getNumRegistersForCallingConv(Ctx, CallConv, CurVT);
606
607 if (NumParts == 1) {
608 // Try to use the register type if we couldn't assign the VT.
609 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
610 Args[i].Flags[0], CCInfo))
611 return false;
612 continue;
613 }
614
615 // For incoming arguments (physregs to vregs), we could have values in
616 // physregs (or memlocs) which we want to extract and copy to vregs.
617 // During this, we might have to deal with the LLT being split across
618 // multiple regs, so we have to record this information for later.
619 //
620 // If we have outgoing args, then we have the opposite case. We have a
621 // vreg with an LLT which we want to assign to a physical location, and
622 // we might have to record that the value has to be split later.
623
624 // We're handling an incoming arg which is split over multiple regs.
625 // E.g. passing an s128 on AArch64.
626 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
627 Args[i].Flags.clear();
628
629 for (unsigned Part = 0; Part < NumParts; ++Part) {
630 ISD::ArgFlagsTy Flags = OrigFlags;
631 if (Part == 0) {
632 Flags.setSplit();
633 } else {
634 Flags.setOrigAlign(Align(1));
635 if (Part == NumParts - 1)
636 Flags.setSplitEnd();
637 }
638
639 Args[i].Flags.push_back(Flags);
640 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
641 Args[i].Flags[Part], CCInfo)) {
642 // Still couldn't assign this smaller part type for some reason.
643 return false;
644 }
645 }
646 }
647
648 return true;
649}
650
653 CCState &CCInfo,
655 MachineIRBuilder &MIRBuilder,
656 ArrayRef<Register> ThisReturnRegs) const {
657 MachineFunction &MF = MIRBuilder.getMF();
659 const Function &F = MF.getFunction();
660 const DataLayout &DL = F.getParent()->getDataLayout();
661
662 const unsigned NumArgs = Args.size();
663
664 // Stores thunks for outgoing register assignments. This is used so we delay
665 // generating register copies until mem loc assignments are done. We do this
666 // so that if the target is using the delayed stack protector feature, we can
667 // find the split point of the block accurately. E.g. if we have:
668 // G_STORE %val, %memloc
669 // $x0 = COPY %foo
670 // $x1 = COPY %bar
671 // CALL func
672 // ... then the split point for the block will correctly be at, and including,
673 // the copy to $x0. If instead the G_STORE instruction immediately precedes
674 // the CALL, then we'd prematurely choose the CALL as the split point, thus
675 // generating a split block with a CALL that uses undefined physregs.
676 SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
677
678 for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
679 assert(j < ArgLocs.size() && "Skipped too many arg locs");
680 CCValAssign &VA = ArgLocs[j];
681 assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
682
683 if (VA.needsCustom()) {
684 std::function<void()> Thunk;
685 unsigned NumArgRegs = Handler.assignCustomValue(
686 Args[i], ArrayRef(ArgLocs).slice(j), &Thunk);
687 if (Thunk)
688 DelayedOutgoingRegAssignments.emplace_back(Thunk);
689 if (!NumArgRegs)
690 return false;
691 j += NumArgRegs;
692 continue;
693 }
694
695 const MVT ValVT = VA.getValVT();
696 const MVT LocVT = VA.getLocVT();
697
698 const LLT LocTy(LocVT);
699 const LLT ValTy(ValVT);
700 const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
701 const EVT OrigVT = EVT::getEVT(Args[i].Ty);
702 const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
703
704 // Expected to be multiple regs for a single incoming arg.
705 // There should be Regs.size() ArgLocs per argument.
706 // This should be the same as getNumRegistersForCallingConv
707 const unsigned NumParts = Args[i].Flags.size();
708
709 // Now split the registers into the assigned types.
710 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
711
712 if (NumParts != 1 || NewLLT != OrigTy) {
713 // If we can't directly assign the register, we need one or more
714 // intermediate values.
715 Args[i].Regs.resize(NumParts);
716
717 // For each split register, create and assign a vreg that will store
718 // the incoming component of the larger value. These will later be
719 // merged to form the final vreg.
720 for (unsigned Part = 0; Part < NumParts; ++Part)
721 Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
722 }
723
724 assert((j + (NumParts - 1)) < ArgLocs.size() &&
725 "Too many regs for number of args");
726
727 // Coerce into outgoing value types before register assignment.
728 if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy) {
729 assert(Args[i].OrigRegs.size() == 1);
730 buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
731 ValTy, extendOpFromFlags(Args[i].Flags[0]));
732 }
733
734 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
735 for (unsigned Part = 0; Part < NumParts; ++Part) {
736 Register ArgReg = Args[i].Regs[Part];
737 // There should be Regs.size() ArgLocs per argument.
738 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
739 CCValAssign &VA = ArgLocs[j + Idx];
740 const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
741
742 if (VA.isMemLoc() && !Flags.isByVal()) {
743 // Individual pieces may have been spilled to the stack and others
744 // passed in registers.
745
746 // TODO: The memory size may be larger than the value we need to
747 // store. We may need to adjust the offset for big endian targets.
748 LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags);
749
751 Register StackAddr = Handler.getStackAddress(
752 MemTy.getSizeInBytes(), VA.getLocMemOffset(), MPO, Flags);
753
754 Handler.assignValueToAddress(Args[i], Part, StackAddr, MemTy, MPO, VA);
755 continue;
756 }
757
758 if (VA.isMemLoc() && Flags.isByVal()) {
759 assert(Args[i].Regs.size() == 1 &&
760 "didn't expect split byval pointer");
761
762 if (Handler.isIncomingArgumentHandler()) {
763 // We just need to copy the frame index value to the pointer.
765 Register StackAddr = Handler.getStackAddress(
766 Flags.getByValSize(), VA.getLocMemOffset(), MPO, Flags);
767 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
768 } else {
769 // For outgoing byval arguments, insert the implicit copy byval
770 // implies, such that writes in the callee do not modify the caller's
771 // value.
772 uint64_t MemSize = Flags.getByValSize();
773 int64_t Offset = VA.getLocMemOffset();
774
775 MachinePointerInfo DstMPO;
776 Register StackAddr =
777 Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
778
779 MachinePointerInfo SrcMPO(Args[i].OrigValue);
780 if (!Args[i].OrigValue) {
781 // We still need to accurately track the stack address space if we
782 // don't know the underlying value.
783 const LLT PtrTy = MRI.getType(StackAddr);
784 SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
785 }
786
787 Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
788 inferAlignFromPtrInfo(MF, DstMPO));
789
790 Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
791 inferAlignFromPtrInfo(MF, SrcMPO));
792
793 Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
794 DstMPO, DstAlign, SrcMPO, SrcAlign,
795 MemSize, VA);
796 }
797 continue;
798 }
799
800 assert(!VA.needsCustom() && "custom loc should have been handled already");
801
802 if (i == 0 && !ThisReturnRegs.empty() &&
803 Handler.isIncomingArgumentHandler() &&
805 Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA);
806 continue;
807 }
808
809 if (Handler.isIncomingArgumentHandler())
810 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
811 else {
812 DelayedOutgoingRegAssignments.emplace_back([=, &Handler]() {
813 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
814 });
815 }
816 }
817
818 // Now that all pieces have been assigned, re-pack the register typed values
819 // into the original value typed registers.
820 if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT) {
821 // Merge the split registers into the expected larger result vregs of
822 // the original call.
823 buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
824 LocTy, Args[i].Flags[0]);
825 }
826
827 j += NumParts - 1;
828 }
829 for (auto &Fn : DelayedOutgoingRegAssignments)
830 Fn();
831
832 return true;
833}
834
836 ArrayRef<Register> VRegs, Register DemoteReg,
837 int FI) const {
838 MachineFunction &MF = MIRBuilder.getMF();
840 const DataLayout &DL = MF.getDataLayout();
841
842 SmallVector<EVT, 4> SplitVTs;
844 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
845
846 assert(VRegs.size() == SplitVTs.size());
847
848 unsigned NumValues = SplitVTs.size();
849 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
850 Type *RetPtrTy = RetTy->getPointerTo(DL.getAllocaAddrSpace());
851 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetPtrTy), DL);
852
854
855 for (unsigned I = 0; I < NumValues; ++I) {
857 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
858 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
859 MRI.getType(VRegs[I]),
860 commonAlignment(BaseAlign, Offsets[I]));
861 MIRBuilder.buildLoad(VRegs[I], Addr, *MMO);
862 }
863}
864
866 ArrayRef<Register> VRegs,
867 Register DemoteReg) const {
868 MachineFunction &MF = MIRBuilder.getMF();
870 const DataLayout &DL = MF.getDataLayout();
871
872 SmallVector<EVT, 4> SplitVTs;
874 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
875
876 assert(VRegs.size() == SplitVTs.size());
877
878 unsigned NumValues = SplitVTs.size();
879 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
880 unsigned AS = DL.getAllocaAddrSpace();
881 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getPointerTo(AS)), DL);
882
883 MachinePointerInfo PtrInfo(AS);
884
885 for (unsigned I = 0; I < NumValues; ++I) {
887 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
888 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
889 MRI.getType(VRegs[I]),
890 commonAlignment(BaseAlign, Offsets[I]));
891 MIRBuilder.buildStore(VRegs[I], Addr, *MMO);
892 }
893}
894
896 const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
897 MachineRegisterInfo &MRI, const DataLayout &DL) const {
898 unsigned AS = DL.getAllocaAddrSpace();
899 DemoteReg = MRI.createGenericVirtualRegister(
900 LLT::pointer(AS, DL.getPointerSizeInBits(AS)));
901
902 Type *PtrTy = PointerType::get(F.getReturnType(), AS);
903
904 SmallVector<EVT, 1> ValueVTs;
905 ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs);
906
907 // NOTE: Assume that a pointer won't get split into more than one VT.
908 assert(ValueVTs.size() == 1);
909
910 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()),
913 DemoteArg.Flags[0].setSRet();
914 SplitArgs.insert(SplitArgs.begin(), DemoteArg);
915}
916
918 const CallBase &CB,
919 CallLoweringInfo &Info) const {
920 const DataLayout &DL = MIRBuilder.getDataLayout();
921 Type *RetTy = CB.getType();
922 unsigned AS = DL.getAllocaAddrSpace();
923 LLT FramePtrTy = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
924
925 int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
926 DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false);
927
928 Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0);
929 ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS),
932 DemoteArg.Flags[0].setSRet();
933
934 Info.OrigArgs.insert(Info.OrigArgs.begin(), DemoteArg);
935 Info.DemoteStackIndex = FI;
936 Info.DemoteRegister = DemoteReg;
937}
938
941 CCAssignFn *Fn) const {
942 for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
943 MVT VT = MVT::getVT(Outs[I].Ty);
944 if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo))
945 return false;
946 }
947 return true;
948}
949
951 AttributeList Attrs,
953 const DataLayout &DL) const {
954 LLVMContext &Context = RetTy->getContext();
956
957 SmallVector<EVT, 4> SplitVTs;
958 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs);
960
961 for (EVT VT : SplitVTs) {
962 unsigned NumParts =
963 TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
964 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
965 Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
966
967 for (unsigned I = 0; I < NumParts; ++I) {
968 Outs.emplace_back(PartTy, Flags);
969 }
970 }
971}
972
974 const auto &F = MF.getFunction();
975 Type *ReturnType = F.getReturnType();
976 CallingConv::ID CallConv = F.getCallingConv();
977
979 getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
980 MF.getDataLayout());
981 return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
982}
983
985 const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
986 const SmallVectorImpl<CCValAssign> &OutLocs,
987 const SmallVectorImpl<ArgInfo> &OutArgs) const {
988 for (unsigned i = 0; i < OutLocs.size(); ++i) {
989 const auto &ArgLoc = OutLocs[i];
990 // If it's not a register, it's fine.
991 if (!ArgLoc.isRegLoc())
992 continue;
993
994 MCRegister PhysReg = ArgLoc.getLocReg();
995
996 // Only look at callee-saved registers.
997 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, PhysReg))
998 continue;
999
1000 LLVM_DEBUG(
1001 dbgs()
1002 << "... Call has an argument passed in a callee-saved register.\n");
1003
1004 // Check if it was copied from.
1005 const ArgInfo &OutInfo = OutArgs[i];
1006
1007 if (OutInfo.Regs.size() > 1) {
1008 LLVM_DEBUG(
1009 dbgs() << "... Cannot handle arguments in multiple registers.\n");
1010 return false;
1011 }
1012
1013 // Check if we copy the register, walking through copies from virtual
1014 // registers. Note that getDefIgnoringCopies does not ignore copies from
1015 // physical registers.
1016 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
1017 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
1018 LLVM_DEBUG(
1019 dbgs()
1020 << "... Parameter was not copied into a VReg, cannot tail call.\n");
1021 return false;
1022 }
1023
1024 // Got a copy. Verify that it's the same as the register we want.
1025 Register CopyRHS = RegDef->getOperand(1).getReg();
1026 if (CopyRHS != PhysReg) {
1027 LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
1028 "VReg, cannot tail call.\n");
1029 return false;
1030 }
1031 }
1032
1033 return true;
1034}
1035
1037 MachineFunction &MF,
1039 ValueAssigner &CalleeAssigner,
1040 ValueAssigner &CallerAssigner) const {
1041 const Function &F = MF.getFunction();
1042 CallingConv::ID CalleeCC = Info.CallConv;
1043 CallingConv::ID CallerCC = F.getCallingConv();
1044
1045 if (CallerCC == CalleeCC)
1046 return true;
1047
1049 CCState CCInfo1(CalleeCC, Info.IsVarArg, MF, ArgLocs1, F.getContext());
1050 if (!determineAssignments(CalleeAssigner, InArgs, CCInfo1))
1051 return false;
1052
1054 CCState CCInfo2(CallerCC, F.isVarArg(), MF, ArgLocs2, F.getContext());
1055 if (!determineAssignments(CallerAssigner, InArgs, CCInfo2))
1056 return false;
1057
1058 // We need the argument locations to match up exactly. If there's more in
1059 // one than the other, then we are done.
1060 if (ArgLocs1.size() != ArgLocs2.size())
1061 return false;
1062
1063 // Make sure that each location is passed in exactly the same way.
1064 for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
1065 const CCValAssign &Loc1 = ArgLocs1[i];
1066 const CCValAssign &Loc2 = ArgLocs2[i];
1067
1068 // We need both of them to be the same. So if one is a register and one
1069 // isn't, we're done.
1070 if (Loc1.isRegLoc() != Loc2.isRegLoc())
1071 return false;
1072
1073 if (Loc1.isRegLoc()) {
1074 // If they don't have the same register location, we're done.
1075 if (Loc1.getLocReg() != Loc2.getLocReg())
1076 return false;
1077
1078 // They matched, so we can move to the next ArgLoc.
1079 continue;
1080 }
1081
1082 // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
1083 if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
1084 return false;
1085 }
1086
1087 return true;
1088}
1089
1091 const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const {
1092 const MVT ValVT = VA.getValVT();
1093 if (ValVT != MVT::iPTR) {
1094 LLT ValTy(ValVT);
1095
1096 // We lost the pointeriness going through CCValAssign, so try to restore it
1097 // based on the flags.
1098 if (Flags.isPointer()) {
1099 LLT PtrTy = LLT::pointer(Flags.getPointerAddrSpace(),
1100 ValTy.getScalarSizeInBits());
1101 if (ValVT.isVector())
1102 return LLT::vector(ValTy.getElementCount(), PtrTy);
1103 return PtrTy;
1104 }
1105
1106 return ValTy;
1107 }
1108
1109 unsigned AddrSpace = Flags.getPointerAddrSpace();
1110 return LLT::pointer(AddrSpace, DL.getPointerSize(AddrSpace));
1111}
1112
1114 const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
1115 const MachinePointerInfo &DstPtrInfo, Align DstAlign,
1116 const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
1117 CCValAssign &VA) const {
1118 MachineFunction &MF = MIRBuilder.getMF();
1120 SrcPtrInfo,
1122 SrcAlign);
1123
1125 DstPtrInfo,
1127 MemSize, DstAlign);
1128
1129 const LLT PtrTy = MRI.getType(DstPtr);
1130 const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
1131
1132 auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
1133 MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1134}
1135
1137 CCValAssign &VA,
1138 unsigned MaxSizeBits) {
1139 LLT LocTy{VA.getLocVT()};
1140 LLT ValTy{VA.getValVT()};
1141
1142 if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1143 return ValReg;
1144
1145 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1146 if (MaxSizeBits <= ValTy.getSizeInBits())
1147 return ValReg;
1148 LocTy = LLT::scalar(MaxSizeBits);
1149 }
1150
1151 const LLT ValRegTy = MRI.getType(ValReg);
1152 if (ValRegTy.isPointer()) {
1153 // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1154 // we have to cast to do the extension.
1155 LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits());
1156 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0);
1157 }
1158
1159 switch (VA.getLocInfo()) {
1160 default: break;
1161 case CCValAssign::Full:
1162 case CCValAssign::BCvt:
1163 // FIXME: bitconverting between vector types may or may not be a
1164 // nop in big-endian situations.
1165 return ValReg;
1166 case CCValAssign::AExt: {
1167 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1168 return MIB.getReg(0);
1169 }
1170 case CCValAssign::SExt: {
1171 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1172 MIRBuilder.buildSExt(NewReg, ValReg);
1173 return NewReg;
1174 }
1175 case CCValAssign::ZExt: {
1176 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1177 MIRBuilder.buildZExt(NewReg, ValReg);
1178 return NewReg;
1179 }
1180 }
1181 llvm_unreachable("unable to extend register");
1182}
1183
1184void CallLowering::ValueAssigner::anchor() {}
1185
1187 Register SrcReg,
1188 LLT NarrowTy) {
1189 switch (VA.getLocInfo()) {
1191 return MIRBuilder
1192 .buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1193 NarrowTy.getScalarSizeInBits())
1194 .getReg(0);
1195 }
1197 return MIRBuilder
1198 .buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1199 NarrowTy.getScalarSizeInBits())
1200 .getReg(0);
1201 break;
1202 }
1203 default:
1204 return SrcReg;
1205 }
1206}
1207
1208/// Check if we can use a basic COPY instruction between the two types.
1209///
1210/// We're currently building on top of the infrastructure using MVT, which loses
1211/// pointer information in the CCValAssign. We accept copies from physical
1212/// registers that have been reported as integers if it's to an equivalent sized
1213/// pointer LLT.
1214static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
1215 if (SrcTy == DstTy)
1216 return true;
1217
1218 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1219 return false;
1220
1221 SrcTy = SrcTy.getScalarType();
1222 DstTy = DstTy.getScalarType();
1223
1224 return (SrcTy.isPointer() && DstTy.isScalar()) ||
1225 (DstTy.isPointer() && SrcTy.isScalar());
1226}
1227
1229 Register PhysReg,
1230 CCValAssign VA) {
1231 const MVT LocVT = VA.getLocVT();
1232 const LLT LocTy(LocVT);
1233 const LLT RegTy = MRI.getType(ValVReg);
1234
1235 if (isCopyCompatibleType(RegTy, LocTy)) {
1236 MIRBuilder.buildCopy(ValVReg, PhysReg);
1237 return;
1238 }
1239
1240 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
1241 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
1242 MIRBuilder.buildTrunc(ValVReg, Hint);
1243}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT, const ISD::ArgFlagsTy Flags)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy)
Check if we can use a basic COPY instruction between the two types.
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
This file describes how to lower LLVM calls to machine code calls.
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Addr
uint64_t Size
static unsigned NumFixedArgs
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
R600 Clause Merge
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:228
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:204
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:168
iterator end() const
Definition: ArrayRef.h:154
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
iterator begin() const
Definition: ArrayRef.h:153
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
Definition: Attributes.h:84
CCState - This class holds information needed while lowering arguments and return values.
CallingConv::ID getCallingConv() const
LLVMContext & getContext() const
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool needsCustom() const
bool isMemLoc() const
int64_t getLocMemOffset() const
unsigned getValNo() const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1190
MaybeAlign getRetAlign() const
Extract the alignment of the return value.
Definition: InstrTypes.h:1753
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
Definition: InstrTypes.h:2054
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1470
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
Value * getCalledOperand() const
Definition: InstrTypes.h:1405
bool isConvergent() const
Determine if the invoke is convergent.
Definition: InstrTypes.h:1938
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1270
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1348
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1489
bool isTailCall() const
Tests if this call site is marked as a tail call.
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: CallLowering.h:494
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: CallLowering.h:594
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
Definition: CallLowering.h:342
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:554
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
ISD::ArgFlagsTy getAttributesForReturn(const CallBase &Call) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:139
bool isVarArg() const
Definition: DerivedTypes.h:123
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:671
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:302
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:249
constexpr bool isScalar() const
Definition: LowLevelType.h:139
constexpr LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
Definition: LowLevelType.h:196
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelType.h:56
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:149
constexpr bool isVector() const
Definition: LowLevelType.h:145
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:49
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:175
constexpr bool isPointer() const
Definition: LowLevelType.h:141
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:272
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:166
constexpr unsigned getAddressSpace() const
Definition: LowLevelType.h:262
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:92
constexpr LLT changeElementCount(ElementCount EC) const
Return a vector or scalar with the same element type and the new element count.
Definition: LowLevelType.h:212
constexpr LLT getScalarType() const
Definition: LowLevelType.h:190
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:185
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:573
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Class to represent pointers.
Definition: DerivedTypes.h:643
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:809
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:688
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:182
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< TypeSize > *Offsets, TypeSize StartingOffset)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:122
@ Offset
Definition: DWP.cpp:440
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:972
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:572
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:987
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:716
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
const Value * OrigValue
Optionally track the original IR value for the argument.
Definition: CallLowering.h:73
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
unsigned OrigArgIndex
Index original Function's argument.
Definition: CallLowering.h:76
static const unsigned NoArgIndex
Sentinel value for implicit machine-level input arguments.
Definition: CallLowering.h:79
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
Provides a default implementation for argument handling.
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:164
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:188
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, MachinePointerInfo &MPO, CCValAssign &VA)=0
The specified value has been assigned to a stack location.
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
Definition: CallLowering.h:245
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:297
virtual void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:616
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:194
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117