LLVM 19.0.0git
CallLowering.cpp
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1//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements some simple delegations needed for call lowering.
11///
12//===----------------------------------------------------------------------===//
13
23#include "llvm/IR/DataLayout.h"
24#include "llvm/IR/LLVMContext.h"
25#include "llvm/IR/Module.h"
27
28#define DEBUG_TYPE "call-lowering"
29
30using namespace llvm;
31
32void CallLowering::anchor() {}
33
34/// Helper function which updates \p Flags when \p AttrFn returns true.
35static void
37 const std::function<bool(Attribute::AttrKind)> &AttrFn) {
38 if (AttrFn(Attribute::SExt))
39 Flags.setSExt();
40 if (AttrFn(Attribute::ZExt))
41 Flags.setZExt();
42 if (AttrFn(Attribute::InReg))
43 Flags.setInReg();
44 if (AttrFn(Attribute::StructRet))
45 Flags.setSRet();
46 if (AttrFn(Attribute::Nest))
47 Flags.setNest();
48 if (AttrFn(Attribute::ByVal))
49 Flags.setByVal();
50 if (AttrFn(Attribute::Preallocated))
51 Flags.setPreallocated();
52 if (AttrFn(Attribute::InAlloca))
53 Flags.setInAlloca();
54 if (AttrFn(Attribute::Returned))
55 Flags.setReturned();
56 if (AttrFn(Attribute::SwiftSelf))
57 Flags.setSwiftSelf();
58 if (AttrFn(Attribute::SwiftAsync))
59 Flags.setSwiftAsync();
60 if (AttrFn(Attribute::SwiftError))
61 Flags.setSwiftError();
62}
63
65 unsigned ArgIdx) const {
66 ISD::ArgFlagsTy Flags;
67 addFlagsUsingAttrFn(Flags, [&Call, &ArgIdx](Attribute::AttrKind Attr) {
68 return Call.paramHasAttr(ArgIdx, Attr);
69 });
70 return Flags;
71}
72
75 ISD::ArgFlagsTy Flags;
76 addFlagsUsingAttrFn(Flags, [&Call](Attribute::AttrKind Attr) {
77 return Call.hasRetAttr(Attr);
78 });
79 return Flags;
80}
81
83 const AttributeList &Attrs,
84 unsigned OpIdx) const {
85 addFlagsUsingAttrFn(Flags, [&Attrs, &OpIdx](Attribute::AttrKind Attr) {
86 return Attrs.hasAttributeAtIndex(OpIdx, Attr);
87 });
88}
89
91 ArrayRef<Register> ResRegs,
93 Register SwiftErrorVReg,
94 std::function<unsigned()> GetCalleeReg) const {
96 const DataLayout &DL = MIRBuilder.getDataLayout();
97 MachineFunction &MF = MIRBuilder.getMF();
99 bool CanBeTailCalled = CB.isTailCall() &&
101 (MF.getFunction()
102 .getFnAttribute("disable-tail-calls")
103 .getValueAsString() != "true");
104
105 CallingConv::ID CallConv = CB.getCallingConv();
106 Type *RetTy = CB.getType();
107 bool IsVarArg = CB.getFunctionType()->isVarArg();
108
110 getReturnInfo(CallConv, RetTy, CB.getAttributes(), SplitArgs, DL);
111 Info.CanLowerReturn = canLowerReturn(MF, CallConv, SplitArgs, IsVarArg);
112
113 Info.IsConvergent = CB.isConvergent();
114
115 if (!Info.CanLowerReturn) {
116 // Callee requires sret demotion.
117 insertSRetOutgoingArgument(MIRBuilder, CB, Info);
118
119 // The sret demotion isn't compatible with tail-calls, since the sret
120 // argument points into the caller's stack frame.
121 CanBeTailCalled = false;
122 }
123
124
125 // First step is to marshall all the function's parameters into the correct
126 // physregs and memory locations. Gather the sequence of argument types that
127 // we'll pass to the assigner function.
128 unsigned i = 0;
129 unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
130 for (const auto &Arg : CB.args()) {
131 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i),
132 i < NumFixedArgs};
134
135 // If we have an explicit sret argument that is an Instruction, (i.e., it
136 // might point to function-local memory), we can't meaningfully tail-call.
137 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg))
138 CanBeTailCalled = false;
139
140 Info.OrigArgs.push_back(OrigArg);
141 ++i;
142 }
143
144 // Try looking through a bitcast from one function type to another.
145 // Commonly happens with calls to objc_msgSend().
146 const Value *CalleeV = CB.getCalledOperand()->stripPointerCasts();
147 if (const Function *F = dyn_cast<Function>(CalleeV))
148 Info.Callee = MachineOperand::CreateGA(F, 0);
149 else if (isa<GlobalIFunc>(CalleeV) || isa<GlobalAlias>(CalleeV)) {
150 // IR IFuncs and Aliases can't be forward declared (only defined), so the
151 // callee must be in the same TU and therefore we can direct-call it without
152 // worrying about it being out of range.
153 Info.Callee = MachineOperand::CreateGA(cast<GlobalValue>(CalleeV), 0);
154 } else
155 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
156
157 Register ReturnHintAlignReg;
158 Align ReturnHintAlign;
159
160 Info.OrigRet = ArgInfo{ResRegs, RetTy, 0, getAttributesForReturn(CB)};
161
162 if (!Info.OrigRet.Ty->isVoidTy()) {
164
165 if (MaybeAlign Alignment = CB.getRetAlign()) {
166 if (*Alignment > Align(1)) {
167 ReturnHintAlignReg = MRI.cloneVirtualRegister(ResRegs[0]);
168 Info.OrigRet.Regs[0] = ReturnHintAlignReg;
169 ReturnHintAlign = *Alignment;
170 }
171 }
172 }
173
174 auto Bundle = CB.getOperandBundle(LLVMContext::OB_kcfi);
175 if (Bundle && CB.isIndirectCall()) {
176 Info.CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
177 assert(Info.CFIType->getType()->isIntegerTy(32) && "Invalid CFI type");
178 }
179
180 Info.CB = &CB;
181 Info.KnownCallees = CB.getMetadata(LLVMContext::MD_callees);
182 Info.CallConv = CallConv;
183 Info.SwiftErrorVReg = SwiftErrorVReg;
184 Info.IsMustTailCall = CB.isMustTailCall();
185 Info.IsTailCall = CanBeTailCalled;
186 Info.IsVarArg = IsVarArg;
187 if (!lowerCall(MIRBuilder, Info))
188 return false;
189
190 if (ReturnHintAlignReg && !Info.LoweredTailCall) {
191 MIRBuilder.buildAssertAlign(ResRegs[0], ReturnHintAlignReg,
192 ReturnHintAlign);
193 }
194
195 return true;
196}
197
198template <typename FuncInfoTy>
200 const DataLayout &DL,
201 const FuncInfoTy &FuncInfo) const {
202 auto &Flags = Arg.Flags[0];
203 const AttributeList &Attrs = FuncInfo.getAttributes();
204 addArgFlagsFromAttributes(Flags, Attrs, OpIdx);
205
206 PointerType *PtrTy = dyn_cast<PointerType>(Arg.Ty->getScalarType());
207 if (PtrTy) {
208 Flags.setPointer();
209 Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace());
210 }
211
212 Align MemAlign = DL.getABITypeAlign(Arg.Ty);
213 if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) {
215 unsigned ParamIdx = OpIdx - AttributeList::FirstArgIndex;
216
217 Type *ElementTy = FuncInfo.getParamByValType(ParamIdx);
218 if (!ElementTy)
219 ElementTy = FuncInfo.getParamInAllocaType(ParamIdx);
220 if (!ElementTy)
221 ElementTy = FuncInfo.getParamPreallocatedType(ParamIdx);
222 assert(ElementTy && "Must have byval, inalloca or preallocated type");
223 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
224
225 // For ByVal, alignment should be passed from FE. BE will guess if
226 // this info is not there but there are cases it cannot get right.
227 if (auto ParamAlign = FuncInfo.getParamStackAlign(ParamIdx))
228 MemAlign = *ParamAlign;
229 else if ((ParamAlign = FuncInfo.getParamAlign(ParamIdx)))
230 MemAlign = *ParamAlign;
231 else
232 MemAlign = Align(getTLI()->getByValTypeAlignment(ElementTy, DL));
233 } else if (OpIdx >= AttributeList::FirstArgIndex) {
234 if (auto ParamAlign =
235 FuncInfo.getParamStackAlign(OpIdx - AttributeList::FirstArgIndex))
236 MemAlign = *ParamAlign;
237 }
238 Flags.setMemAlign(MemAlign);
239 Flags.setOrigAlign(DL.getABITypeAlign(Arg.Ty));
240
241 // Don't try to use the returned attribute if the argument is marked as
242 // swiftself, since it won't be passed in x0.
243 if (Flags.isSwiftSelf())
244 Flags.setReturned(false);
245}
246
247template void
248CallLowering::setArgFlags<Function>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
249 const DataLayout &DL,
250 const Function &FuncInfo) const;
251
252template void
253CallLowering::setArgFlags<CallBase>(CallLowering::ArgInfo &Arg, unsigned OpIdx,
254 const DataLayout &DL,
255 const CallBase &FuncInfo) const;
256
258 SmallVectorImpl<ArgInfo> &SplitArgs,
259 const DataLayout &DL,
260 CallingConv::ID CallConv,
261 SmallVectorImpl<uint64_t> *Offsets) const {
262 LLVMContext &Ctx = OrigArg.Ty->getContext();
263
264 SmallVector<EVT, 4> SplitVTs;
265 ComputeValueVTs(*TLI, DL, OrigArg.Ty, SplitVTs, Offsets, 0);
266
267 if (SplitVTs.size() == 0)
268 return;
269
270 if (SplitVTs.size() == 1) {
271 // No splitting to do, but we want to replace the original type (e.g. [1 x
272 // double] -> double).
273 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
274 OrigArg.OrigArgIndex, OrigArg.Flags[0],
275 OrigArg.IsFixed, OrigArg.OrigValue);
276 return;
277 }
278
279 // Create one ArgInfo for each virtual register in the original ArgInfo.
280 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
281
282 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
283 OrigArg.Ty, CallConv, false, DL);
284 for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
285 Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
286 SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.OrigArgIndex,
287 OrigArg.Flags[0], OrigArg.IsFixed);
288 if (NeedsRegBlock)
289 SplitArgs.back().Flags[0].setInConsecutiveRegs();
290 }
291
292 SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
293}
294
295/// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
298 ArrayRef<Register> SrcRegs) {
299 MachineRegisterInfo &MRI = *B.getMRI();
300 LLT LLTy = MRI.getType(DstRegs[0]);
301 LLT PartLLT = MRI.getType(SrcRegs[0]);
302
303 // Deal with v3s16 split into v2s16
304 LLT LCMTy = getCoverTy(LLTy, PartLLT);
305 if (LCMTy == LLTy) {
306 // Common case where no padding is needed.
307 assert(DstRegs.size() == 1);
308 return B.buildConcatVectors(DstRegs[0], SrcRegs);
309 }
310
311 // We need to create an unmerge to the result registers, which may require
312 // widening the original value.
313 Register UnmergeSrcReg;
314 if (LCMTy != PartLLT) {
315 assert(DstRegs.size() == 1);
316 return B.buildDeleteTrailingVectorElements(
317 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs));
318 } else {
319 // We don't need to widen anything if we're extracting a scalar which was
320 // promoted to a vector e.g. s8 -> v4s8 -> s8
321 assert(SrcRegs.size() == 1);
322 UnmergeSrcReg = SrcRegs[0];
323 }
324
325 int NumDst = LCMTy.getSizeInBits() / LLTy.getSizeInBits();
326
327 SmallVector<Register, 8> PadDstRegs(NumDst);
328 std::copy(DstRegs.begin(), DstRegs.end(), PadDstRegs.begin());
329
330 // Create the excess dead defs for the unmerge.
331 for (int I = DstRegs.size(); I != NumDst; ++I)
332 PadDstRegs[I] = MRI.createGenericVirtualRegister(LLTy);
333
334 if (PadDstRegs.size() == 1)
335 return B.buildDeleteTrailingVectorElements(DstRegs[0], UnmergeSrcReg);
336 return B.buildUnmerge(PadDstRegs, UnmergeSrcReg);
337}
338
339/// Create a sequence of instructions to combine pieces split into register
340/// typed values to the original IR value. \p OrigRegs contains the destination
341/// value registers of type \p LLTy, and \p Regs contains the legalized pieces
342/// with type \p PartLLT. This is used for incoming values (physregs to vregs).
344 ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT,
345 const ISD::ArgFlagsTy Flags) {
346 MachineRegisterInfo &MRI = *B.getMRI();
347
348 if (PartLLT == LLTy) {
349 // We should have avoided introducing a new virtual register, and just
350 // directly assigned here.
351 assert(OrigRegs[0] == Regs[0]);
352 return;
353 }
354
355 if (PartLLT.getSizeInBits() == LLTy.getSizeInBits() && OrigRegs.size() == 1 &&
356 Regs.size() == 1) {
357 B.buildBitcast(OrigRegs[0], Regs[0]);
358 return;
359 }
360
361 // A vector PartLLT needs extending to LLTy's element size.
362 // E.g. <2 x s64> = G_SEXT <2 x s32>.
363 if (PartLLT.isVector() == LLTy.isVector() &&
364 PartLLT.getScalarSizeInBits() > LLTy.getScalarSizeInBits() &&
365 (!PartLLT.isVector() ||
366 PartLLT.getElementCount() == LLTy.getElementCount()) &&
367 OrigRegs.size() == 1 && Regs.size() == 1) {
368 Register SrcReg = Regs[0];
369
370 LLT LocTy = MRI.getType(SrcReg);
371
372 if (Flags.isSExt()) {
373 SrcReg = B.buildAssertSExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
374 .getReg(0);
375 } else if (Flags.isZExt()) {
376 SrcReg = B.buildAssertZExt(LocTy, SrcReg, LLTy.getScalarSizeInBits())
377 .getReg(0);
378 }
379
380 // Sometimes pointers are passed zero extended.
381 LLT OrigTy = MRI.getType(OrigRegs[0]);
382 if (OrigTy.isPointer()) {
383 LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits());
384 B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg));
385 return;
386 }
387
388 B.buildTrunc(OrigRegs[0], SrcReg);
389 return;
390 }
391
392 if (!LLTy.isVector() && !PartLLT.isVector()) {
393 assert(OrigRegs.size() == 1);
394 LLT OrigTy = MRI.getType(OrigRegs[0]);
395
396 unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
397 if (SrcSize == OrigTy.getSizeInBits())
398 B.buildMergeValues(OrigRegs[0], Regs);
399 else {
400 auto Widened = B.buildMergeLikeInstr(LLT::scalar(SrcSize), Regs);
401 B.buildTrunc(OrigRegs[0], Widened);
402 }
403
404 return;
405 }
406
407 if (PartLLT.isVector()) {
408 assert(OrigRegs.size() == 1);
409 SmallVector<Register> CastRegs(Regs.begin(), Regs.end());
410
411 // If PartLLT is a mismatched vector in both number of elements and element
412 // size, e.g. PartLLT == v2s64 and LLTy is v3s32, then first coerce it to
413 // have the same elt type, i.e. v4s32.
414 // TODO: Extend this coersion to element multiples other than just 2.
415 if (TypeSize::isKnownGT(PartLLT.getSizeInBits(), LLTy.getSizeInBits()) &&
416 PartLLT.getScalarSizeInBits() == LLTy.getScalarSizeInBits() * 2 &&
417 Regs.size() == 1) {
418 LLT NewTy = PartLLT.changeElementType(LLTy.getElementType())
419 .changeElementCount(PartLLT.getElementCount() * 2);
420 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0);
421 PartLLT = NewTy;
422 }
423
424 if (LLTy.getScalarType() == PartLLT.getElementType()) {
425 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
426 } else {
427 unsigned I = 0;
428 LLT GCDTy = getGCDType(LLTy, PartLLT);
429
430 // We are both splitting a vector, and bitcasting its element types. Cast
431 // the source pieces into the appropriate number of pieces with the result
432 // element type.
433 for (Register SrcReg : CastRegs)
434 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0);
435 mergeVectorRegsToResultRegs(B, OrigRegs, CastRegs);
436 }
437
438 return;
439 }
440
441 assert(LLTy.isVector() && !PartLLT.isVector());
442
443 LLT DstEltTy = LLTy.getElementType();
444
445 // Pointer information was discarded. We'll need to coerce some register types
446 // to avoid violating type constraints.
447 LLT RealDstEltTy = MRI.getType(OrigRegs[0]).getElementType();
448
449 assert(DstEltTy.getSizeInBits() == RealDstEltTy.getSizeInBits());
450
451 if (DstEltTy == PartLLT) {
452 // Vector was trivially scalarized.
453
454 if (RealDstEltTy.isPointer()) {
455 for (Register Reg : Regs)
456 MRI.setType(Reg, RealDstEltTy);
457 }
458
459 B.buildBuildVector(OrigRegs[0], Regs);
460 } else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
461 // Deal with vector with 64-bit elements decomposed to 32-bit
462 // registers. Need to create intermediate 64-bit elements.
463 SmallVector<Register, 8> EltMerges;
464 int PartsPerElt = DstEltTy.getSizeInBits() / PartLLT.getSizeInBits();
465
466 assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
467
468 for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
469 auto Merge =
470 B.buildMergeLikeInstr(RealDstEltTy, Regs.take_front(PartsPerElt));
471 // Fix the type in case this is really a vector of pointers.
472 MRI.setType(Merge.getReg(0), RealDstEltTy);
473 EltMerges.push_back(Merge.getReg(0));
474 Regs = Regs.drop_front(PartsPerElt);
475 }
476
477 B.buildBuildVector(OrigRegs[0], EltMerges);
478 } else {
479 // Vector was split, and elements promoted to a wider type.
480 // FIXME: Should handle floating point promotions.
481 unsigned NumElts = LLTy.getNumElements();
482 LLT BVType = LLT::fixed_vector(NumElts, PartLLT);
483
484 Register BuildVec;
485 if (NumElts == Regs.size())
486 BuildVec = B.buildBuildVector(BVType, Regs).getReg(0);
487 else {
488 // Vector elements are packed in the inputs.
489 // e.g. we have a <4 x s16> but 2 x s32 in regs.
490 assert(NumElts > Regs.size());
491 LLT SrcEltTy = MRI.getType(Regs[0]);
492
493 LLT OriginalEltTy = MRI.getType(OrigRegs[0]).getElementType();
494
495 // Input registers contain packed elements.
496 // Determine how many elements per reg.
497 assert((SrcEltTy.getSizeInBits() % OriginalEltTy.getSizeInBits()) == 0);
498 unsigned EltPerReg =
499 (SrcEltTy.getSizeInBits() / OriginalEltTy.getSizeInBits());
500
502 BVRegs.reserve(Regs.size() * EltPerReg);
503 for (Register R : Regs) {
504 auto Unmerge = B.buildUnmerge(OriginalEltTy, R);
505 for (unsigned K = 0; K < EltPerReg; ++K)
506 BVRegs.push_back(B.buildAnyExt(PartLLT, Unmerge.getReg(K)).getReg(0));
507 }
508
509 // We may have some more elements in BVRegs, e.g. if we have 2 s32 pieces
510 // for a <3 x s16> vector. We should have less than EltPerReg extra items.
511 if (BVRegs.size() > NumElts) {
512 assert((BVRegs.size() - NumElts) < EltPerReg);
513 BVRegs.truncate(NumElts);
514 }
515 BuildVec = B.buildBuildVector(BVType, BVRegs).getReg(0);
516 }
517 B.buildTrunc(OrigRegs[0], BuildVec);
518 }
519}
520
521/// Create a sequence of instructions to expand the value in \p SrcReg (of type
522/// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
523/// contain the type of scalar value extension if necessary.
524///
525/// This is used for outgoing values (vregs to physregs)
527 Register SrcReg, LLT SrcTy, LLT PartTy,
528 unsigned ExtendOp = TargetOpcode::G_ANYEXT) {
529 // We could just insert a regular copy, but this is unreachable at the moment.
530 assert(SrcTy != PartTy && "identical part types shouldn't reach here");
531
532 const TypeSize PartSize = PartTy.getSizeInBits();
533
534 if (PartTy.isVector() == SrcTy.isVector() &&
535 PartTy.getScalarSizeInBits() > SrcTy.getScalarSizeInBits()) {
536 assert(DstRegs.size() == 1);
537 B.buildInstr(ExtendOp, {DstRegs[0]}, {SrcReg});
538 return;
539 }
540
541 if (SrcTy.isVector() && !PartTy.isVector() &&
542 TypeSize::isKnownGT(PartSize, SrcTy.getElementType().getSizeInBits())) {
543 // Vector was scalarized, and the elements extended.
544 auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(), SrcReg);
545 for (int i = 0, e = DstRegs.size(); i != e; ++i)
546 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
547 return;
548 }
549
550 if (SrcTy.isVector() && PartTy.isVector() &&
551 PartTy.getSizeInBits() == SrcTy.getSizeInBits() &&
553 PartTy.getElementCount())) {
554 // A coercion like: v2f32 -> v4f32 or nxv2f32 -> nxv4f32
555 Register DstReg = DstRegs.front();
556 B.buildPadVectorWithUndefElements(DstReg, SrcReg);
557 return;
558 }
559
560 LLT GCDTy = getGCDType(SrcTy, PartTy);
561 if (GCDTy == PartTy) {
562 // If this already evenly divisible, we can create a simple unmerge.
563 B.buildUnmerge(DstRegs, SrcReg);
564 return;
565 }
566
567 MachineRegisterInfo &MRI = *B.getMRI();
568 LLT DstTy = MRI.getType(DstRegs[0]);
569 LLT LCMTy = getCoverTy(SrcTy, PartTy);
570
571 if (PartTy.isVector() && LCMTy == PartTy) {
572 assert(DstRegs.size() == 1);
573 B.buildPadVectorWithUndefElements(DstRegs[0], SrcReg);
574 return;
575 }
576
577 const unsigned DstSize = DstTy.getSizeInBits();
578 const unsigned SrcSize = SrcTy.getSizeInBits();
579 unsigned CoveringSize = LCMTy.getSizeInBits();
580
581 Register UnmergeSrc = SrcReg;
582
583 if (!LCMTy.isVector() && CoveringSize != SrcSize) {
584 // For scalars, it's common to be able to use a simple extension.
585 if (SrcTy.isScalar() && DstTy.isScalar()) {
586 CoveringSize = alignTo(SrcSize, DstSize);
587 LLT CoverTy = LLT::scalar(CoveringSize);
588 UnmergeSrc = B.buildInstr(ExtendOp, {CoverTy}, {SrcReg}).getReg(0);
589 } else {
590 // Widen to the common type.
591 // FIXME: This should respect the extend type
592 Register Undef = B.buildUndef(SrcTy).getReg(0);
593 SmallVector<Register, 8> MergeParts(1, SrcReg);
594 for (unsigned Size = SrcSize; Size != CoveringSize; Size += SrcSize)
595 MergeParts.push_back(Undef);
596 UnmergeSrc = B.buildMergeLikeInstr(LCMTy, MergeParts).getReg(0);
597 }
598 }
599
600 if (LCMTy.isVector() && CoveringSize != SrcSize)
601 UnmergeSrc = B.buildPadVectorWithUndefElements(LCMTy, SrcReg).getReg(0);
602
603 B.buildUnmerge(DstRegs, UnmergeSrc);
604}
605
607 ValueHandler &Handler, ValueAssigner &Assigner,
609 CallingConv::ID CallConv, bool IsVarArg,
610 ArrayRef<Register> ThisReturnRegs) const {
611 MachineFunction &MF = MIRBuilder.getMF();
612 const Function &F = MF.getFunction();
614
615 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, F.getContext());
616 if (!determineAssignments(Assigner, Args, CCInfo))
617 return false;
618
619 return handleAssignments(Handler, Args, CCInfo, ArgLocs, MIRBuilder,
620 ThisReturnRegs);
621}
622
624 if (Flags.isSExt())
625 return TargetOpcode::G_SEXT;
626 if (Flags.isZExt())
627 return TargetOpcode::G_ZEXT;
628 return TargetOpcode::G_ANYEXT;
629}
630
633 CCState &CCInfo) const {
634 LLVMContext &Ctx = CCInfo.getContext();
635 const CallingConv::ID CallConv = CCInfo.getCallingConv();
636
637 unsigned NumArgs = Args.size();
638 for (unsigned i = 0; i != NumArgs; ++i) {
639 EVT CurVT = EVT::getEVT(Args[i].Ty);
640
641 MVT NewVT = TLI->getRegisterTypeForCallingConv(Ctx, CallConv, CurVT);
642
643 // If we need to split the type over multiple regs, check it's a scenario
644 // we currently support.
645 unsigned NumParts =
646 TLI->getNumRegistersForCallingConv(Ctx, CallConv, CurVT);
647
648 if (NumParts == 1) {
649 // Try to use the register type if we couldn't assign the VT.
650 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
651 Args[i].Flags[0], CCInfo))
652 return false;
653 continue;
654 }
655
656 // For incoming arguments (physregs to vregs), we could have values in
657 // physregs (or memlocs) which we want to extract and copy to vregs.
658 // During this, we might have to deal with the LLT being split across
659 // multiple regs, so we have to record this information for later.
660 //
661 // If we have outgoing args, then we have the opposite case. We have a
662 // vreg with an LLT which we want to assign to a physical location, and
663 // we might have to record that the value has to be split later.
664
665 // We're handling an incoming arg which is split over multiple regs.
666 // E.g. passing an s128 on AArch64.
667 ISD::ArgFlagsTy OrigFlags = Args[i].Flags[0];
668 Args[i].Flags.clear();
669
670 for (unsigned Part = 0; Part < NumParts; ++Part) {
671 ISD::ArgFlagsTy Flags = OrigFlags;
672 if (Part == 0) {
673 Flags.setSplit();
674 } else {
675 Flags.setOrigAlign(Align(1));
676 if (Part == NumParts - 1)
677 Flags.setSplitEnd();
678 }
679
680 Args[i].Flags.push_back(Flags);
681 if (Assigner.assignArg(i, CurVT, NewVT, NewVT, CCValAssign::Full, Args[i],
682 Args[i].Flags[Part], CCInfo)) {
683 // Still couldn't assign this smaller part type for some reason.
684 return false;
685 }
686 }
687 }
688
689 return true;
690}
691
694 CCState &CCInfo,
696 MachineIRBuilder &MIRBuilder,
697 ArrayRef<Register> ThisReturnRegs) const {
698 MachineFunction &MF = MIRBuilder.getMF();
700 const Function &F = MF.getFunction();
701 const DataLayout &DL = F.getParent()->getDataLayout();
702
703 const unsigned NumArgs = Args.size();
704
705 // Stores thunks for outgoing register assignments. This is used so we delay
706 // generating register copies until mem loc assignments are done. We do this
707 // so that if the target is using the delayed stack protector feature, we can
708 // find the split point of the block accurately. E.g. if we have:
709 // G_STORE %val, %memloc
710 // $x0 = COPY %foo
711 // $x1 = COPY %bar
712 // CALL func
713 // ... then the split point for the block will correctly be at, and including,
714 // the copy to $x0. If instead the G_STORE instruction immediately precedes
715 // the CALL, then we'd prematurely choose the CALL as the split point, thus
716 // generating a split block with a CALL that uses undefined physregs.
717 SmallVector<std::function<void()>> DelayedOutgoingRegAssignments;
718
719 for (unsigned i = 0, j = 0; i != NumArgs; ++i, ++j) {
720 assert(j < ArgLocs.size() && "Skipped too many arg locs");
721 CCValAssign &VA = ArgLocs[j];
722 assert(VA.getValNo() == i && "Location doesn't correspond to current arg");
723
724 if (VA.needsCustom()) {
725 std::function<void()> Thunk;
726 unsigned NumArgRegs = Handler.assignCustomValue(
727 Args[i], ArrayRef(ArgLocs).slice(j), &Thunk);
728 if (Thunk)
729 DelayedOutgoingRegAssignments.emplace_back(Thunk);
730 if (!NumArgRegs)
731 return false;
732 j += (NumArgRegs - 1);
733 continue;
734 }
735
736 const MVT ValVT = VA.getValVT();
737 const MVT LocVT = VA.getLocVT();
738
739 const LLT LocTy(LocVT);
740 const LLT ValTy(ValVT);
741 const LLT NewLLT = Handler.isIncomingArgumentHandler() ? LocTy : ValTy;
742 const EVT OrigVT = EVT::getEVT(Args[i].Ty);
743 const LLT OrigTy = getLLTForType(*Args[i].Ty, DL);
744
745 // Expected to be multiple regs for a single incoming arg.
746 // There should be Regs.size() ArgLocs per argument.
747 // This should be the same as getNumRegistersForCallingConv
748 const unsigned NumParts = Args[i].Flags.size();
749
750 // Now split the registers into the assigned types.
751 Args[i].OrigRegs.assign(Args[i].Regs.begin(), Args[i].Regs.end());
752
753 if (NumParts != 1 || NewLLT != OrigTy) {
754 // If we can't directly assign the register, we need one or more
755 // intermediate values.
756 Args[i].Regs.resize(NumParts);
757
758 // For each split register, create and assign a vreg that will store
759 // the incoming component of the larger value. These will later be
760 // merged to form the final vreg.
761 for (unsigned Part = 0; Part < NumParts; ++Part)
762 Args[i].Regs[Part] = MRI.createGenericVirtualRegister(NewLLT);
763 }
764
765 assert((j + (NumParts - 1)) < ArgLocs.size() &&
766 "Too many regs for number of args");
767
768 // Coerce into outgoing value types before register assignment.
769 if (!Handler.isIncomingArgumentHandler() && OrigTy != ValTy) {
770 assert(Args[i].OrigRegs.size() == 1);
771 buildCopyToRegs(MIRBuilder, Args[i].Regs, Args[i].OrigRegs[0], OrigTy,
772 ValTy, extendOpFromFlags(Args[i].Flags[0]));
773 }
774
775 bool BigEndianPartOrdering = TLI->hasBigEndianPartOrdering(OrigVT, DL);
776 for (unsigned Part = 0; Part < NumParts; ++Part) {
777 Register ArgReg = Args[i].Regs[Part];
778 // There should be Regs.size() ArgLocs per argument.
779 unsigned Idx = BigEndianPartOrdering ? NumParts - 1 - Part : Part;
780 CCValAssign &VA = ArgLocs[j + Idx];
781 const ISD::ArgFlagsTy Flags = Args[i].Flags[Part];
782
783 if (VA.isMemLoc() && !Flags.isByVal()) {
784 // Individual pieces may have been spilled to the stack and others
785 // passed in registers.
786
787 // TODO: The memory size may be larger than the value we need to
788 // store. We may need to adjust the offset for big endian targets.
789 LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags);
790
792 Register StackAddr = Handler.getStackAddress(
793 MemTy.getSizeInBytes(), VA.getLocMemOffset(), MPO, Flags);
794
795 Handler.assignValueToAddress(Args[i], Part, StackAddr, MemTy, MPO, VA);
796 continue;
797 }
798
799 if (VA.isMemLoc() && Flags.isByVal()) {
800 assert(Args[i].Regs.size() == 1 &&
801 "didn't expect split byval pointer");
802
803 if (Handler.isIncomingArgumentHandler()) {
804 // We just need to copy the frame index value to the pointer.
806 Register StackAddr = Handler.getStackAddress(
807 Flags.getByValSize(), VA.getLocMemOffset(), MPO, Flags);
808 MIRBuilder.buildCopy(Args[i].Regs[0], StackAddr);
809 } else {
810 // For outgoing byval arguments, insert the implicit copy byval
811 // implies, such that writes in the callee do not modify the caller's
812 // value.
813 uint64_t MemSize = Flags.getByValSize();
814 int64_t Offset = VA.getLocMemOffset();
815
816 MachinePointerInfo DstMPO;
817 Register StackAddr =
818 Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
819
820 MachinePointerInfo SrcMPO(Args[i].OrigValue);
821 if (!Args[i].OrigValue) {
822 // We still need to accurately track the stack address space if we
823 // don't know the underlying value.
824 const LLT PtrTy = MRI.getType(StackAddr);
825 SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
826 }
827
828 Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
829 inferAlignFromPtrInfo(MF, DstMPO));
830
831 Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
832 inferAlignFromPtrInfo(MF, SrcMPO));
833
834 Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
835 DstMPO, DstAlign, SrcMPO, SrcAlign,
836 MemSize, VA);
837 }
838 continue;
839 }
840
841 assert(!VA.needsCustom() && "custom loc should have been handled already");
842
843 if (i == 0 && !ThisReturnRegs.empty() &&
844 Handler.isIncomingArgumentHandler() &&
846 Handler.assignValueToReg(ArgReg, ThisReturnRegs[Part], VA);
847 continue;
848 }
849
850 if (Handler.isIncomingArgumentHandler())
851 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
852 else {
853 DelayedOutgoingRegAssignments.emplace_back([=, &Handler]() {
854 Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA);
855 });
856 }
857 }
858
859 // Now that all pieces have been assigned, re-pack the register typed values
860 // into the original value typed registers.
861 if (Handler.isIncomingArgumentHandler() && OrigVT != LocVT) {
862 // Merge the split registers into the expected larger result vregs of
863 // the original call.
864 buildCopyFromRegs(MIRBuilder, Args[i].OrigRegs, Args[i].Regs, OrigTy,
865 LocTy, Args[i].Flags[0]);
866 }
867
868 j += NumParts - 1;
869 }
870 for (auto &Fn : DelayedOutgoingRegAssignments)
871 Fn();
872
873 return true;
874}
875
877 ArrayRef<Register> VRegs, Register DemoteReg,
878 int FI) const {
879 MachineFunction &MF = MIRBuilder.getMF();
881 const DataLayout &DL = MF.getDataLayout();
882
883 SmallVector<EVT, 4> SplitVTs;
885 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
886
887 assert(VRegs.size() == SplitVTs.size());
888
889 unsigned NumValues = SplitVTs.size();
890 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
891 Type *RetPtrTy =
892 PointerType::get(RetTy->getContext(), DL.getAllocaAddrSpace());
893 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetPtrTy), DL);
894
896
897 for (unsigned I = 0; I < NumValues; ++I) {
899 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
900 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
901 MRI.getType(VRegs[I]),
902 commonAlignment(BaseAlign, Offsets[I]));
903 MIRBuilder.buildLoad(VRegs[I], Addr, *MMO);
904 }
905}
906
908 ArrayRef<Register> VRegs,
909 Register DemoteReg) const {
910 MachineFunction &MF = MIRBuilder.getMF();
912 const DataLayout &DL = MF.getDataLayout();
913
914 SmallVector<EVT, 4> SplitVTs;
916 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs, &Offsets, 0);
917
918 assert(VRegs.size() == SplitVTs.size());
919
920 unsigned NumValues = SplitVTs.size();
921 Align BaseAlign = DL.getPrefTypeAlign(RetTy);
922 unsigned AS = DL.getAllocaAddrSpace();
923 LLT OffsetLLTy = getLLTForType(*DL.getIndexType(RetTy->getPointerTo(AS)), DL);
924
925 MachinePointerInfo PtrInfo(AS);
926
927 for (unsigned I = 0; I < NumValues; ++I) {
929 MIRBuilder.materializePtrAdd(Addr, DemoteReg, OffsetLLTy, Offsets[I]);
930 auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
931 MRI.getType(VRegs[I]),
932 commonAlignment(BaseAlign, Offsets[I]));
933 MIRBuilder.buildStore(VRegs[I], Addr, *MMO);
934 }
935}
936
938 const Function &F, SmallVectorImpl<ArgInfo> &SplitArgs, Register &DemoteReg,
939 MachineRegisterInfo &MRI, const DataLayout &DL) const {
940 unsigned AS = DL.getAllocaAddrSpace();
941 DemoteReg = MRI.createGenericVirtualRegister(
942 LLT::pointer(AS, DL.getPointerSizeInBits(AS)));
943
944 Type *PtrTy = PointerType::get(F.getReturnType(), AS);
945
946 SmallVector<EVT, 1> ValueVTs;
947 ComputeValueVTs(*TLI, DL, PtrTy, ValueVTs);
948
949 // NOTE: Assume that a pointer won't get split into more than one VT.
950 assert(ValueVTs.size() == 1);
951
952 ArgInfo DemoteArg(DemoteReg, ValueVTs[0].getTypeForEVT(PtrTy->getContext()),
955 DemoteArg.Flags[0].setSRet();
956 SplitArgs.insert(SplitArgs.begin(), DemoteArg);
957}
958
960 const CallBase &CB,
961 CallLoweringInfo &Info) const {
962 const DataLayout &DL = MIRBuilder.getDataLayout();
963 Type *RetTy = CB.getType();
964 unsigned AS = DL.getAllocaAddrSpace();
965 LLT FramePtrTy = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
966
967 int FI = MIRBuilder.getMF().getFrameInfo().CreateStackObject(
968 DL.getTypeAllocSize(RetTy), DL.getPrefTypeAlign(RetTy), false);
969
970 Register DemoteReg = MIRBuilder.buildFrameIndex(FramePtrTy, FI).getReg(0);
971 ArgInfo DemoteArg(DemoteReg, PointerType::get(RetTy, AS),
974 DemoteArg.Flags[0].setSRet();
975
976 Info.OrigArgs.insert(Info.OrigArgs.begin(), DemoteArg);
977 Info.DemoteStackIndex = FI;
978 Info.DemoteRegister = DemoteReg;
979}
980
983 CCAssignFn *Fn) const {
984 for (unsigned I = 0, E = Outs.size(); I < E; ++I) {
985 MVT VT = MVT::getVT(Outs[I].Ty);
986 if (Fn(I, VT, VT, CCValAssign::Full, Outs[I].Flags[0], CCInfo))
987 return false;
988 }
989 return true;
990}
991
993 AttributeList Attrs,
995 const DataLayout &DL) const {
996 LLVMContext &Context = RetTy->getContext();
998
999 SmallVector<EVT, 4> SplitVTs;
1000 ComputeValueVTs(*TLI, DL, RetTy, SplitVTs);
1002
1003 for (EVT VT : SplitVTs) {
1004 unsigned NumParts =
1005 TLI->getNumRegistersForCallingConv(Context, CallConv, VT);
1006 MVT RegVT = TLI->getRegisterTypeForCallingConv(Context, CallConv, VT);
1007 Type *PartTy = EVT(RegVT).getTypeForEVT(Context);
1008
1009 for (unsigned I = 0; I < NumParts; ++I) {
1010 Outs.emplace_back(PartTy, Flags);
1011 }
1012 }
1013}
1014
1016 const auto &F = MF.getFunction();
1017 Type *ReturnType = F.getReturnType();
1018 CallingConv::ID CallConv = F.getCallingConv();
1019
1021 getReturnInfo(CallConv, ReturnType, F.getAttributes(), SplitArgs,
1022 MF.getDataLayout());
1023 return canLowerReturn(MF, CallConv, SplitArgs, F.isVarArg());
1024}
1025
1027 const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask,
1028 const SmallVectorImpl<CCValAssign> &OutLocs,
1029 const SmallVectorImpl<ArgInfo> &OutArgs) const {
1030 for (unsigned i = 0; i < OutLocs.size(); ++i) {
1031 const auto &ArgLoc = OutLocs[i];
1032 // If it's not a register, it's fine.
1033 if (!ArgLoc.isRegLoc())
1034 continue;
1035
1036 MCRegister PhysReg = ArgLoc.getLocReg();
1037
1038 // Only look at callee-saved registers.
1039 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, PhysReg))
1040 continue;
1041
1042 LLVM_DEBUG(
1043 dbgs()
1044 << "... Call has an argument passed in a callee-saved register.\n");
1045
1046 // Check if it was copied from.
1047 const ArgInfo &OutInfo = OutArgs[i];
1048
1049 if (OutInfo.Regs.size() > 1) {
1050 LLVM_DEBUG(
1051 dbgs() << "... Cannot handle arguments in multiple registers.\n");
1052 return false;
1053 }
1054
1055 // Check if we copy the register, walking through copies from virtual
1056 // registers. Note that getDefIgnoringCopies does not ignore copies from
1057 // physical registers.
1058 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
1059 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
1060 LLVM_DEBUG(
1061 dbgs()
1062 << "... Parameter was not copied into a VReg, cannot tail call.\n");
1063 return false;
1064 }
1065
1066 // Got a copy. Verify that it's the same as the register we want.
1067 Register CopyRHS = RegDef->getOperand(1).getReg();
1068 if (CopyRHS != PhysReg) {
1069 LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
1070 "VReg, cannot tail call.\n");
1071 return false;
1072 }
1073 }
1074
1075 return true;
1076}
1077
1079 MachineFunction &MF,
1081 ValueAssigner &CalleeAssigner,
1082 ValueAssigner &CallerAssigner) const {
1083 const Function &F = MF.getFunction();
1084 CallingConv::ID CalleeCC = Info.CallConv;
1085 CallingConv::ID CallerCC = F.getCallingConv();
1086
1087 if (CallerCC == CalleeCC)
1088 return true;
1089
1091 CCState CCInfo1(CalleeCC, Info.IsVarArg, MF, ArgLocs1, F.getContext());
1092 if (!determineAssignments(CalleeAssigner, InArgs, CCInfo1))
1093 return false;
1094
1096 CCState CCInfo2(CallerCC, F.isVarArg(), MF, ArgLocs2, F.getContext());
1097 if (!determineAssignments(CallerAssigner, InArgs, CCInfo2))
1098 return false;
1099
1100 // We need the argument locations to match up exactly. If there's more in
1101 // one than the other, then we are done.
1102 if (ArgLocs1.size() != ArgLocs2.size())
1103 return false;
1104
1105 // Make sure that each location is passed in exactly the same way.
1106 for (unsigned i = 0, e = ArgLocs1.size(); i < e; ++i) {
1107 const CCValAssign &Loc1 = ArgLocs1[i];
1108 const CCValAssign &Loc2 = ArgLocs2[i];
1109
1110 // We need both of them to be the same. So if one is a register and one
1111 // isn't, we're done.
1112 if (Loc1.isRegLoc() != Loc2.isRegLoc())
1113 return false;
1114
1115 if (Loc1.isRegLoc()) {
1116 // If they don't have the same register location, we're done.
1117 if (Loc1.getLocReg() != Loc2.getLocReg())
1118 return false;
1119
1120 // They matched, so we can move to the next ArgLoc.
1121 continue;
1122 }
1123
1124 // Loc1 wasn't a RegLoc, so they both must be MemLocs. Check if they match.
1125 if (Loc1.getLocMemOffset() != Loc2.getLocMemOffset())
1126 return false;
1127 }
1128
1129 return true;
1130}
1131
1133 const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const {
1134 const MVT ValVT = VA.getValVT();
1135 if (ValVT != MVT::iPTR) {
1136 LLT ValTy(ValVT);
1137
1138 // We lost the pointeriness going through CCValAssign, so try to restore it
1139 // based on the flags.
1140 if (Flags.isPointer()) {
1141 LLT PtrTy = LLT::pointer(Flags.getPointerAddrSpace(),
1142 ValTy.getScalarSizeInBits());
1143 if (ValVT.isVector())
1144 return LLT::vector(ValTy.getElementCount(), PtrTy);
1145 return PtrTy;
1146 }
1147
1148 return ValTy;
1149 }
1150
1151 unsigned AddrSpace = Flags.getPointerAddrSpace();
1152 return LLT::pointer(AddrSpace, DL.getPointerSize(AddrSpace));
1153}
1154
1156 const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
1157 const MachinePointerInfo &DstPtrInfo, Align DstAlign,
1158 const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize,
1159 CCValAssign &VA) const {
1160 MachineFunction &MF = MIRBuilder.getMF();
1162 SrcPtrInfo,
1164 SrcAlign);
1165
1167 DstPtrInfo,
1169 MemSize, DstAlign);
1170
1171 const LLT PtrTy = MRI.getType(DstPtr);
1172 const LLT SizeTy = LLT::scalar(PtrTy.getSizeInBits());
1173
1174 auto SizeConst = MIRBuilder.buildConstant(SizeTy, MemSize);
1175 MIRBuilder.buildMemCpy(DstPtr, SrcPtr, SizeConst, *DstMMO, *SrcMMO);
1176}
1177
1179 const CCValAssign &VA,
1180 unsigned MaxSizeBits) {
1181 LLT LocTy{VA.getLocVT()};
1182 LLT ValTy{VA.getValVT()};
1183
1184 if (LocTy.getSizeInBits() == ValTy.getSizeInBits())
1185 return ValReg;
1186
1187 if (LocTy.isScalar() && MaxSizeBits && MaxSizeBits < LocTy.getSizeInBits()) {
1188 if (MaxSizeBits <= ValTy.getSizeInBits())
1189 return ValReg;
1190 LocTy = LLT::scalar(MaxSizeBits);
1191 }
1192
1193 const LLT ValRegTy = MRI.getType(ValReg);
1194 if (ValRegTy.isPointer()) {
1195 // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so
1196 // we have to cast to do the extension.
1197 LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits());
1198 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0);
1199 }
1200
1201 switch (VA.getLocInfo()) {
1202 default: break;
1203 case CCValAssign::Full:
1204 case CCValAssign::BCvt:
1205 // FIXME: bitconverting between vector types may or may not be a
1206 // nop in big-endian situations.
1207 return ValReg;
1208 case CCValAssign::AExt: {
1209 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
1210 return MIB.getReg(0);
1211 }
1212 case CCValAssign::SExt: {
1213 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1214 MIRBuilder.buildSExt(NewReg, ValReg);
1215 return NewReg;
1216 }
1217 case CCValAssign::ZExt: {
1218 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
1219 MIRBuilder.buildZExt(NewReg, ValReg);
1220 return NewReg;
1221 }
1222 }
1223 llvm_unreachable("unable to extend register");
1224}
1225
1226void CallLowering::ValueAssigner::anchor() {}
1227
1229 const CCValAssign &VA, Register SrcReg, LLT NarrowTy) {
1230 switch (VA.getLocInfo()) {
1232 return MIRBuilder
1233 .buildAssertZExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1234 NarrowTy.getScalarSizeInBits())
1235 .getReg(0);
1236 }
1238 return MIRBuilder
1239 .buildAssertSExt(MRI.cloneVirtualRegister(SrcReg), SrcReg,
1240 NarrowTy.getScalarSizeInBits())
1241 .getReg(0);
1242 break;
1243 }
1244 default:
1245 return SrcReg;
1246 }
1247}
1248
1249/// Check if we can use a basic COPY instruction between the two types.
1250///
1251/// We're currently building on top of the infrastructure using MVT, which loses
1252/// pointer information in the CCValAssign. We accept copies from physical
1253/// registers that have been reported as integers if it's to an equivalent sized
1254/// pointer LLT.
1255static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
1256 if (SrcTy == DstTy)
1257 return true;
1258
1259 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1260 return false;
1261
1262 SrcTy = SrcTy.getScalarType();
1263 DstTy = DstTy.getScalarType();
1264
1265 return (SrcTy.isPointer() && DstTy.isScalar()) ||
1266 (DstTy.isPointer() && SrcTy.isScalar());
1267}
1268
1270 Register ValVReg, Register PhysReg, const CCValAssign &VA) {
1271 const MVT LocVT = VA.getLocVT();
1272 const LLT LocTy(LocVT);
1273 const LLT RegTy = MRI.getType(ValVReg);
1274
1275 if (isCopyCompatibleType(RegTy, LocTy)) {
1276 MIRBuilder.buildCopy(ValVReg, PhysReg);
1277 return;
1278 }
1279
1280 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);
1281 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy);
1282 MIRBuilder.buildTrunc(ValVReg, Hint);
1283}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static void addFlagsUsingAttrFn(ISD::ArgFlagsTy &Flags, const std::function< bool(Attribute::AttrKind)> &AttrFn)
Helper function which updates Flags when AttrFn returns true.
static void buildCopyToRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy, unsigned ExtendOp=TargetOpcode::G_ANYEXT)
Create a sequence of instructions to expand the value in SrcReg (of type SrcTy) to the types in DstRe...
static MachineInstrBuilder mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef< Register > DstRegs, ArrayRef< Register > SrcRegs)
Pack values SrcRegs to cover the vector type result DstRegs.
static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef< Register > OrigRegs, ArrayRef< Register > Regs, LLT LLTy, LLT PartLLT, const ISD::ArgFlagsTy Flags)
Create a sequence of instructions to combine pieces split into register typed values to the original ...
static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy)
Check if we can use a basic COPY instruction between the two types.
static unsigned extendOpFromFlags(llvm::ISD::ArgFlagsTy Flags)
This file describes how to lower LLVM calls to machine code calls.
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Addr
uint64_t Size
static unsigned NumFixedArgs
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares the MachineIRBuilder class.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
R600 Clause Merge
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ArrayRef< T > take_front(size_t N=1) const
Return a copy of *this with only the first N elements.
Definition: ArrayRef.h:228
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
Definition: ArrayRef.h:204
const T & front() const
front - Get the first element.
Definition: ArrayRef.h:168
iterator end() const
Definition: ArrayRef.h:154
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
iterator begin() const
Definition: ArrayRef.h:153
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
AttrKind
This enumeration lists the attributes that can be associated with parameters, function results,...
Definition: Attributes.h:84
CCState - This class holds information needed while lowering arguments and return values.
CallingConv::ID getCallingConv() const
LLVMContext & getContext() const
CCValAssign - Represent assignment of one arg/retval to a location.
bool isRegLoc() const
Register getLocReg() const
LocInfo getLocInfo() const
bool needsCustom() const
bool isMemLoc() const
int64_t getLocMemOffset() const
unsigned getValNo() const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1259
MaybeAlign getRetAlign() const
Extract the alignment of the return value.
Definition: InstrTypes.h:1822
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
Definition: InstrTypes.h:2123
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1539
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
Value * getCalledOperand() const
Definition: InstrTypes.h:1474
bool isConvergent() const
Determine if the invoke is convergent.
Definition: InstrTypes.h:2007
FunctionType * getFunctionType() const
Definition: InstrTypes.h:1339
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Definition: InstrTypes.h:1417
AttributeList getAttributes() const
Return the parameter attributes for this call.
Definition: InstrTypes.h:1558
bool isTailCall() const
Tests if this call site is marked as a tail call.
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetOutgoingArgument(MachineIRBuilder &MIRBuilder, const CallBase &CB, CallLoweringInfo &Info) const
For the call-base described by CB, insert the hidden sret ArgInfo to the OrigArgs field of Info.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool checkReturnTypeForCallConv(MachineFunction &MF) const
Toplevel function to check the return type based on the target calling convention.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
virtual bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const
This hook must be implemented to check whether the return values described by Outs can fit into the r...
Definition: CallLowering.h:495
virtual bool isTypeIsValidForThisReturn(EVT Ty) const
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
Definition: CallLowering.h:595
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
ISD::ArgFlagsTy getAttributesForArgIdx(const CallBase &Call, unsigned ArgIdx) const
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
void addArgFlagsFromAttributes(ISD::ArgFlagsTy &Flags, const AttributeList &Attrs, unsigned OpIdx) const
Adds flags to Flags based off of the attributes in Attrs.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
void getReturnInfo(CallingConv::ID CallConv, Type *RetTy, AttributeList Attrs, SmallVectorImpl< BaseArgInfo > &Outs, const DataLayout &DL) const
Get the type and the ArgFlags for the split components of RetTy as returned by ComputeValueVTs.
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
const TargetLowering * getTLI() const
Getter for generic TargetLowering class.
Definition: CallLowering.h:343
virtual bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: CallLowering.h:555
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
ISD::ArgFlagsTy getAttributesForReturn(const CallBase &Call) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Definition: DerivedTypes.h:142
bool isVarArg() const
Definition: DerivedTypes.h:123
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.cpp:695
MDNode * getMetadata(unsigned KindID) const
Get the metadata of given kind attached to this Instruction.
Definition: Instruction.h:357
constexpr unsigned getScalarSizeInBits() const
Definition: LowLevelType.h:259
constexpr bool isScalar() const
Definition: LowLevelType.h:139
constexpr LLT changeElementType(LLT NewEltTy) const
If this type is a vector, return a vector with the same number of elements but the new element type.
Definition: LowLevelType.h:206
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelType.h:56
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:151
constexpr bool isVector() const
Definition: LowLevelType.h:147
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:49
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:185
constexpr bool isPointer() const
Definition: LowLevelType.h:141
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
Definition: LowLevelType.h:282
constexpr ElementCount getElementCount() const
Definition: LowLevelType.h:176
constexpr unsigned getAddressSpace() const
Definition: LowLevelType.h:272
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelType.h:92
constexpr LLT changeElementCount(ElementCount EC) const
Return a vector or scalar with the same element type and the new element count.
Definition: LowLevelType.h:222
constexpr LLT getScalarType() const
Definition: LowLevelType.h:200
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:195
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:583
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Helper class to build MachineInstr.
std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)
Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)
MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_SEXT Op.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildMemCpy(const SrcOp &DstPtr, const SrcOp &SrcPtr, const SrcOp &Size, MachineMemOperand &DstMMO, MachineMemOperand &SrcMMO)
MachineInstrBuilder buildAssertAlign(const DstOp &Res, const SrcOp &Op, Align AlignVal)
Build and insert Res = G_ASSERT_ALIGN Op, AlignVal.
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
const DataLayout & getDataLayout() const
MachineInstrBuilder buildAssertSExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_SEXT Op, Size.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src)
Build and insert a G_PTRTOINT instruction.
Register getReg(unsigned Idx) const
Get the register for the operand index.
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:543
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
A description of a memory reference used in the backend.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Class to represent pointers.
Definition: DerivedTypes.h:646
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void reserve(size_type N)
Definition: SmallVector.h:676
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:818
void truncate(size_type N)
Like resize, but requires that N is less than size().
Definition: SmallVector.h:657
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
const Value * stripPointerCasts() const
Strip off pointer casts, all-zero GEPs and address space casts.
Definition: Value.cpp:693
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:203
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
Definition: TypeSize.h:210
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:466
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:1143
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
Definition: Analysis.cpp:535
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:1164
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:866
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
const Value * OrigValue
Optionally track the original IR value for the argument.
Definition: CallLowering.h:73
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
unsigned OrigArgIndex
Index original Function's argument.
Definition: CallLowering.h:76
static const unsigned NoArgIndex
Sentinel value for implicit machine-level input arguments.
Definition: CallLowering.h:79
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
Provides a default implementation for argument handling.
Register buildExtensionHint(const CCValAssign &VA, Register SrcReg, LLT NarrowTy)
Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on VA, returning the new register ...
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:164
virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, const ArgInfo &Info, ISD::ArgFlagsTy Flags, CCState &State)
Wrap call to (typically tablegenerated CCAssignFn).
Definition: CallLowering.h:188
void copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr, const MachinePointerInfo &DstPtrInfo, Align DstAlign, const MachinePointerInfo &SrcPtrInfo, Align SrcAlign, uint64_t MemSize, CCValAssign &VA) const
Do a memory copy of MemSize bytes from SrcPtr to DstPtr.
virtual Register getStackAddress(uint64_t MemSize, int64_t Offset, MachinePointerInfo &MPO, ISD::ArgFlagsTy Flags)=0
Materialize a VReg containing the address of the specified stack-based object.
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
bool isIncomingArgumentHandler() const
Returns true if the handler is dealing with incoming arguments, i.e.
Definition: CallLowering.h:245
virtual void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA)=0
The specified value has been assigned to a stack location.
Register extendRegister(Register ValReg, const CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
virtual unsigned assignCustomValue(ArgInfo &Arg, ArrayRef< CCValAssign > VAs, std::function< void()> *Thunk=nullptr)
Handle custom values, which may be passed into one or more of VAs.
Definition: CallLowering.h:297
virtual void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA)=0
The specified value has been assigned to a physical register, handle the appropriate COPY (either to ...
Extended Value Type.
Definition: ValueTypes.h:34
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:626
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117