LLVM  15.0.0git
AMDGPULegalizerInfo.h
Go to the documentation of this file.
1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
16 
19 #include "SIInstrInfo.h"
20 
21 namespace llvm {
22 
23 class GCNTargetMachine;
24 class GCNSubtarget;
25 class MachineIRBuilder;
26 
27 namespace AMDGPU {
28 struct ImageDimIntrinsicInfo;
29 }
30 /// This class provides the information for the target register banks.
31 class AMDGPULegalizerInfo final : public LegalizerInfo {
32  const GCNSubtarget &ST;
33 
34 public:
36  const GCNTargetMachine &TM);
37 
38  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
39 
40  Register getSegmentAperture(unsigned AddrSpace,
42  MachineIRBuilder &B) const;
43 
45  MachineIRBuilder &B) const;
47  MachineIRBuilder &B) const;
49  MachineIRBuilder &B) const;
51  MachineIRBuilder &B) const;
53  MachineIRBuilder &B) const;
55  MachineIRBuilder &B, bool Signed) const;
57  MachineIRBuilder &B, bool Signed) const;
60  MachineIRBuilder &B) const;
62  MachineIRBuilder &B) const;
64  MachineIRBuilder &B) const;
65 
67  MachineIRBuilder &B) const;
68 
70  const GlobalValue *GV, int64_t Offset,
71  unsigned GAFlags = SIInstrInfo::MO_NONE) const;
72 
74  MachineIRBuilder &B) const;
75  bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
76 
78  MachineIRBuilder &B) const;
79 
81  MachineIRBuilder &B) const;
83  double Log2BaseInverted) const;
87  MachineIRBuilder &B) const;
88 
90  MachineIRBuilder &B) const;
91 
94  bool UsePartialMad64_32,
95  bool SeparateOddAlignedProducts) const;
96  bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const;
98  MachineIRBuilder &B) const;
99 
101  const ArgDescriptor *Arg,
102  const TargetRegisterClass *ArgRC, LLT ArgTy) const;
105 
111  unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
112 
113  Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const;
115  uint64_t Offset,
116  Align Alignment = Align(4)) const;
117 
119  MachineIRBuilder &B) const;
120 
122  Register DstRemReg, Register Num,
123  Register Den) const;
124 
126  Register DstRemReg, Register Num,
127  Register Den) const;
128 
130  MachineIRBuilder &B) const;
131 
133  MachineIRBuilder &B) const;
135  MachineIRBuilder &B) const;
137  MachineIRBuilder &B) const;
139  MachineIRBuilder &B) const;
141  MachineIRBuilder &B) const;
143  MachineIRBuilder &B) const;
145  MachineIRBuilder &B) const;
146 
148  MachineIRBuilder &B) const;
149 
151  MachineInstr &MI, Intrinsic::ID IID) const;
152 
154  MachineIRBuilder &B) const;
155 
157  MachineIRBuilder &B) const;
159  MachineIRBuilder &B, unsigned AddrSpace) const;
160 
161  std::pair<Register, unsigned> splitBufferOffsets(MachineIRBuilder &B,
162  Register OrigOffset) const;
163  void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
164  Register SOffset, unsigned ImmOffset, Register VIndex,
165  MachineRegisterInfo &MRI) const;
166 
168  Register Reg, bool ImageStore = false) const;
170  MachineIRBuilder &B, bool IsFormat) const;
172  MachineIRBuilder &B, bool IsFormat) const;
174  bool IsFormat) const;
175 
177  MachineIRBuilder &B, bool IsTyped,
178  bool IsFormat) const;
180  MachineIRBuilder &B, bool IsFormat,
181  bool IsTyped) const;
183  Intrinsic::ID IID) const;
184 
186 
188 
191  GISelChangeObserver &Observer,
192  const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
193 
194  bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
195 
197  bool IsInc) const;
198 
200  MachineIRBuilder &B) const;
202  MachineIRBuilder &B) const;
204  MachineIRBuilder &B) const;
206  MachineIRBuilder &B) const;
208  MachineIRBuilder &B) const;
209 
210  bool legalizeIntrinsic(LegalizerHelper &Helper,
211  MachineInstr &MI) const override;
212 };
213 } // End llvm namespace.
214 #endif
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::AMDGPULegalizerInfo::legalizeWorkitemIDIntrinsic
bool legalizeWorkitemIDIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned Dim, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:3347
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4637
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AMDGPULegalizerInfo::legalizeImplicitArgPtr
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4183
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
Definition: AMDGPULegalizerInfo.cpp:4200
llvm::AMDGPU::ImageDimIntrinsicInfo
Definition: AMDGPUInstrInfo.h:47
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPULegalizerInfo::loadInputValue
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg, const TargetRegisterClass *ArgRC, LLT ArgTy) const
Definition: AMDGPULegalizerInfo.cpp:3269
llvm::AMDGPULegalizerInfo::legalizeShuffleVector
bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2408
llvm::AMDGPULegalizerInfo::splitBufferOffsets
std::pair< Register, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const
Definition: AMDGPULegalizerInfo.cpp:4220
llvm::AMDGPULegalizerInfo::legalizeFrem
bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2104
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::AMDGPULegalizerInfo::legalizeInsertVectorElt
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2366
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::AMDGPULegalizerInfo::legalizeSBufferLoad
bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:5187
llvm::AMDGPULegalizerInfo::legalizeLoad
bool legalizeLoad(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2625
llvm::SPIRV::Dim
Dim
Definition: SPIRVBaseInfo.h:279
llvm::AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5335
llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2729
llvm::LegalizerHelper
Definition: LegalizerHelper.h:46
LegalizerInfo.h
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:31
llvm::AMDGPULegalizerInfo::legalizeFlog
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
Definition: AMDGPULegalizerInfo.cpp:2754
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM64Impl
void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3528
llvm::AMDGPULegalizerInfo::legalizeFPTOI
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2246
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
llvm::AMDGPULegalizerInfo::legalizeFDIV
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3423
llvm::SIInstrInfo::MO_NONE
@ MO_NONE
Definition: SIInstrInfo.h:157
llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2138
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
llvm::AMDGPULegalizerInfo::legalizeFExp
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2769
llvm::AMDGPULegalizerInfo::legalizeFceil
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2075
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AMDGPULegalizerInfo::legalizeFDIV16
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3834
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic
bool legalizeBVHIntrinsic(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5356
llvm::AMDGPULegalizerInfo::legalizePreloadedArgIntrin
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
Definition: AMDGPULegalizerInfo.cpp:3330
llvm::AMDGPULegalizerInfo::fixStoreSourceType
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4353
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::AMDGPULegalizerInfo::legalizeTrapIntrinsic
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5238
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPULegalizerInfo::legalizeGlobalValue
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2516
llvm::AMDGPULegalizerInfo::legalizeFPTruncRound
bool legalizeFPTruncRound(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5498
llvm::AMDGPULegalizerInfo::legalizeAtomicIncDec
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
Definition: AMDGPULegalizerInfo.cpp:4581
llvm::AMDGPULegalizerInfo::legalizeFDIVFastIntrin
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4049
llvm::AMDGPULegalizerInfo::getImplicitArgPtr
bool getImplicitArgPtr(Register DstReg, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4164
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:219
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::AMDGPULegalizerInfo::handleD16VData
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg, bool ImageStore=false) const
Handle register layout difference for f16 images for some subtargets.
Definition: AMDGPULegalizerInfo.cpp:4290
llvm::AMDGPULegalizerInfo::legalizeTrapHsa
bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5327
llvm::AMDGPULegalizerInfo::legalizeBufferStore
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
Definition: AMDGPULegalizerInfo.cpp:4376
SIInstrInfo.h
llvm::AMDGPULegalizerInfo::legalizeDSAtomicFPIntrinsic
bool legalizeDSAtomicFPIntrinsic(LegalizerHelper &Helper, MachineInstr &MI, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:4146
llvm::AMDGPULegalizerInfo::getKernargParameterPtr
Register getKernargParameterPtr(MachineIRBuilder &B, int64_t Offset) const
Definition: AMDGPULegalizerInfo.cpp:3387
llvm::AMDGPULegalizerInfo::legalizeFPow
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2783
llvm::GCNTargetMachine
Definition: AMDGPUTargetMachine.h:75
llvm::AMDGPULegalizerInfo::legalizeFrint
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2049
llvm::AMDGPULegalizerInfo::legalizeMul
bool legalizeMul(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:3148
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::AMDGPULegalizerInfo::buildMultiply
void buildMultiply(LegalizerHelper &Helper, MutableArrayRef< Register > Accum, ArrayRef< Register > Src0, ArrayRef< Register > Src1, bool UsePartialMad64_32, bool SeparateOddAlignedProducts) const
Definition: AMDGPULegalizerInfo.cpp:2914
llvm::AMDGPULegalizerInfo::legalizeFDIV64
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3968
llvm::AMDGPULegalizerInfo::legalizeExtractVectorElt
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2332
llvm::GISelChangeObserver
Abstract class that contains various methods for clients to notify about changes.
Definition: GISelChangeObserver.h:29
llvm::AMDGPULegalizerInfo::legalizeTrapEndpgm
bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5261
llvm::AMDGPULegalizerInfo::buildPCRelGlobalAddress
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
Definition: AMDGPULegalizerInfo.cpp:2456
llvm::AMDGPULegalizerInfo::legalizeIntrinsic
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
Definition: AMDGPULegalizerInfo.cpp:5519
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::AMDGPULegalizerInfo::legalizeITOFP
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
Definition: AMDGPULegalizerInfo.cpp:2183
llvm::AMDGPULegalizerInfo::legalizeKernargMemParameter
bool legalizeKernargMemParameter(MachineInstr &MI, MachineIRBuilder &B, uint64_t Offset, Align Alignment=Align(4)) const
Legalize a value that's loaded from kernel arguments.
Definition: AMDGPULegalizerInfo.cpp:3405
llvm::AMDGPULegalizerInfo::legalizeSignedDIV_REM
bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3680
llvm::AMDGPULegalizerInfo::legalizeBufferAtomic
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
Definition: AMDGPULegalizerInfo.cpp:4650
llvm::AMDGPULegalizerInfo::getSegmentAperture
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1819
llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr
bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:5268
llvm::AMDGPULegalizerInfo::legalizeRawBufferLoad
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeRsqClampIntrinsic
bool legalizeRsqClampIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:4090
llvm::AMDGPULegalizerInfo::legalizeFFloor
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2830
llvm::AMDGPULegalizerInfo::legalizeCTLZ_CTTZ
bool legalizeCTLZ_CTTZ(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3200
llvm::AMDGPULegalizerInfo::legalizeFMad
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2707
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3748
llvm::AMDGPULegalizerInfo::legalizeBufferLoad
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat, bool IsTyped) const
Definition: AMDGPULegalizerInfo.cpp:4463
llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:1929
llvm::AMDGPULegalizerInfo::AMDGPULegalizerInfo
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
Definition: AMDGPULegalizerInfo.cpp:426
llvm::AMDGPULegalizerInfo::legalizeBuildVector
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2888
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM
bool legalizeUnsignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3640
llvm::AMDGPULegalizerInfo::legalizeRawBufferStore
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
llvm::AMDGPULegalizerInfo::legalizeFastUnsafeFDIV64
bool legalizeFastUnsafeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3797
llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic
bool legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
Rewrite image intrinsics to use register layouts expected by the subtarget.
Definition: AMDGPULegalizerInfo.cpp:4832
llvm::AMDGPULegalizerInfo::legalizeMinNumMaxNum
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const
Definition: AMDGPULegalizerInfo.cpp:2313
llvm::AMDGPULegalizerInfo::legalizeFDIV32
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:3899
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1180
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::AMDGPULegalizerInfo::legalizeUnsignedDIV_REM32Impl
void legalizeUnsignedDIV_REM32Impl(MachineIRBuilder &B, Register DstDivReg, Register DstRemReg, Register Num, Register Den) const
Definition: AMDGPULegalizerInfo.cpp:3442
llvm::AMDGPULegalizerInfo::legalizeCustom
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
Definition: AMDGPULegalizerInfo.cpp:1735
AMDGPUArgumentUsageInfo.h
llvm::AMDGPULegalizerInfo::legalizeSinCos
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Definition: AMDGPULegalizerInfo.cpp:2428
llvm::AMDGPULegalizerInfo::updateBufferMMO
void updateBufferMMO(MachineMemOperand *MMO, Register VOffset, Register SOffset, unsigned ImmOffset, Register VIndex, MachineRegisterInfo &MRI) const
Update MMO based on the offset inputs to a raw/struct buffer intrinsic.
Definition: AMDGPULegalizerInfo.cpp:4265
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
llvm::LLT
Definition: LowLevelTypeImpl.h:39