LLVM  12.0.0git
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1 //===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file declares the targeting of the Machinelegalizer class for
10 /// AMDGPU.
11 /// \todo This should be generated by TableGen.
12 //===----------------------------------------------------------------------===//
19 #include "SIInstrInfo.h"
21 namespace llvm {
23 class GCNTargetMachine;
24 class LLVMContext;
25 class GCNSubtarget;
27 /// This class provides the information for the target register banks.
29  const GCNSubtarget &ST;
31 public:
33  const GCNTargetMachine &TM);
35  bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
37  Register getSegmentAperture(unsigned AddrSpace,
39  MachineIRBuilder &B) const;
42  MachineIRBuilder &B) const;
44  MachineIRBuilder &B) const;
46  MachineIRBuilder &B) const;
48  MachineIRBuilder &B) const;
50  MachineIRBuilder &B, bool Signed) const;
52  MachineIRBuilder &B, bool Signed) const;
53  bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
55  MachineIRBuilder &B) const;
57  MachineIRBuilder &B) const;
59  MachineIRBuilder &B) const;
62  MachineIRBuilder &B) const;
65  const GlobalValue *GV, int64_t Offset,
66  unsigned GAFlags = SIInstrInfo::MO_NONE) const;
69  MachineIRBuilder &B) const;
72  GISelChangeObserver &Observer) const;
75  MachineIRBuilder &B) const;
78  MachineIRBuilder &B) const;
80  double Log2BaseInverted) const;
81  bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
82  bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
84  MachineIRBuilder &B) const;
87  MachineIRBuilder &B) const;
90  Register PhyReg, LLT Ty,
91  bool InsertLiveInCopy = true) const;
93  Register LiveIn, Register PhyReg) const;
94  const ArgDescriptor *
98  const ArgDescriptor *Arg) const;
104  MachineIRBuilder &B) const;
107  Register DstReg, Register Num, Register Den,
108  bool IsRem) const;
110  MachineIRBuilder &B) const;
112  MachineIRBuilder &B) const;
115  Register DstReg, Register Numer, Register Denom,
116  bool IsDiv) const;
119  MachineIRBuilder &B) const;
121  MachineIRBuilder &B) const;
124  MachineIRBuilder &B) const;
126  MachineIRBuilder &B) const;
128  MachineIRBuilder &B) const;
130  MachineIRBuilder &B) const;
132  MachineIRBuilder &B) const;
134  MachineIRBuilder &B) const;
137  MachineIRBuilder &B) const;
139  MachineIRBuilder &B, unsigned AddrSpace) const;
141  std::tuple<Register, unsigned, unsigned>
142  splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
145  Register Reg) const;
147  MachineIRBuilder &B, bool IsFormat) const;
149  MachineIRBuilder &B, bool IsFormat) const;
151  bool IsFormat) const;
154  MachineIRBuilder &B, bool IsTyped,
155  bool IsFormat) const;
157  MachineIRBuilder &B, bool IsTyped,
158  bool IsFormat) const;
160  Intrinsic::ID IID) const;
164  GISelChangeObserver &Observer,
165  const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
167  bool legalizeSBufferLoad(
169  GISelChangeObserver &Observer) const;
172  bool IsInc) const;
175  MachineIRBuilder &B) const;
177  MachineIRBuilder &B) const;
179  bool legalizeIntrinsic(LegalizerHelper &Helper,
180  MachineInstr &MI) const override;
181 };
182 } // End llvm namespace.
183 #endif
bool loadInputValue(Register DstReg, MachineIRBuilder &B, const ArgDescriptor *Arg) const
bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override
Called for instructions with the Custom LegalizationAction.
bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Register getSegmentAperture(unsigned AddrSpace, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeSBufferLoad(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer) const
unsigned Reg
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, unsigned AddrSpace) const
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, GISelChangeObserver &Observer) const
Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register Reg) const
Handle register layout difference for f16 images for some subtargets.
Register fixStoreSourceType(MachineIRBuilder &B, Register VData, bool IsFormat) const
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B, bool IsInc) const
bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
void legalizeUDIV_UREM64Impl(MachineIRBuilder &B, Register DstReg, Register Numer, Register Denom, bool IsDiv) const
bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Abstract class that contains various methods for clients to notify about changes. ...
bool buildPCRelGlobalAddress(Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV, int64_t Offset, unsigned GAFlags=SIInstrInfo::MO_NONE) const
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned const MachineRegisterInfo * MRI
bool legalizePreloadedArgIntrin(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Helper class to build MachineInstr.
bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool Signed) const
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
AMDGPULegalizerInfo(const GCNSubtarget &ST, const GCNTargetMachine &TM)
bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsFormat) const
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B, double Log2BaseInverted) const
bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B, Intrinsic::ID IID) const
std::tuple< Register, unsigned, unsigned > splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const
bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
This class provides the information for the target register banks.
bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Interface definition for SIInstrInfo.
bool legalizeImageIntrinsic(MachineInstr &MI, MachineIRBuilder &B, GISelChangeObserver &Observer, const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const
Rewrite image intrinsics to use register layouts expected by the subtarget.
Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register PhyReg, LLT Ty, bool InsertLiveInCopy=true) const
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
const ArgDescriptor * getArgDescriptor(MachineIRBuilder &B, AMDGPUFunctionArgInfo::PreloadedValue ArgType) const
bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI, Register LiveIn, Register PhyReg) const
bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
void legalizeUDIV_UREM32Impl(MachineIRBuilder &B, Register DstReg, Register Num, Register Den, bool IsRem) const
IRTranslator LLVM IR MI
bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const
bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, bool IsTyped, bool IsFormat) const
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19