LLVM 18.0.0git
AArch64CallLowering.cpp
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1//===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12///
13//===----------------------------------------------------------------------===//
14
15#include "AArch64CallLowering.h"
16#include "AArch64ISelLowering.h"
18#include "AArch64RegisterInfo.h"
19#include "AArch64Subtarget.h"
20#include "llvm/ADT/ArrayRef.h"
40#include "llvm/IR/Argument.h"
41#include "llvm/IR/Attributes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include <algorithm>
46#include <cassert>
47#include <cstdint>
48#include <iterator>
49
50#define DEBUG_TYPE "aarch64-call-lowering"
51
52using namespace llvm;
53
55 : CallLowering(&TLI) {}
56
57static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT,
58 MVT &LocVT) {
59 // If ValVT is i1/i8/i16, we should set LocVT to i8/i8/i16. This is a legacy
60 // hack because the DAG calls the assignment function with pre-legalized
61 // register typed values, not the raw type.
62 //
63 // This hack is not applied to return values which are not passed on the
64 // stack.
65 if (OrigVT == MVT::i1 || OrigVT == MVT::i8)
66 ValVT = LocVT = MVT::i8;
67 else if (OrigVT == MVT::i16)
68 ValVT = LocVT = MVT::i16;
69}
70
71// Account for i1/i8/i16 stack passed value hack
73 const MVT ValVT = VA.getValVT();
74 return (ValVT == MVT::i8 || ValVT == MVT::i16) ? LLT(ValVT)
75 : LLT(VA.getLocVT());
76}
77
78namespace {
79
80struct AArch64IncomingValueAssigner
82 AArch64IncomingValueAssigner(CCAssignFn *AssignFn_,
83 CCAssignFn *AssignFnVarArg_)
84 : IncomingValueAssigner(AssignFn_, AssignFnVarArg_) {}
85
86 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
89 CCState &State) override {
90 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
91 return IncomingValueAssigner::assignArg(ValNo, OrigVT, ValVT, LocVT,
92 LocInfo, Info, Flags, State);
93 }
94};
95
96struct AArch64OutgoingValueAssigner
98 const AArch64Subtarget &Subtarget;
99
100 /// Track if this is used for a return instead of function argument
101 /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
102 /// stack passed returns for them and cannot apply the type adjustment.
103 bool IsReturn;
104
105 AArch64OutgoingValueAssigner(CCAssignFn *AssignFn_,
106 CCAssignFn *AssignFnVarArg_,
107 const AArch64Subtarget &Subtarget_,
108 bool IsReturn)
109 : OutgoingValueAssigner(AssignFn_, AssignFnVarArg_),
110 Subtarget(Subtarget_), IsReturn(IsReturn) {}
111
112 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
113 CCValAssign::LocInfo LocInfo,
115 CCState &State) override {
116 bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv());
117 bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg();
118
119 bool Res;
120 if (Info.IsFixed && !UseVarArgsCCForFixed) {
121 if (!IsReturn)
122 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
123 Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
124 } else
125 Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
126
127 StackSize = State.getStackSize();
128 return Res;
129 }
130};
131
132struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
133 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
134 : IncomingValueHandler(MIRBuilder, MRI) {}
135
136 Register getStackAddress(uint64_t Size, int64_t Offset,
138 ISD::ArgFlagsTy Flags) override {
139 auto &MFI = MIRBuilder.getMF().getFrameInfo();
140
141 // Byval is assumed to be writable memory, but other stack passed arguments
142 // are not.
143 const bool IsImmutable = !Flags.isByVal();
144
145 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
146 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
147 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
148 return AddrReg.getReg(0);
149 }
150
151 LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
152 ISD::ArgFlagsTy Flags) const override {
153 // For pointers, we just need to fixup the integer types reported in the
154 // CCValAssign.
155 if (Flags.isPointer())
158 }
159
160 void assignValueToReg(Register ValVReg, Register PhysReg,
161 CCValAssign VA) override {
162 markPhysRegUsed(PhysReg);
163 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
164 }
165
166 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
167 MachinePointerInfo &MPO, CCValAssign &VA) override {
168 MachineFunction &MF = MIRBuilder.getMF();
169
170 LLT ValTy(VA.getValVT());
171 LLT LocTy(VA.getLocVT());
172
173 // Fixup the types for the DAG compatibility hack.
174 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
175 std::swap(ValTy, LocTy);
176 else {
177 // The calling code knows if this is a pointer or not, we're only touching
178 // the LocTy for the i8/i16 hack.
179 assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
180 LocTy = MemTy;
181 }
182
183 auto MMO = MF.getMachineMemOperand(
185 inferAlignFromPtrInfo(MF, MPO));
186
187 switch (VA.getLocInfo()) {
188 case CCValAssign::LocInfo::ZExt:
189 MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
190 return;
191 case CCValAssign::LocInfo::SExt:
192 MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
193 return;
194 default:
195 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
196 return;
197 }
198 }
199
200 /// How the physical register gets marked varies between formal
201 /// parameters (it's a basic-block live-in), and a call instruction
202 /// (it's an implicit-def of the BL).
203 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
204};
205
206struct FormalArgHandler : public IncomingArgHandler {
208 : IncomingArgHandler(MIRBuilder, MRI) {}
209
210 void markPhysRegUsed(MCRegister PhysReg) override {
211 MIRBuilder.getMRI()->addLiveIn(PhysReg);
212 MIRBuilder.getMBB().addLiveIn(PhysReg);
213 }
214};
215
216struct CallReturnHandler : public IncomingArgHandler {
219 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
220
221 void markPhysRegUsed(MCRegister PhysReg) override {
222 MIB.addDef(PhysReg, RegState::Implicit);
223 }
224
226};
227
228/// A special return arg handler for "returned" attribute arg calls.
229struct ReturnedArgCallReturnHandler : public CallReturnHandler {
230 ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
233 : CallReturnHandler(MIRBuilder, MRI, MIB) {}
234
235 void markPhysRegUsed(MCRegister PhysReg) override {}
236};
237
238struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
239 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
240 MachineInstrBuilder MIB, bool IsTailCall = false,
241 int FPDiff = 0)
242 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall),
243 FPDiff(FPDiff),
244 Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
245
246 Register getStackAddress(uint64_t Size, int64_t Offset,
248 ISD::ArgFlagsTy Flags) override {
249 MachineFunction &MF = MIRBuilder.getMF();
250 LLT p0 = LLT::pointer(0, 64);
251 LLT s64 = LLT::scalar(64);
252
253 if (IsTailCall) {
254 assert(!Flags.isByVal() && "byval unhandled with tail calls");
255
256 Offset += FPDiff;
257 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
258 auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
260 return FIReg.getReg(0);
261 }
262
263 if (!SPReg)
264 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
265
266 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
267
268 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
269
271 return AddrReg.getReg(0);
272 }
273
274 /// We need to fixup the reported store size for certain value types because
275 /// we invert the interpretation of ValVT and LocVT in certain cases. This is
276 /// for compatability with the DAG call lowering implementation, which we're
277 /// currently building on top of.
278 LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
279 ISD::ArgFlagsTy Flags) const override {
280 if (Flags.isPointer())
283 }
284
285 void assignValueToReg(Register ValVReg, Register PhysReg,
286 CCValAssign VA) override {
287 MIB.addUse(PhysReg, RegState::Implicit);
288 Register ExtReg = extendRegister(ValVReg, VA);
289 MIRBuilder.buildCopy(PhysReg, ExtReg);
290 }
291
292 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
293 MachinePointerInfo &MPO, CCValAssign &VA) override {
294 MachineFunction &MF = MIRBuilder.getMF();
295 auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
296 inferAlignFromPtrInfo(MF, MPO));
297 MIRBuilder.buildStore(ValVReg, Addr, *MMO);
298 }
299
300 void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
301 Register Addr, LLT MemTy, MachinePointerInfo &MPO,
302 CCValAssign &VA) override {
303 unsigned MaxSize = MemTy.getSizeInBytes() * 8;
304 // For varargs, we always want to extend them to 8 bytes, in which case
305 // we disable setting a max.
306 if (!Arg.IsFixed)
307 MaxSize = 0;
308
309 Register ValVReg = Arg.Regs[RegIndex];
310 if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
311 MVT LocVT = VA.getLocVT();
312 MVT ValVT = VA.getValVT();
313
314 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
315 std::swap(ValVT, LocVT);
316 MemTy = LLT(VA.getValVT());
317 }
318
319 ValVReg = extendRegister(ValVReg, VA, MaxSize);
320 } else {
321 // The store does not cover the full allocated stack slot.
322 MemTy = LLT(VA.getValVT());
323 }
324
325 assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
326 }
327
329
330 bool IsTailCall;
331
332 /// For tail calls, the byte offset of the call's argument area from the
333 /// callee's. Unused elsewhere.
334 int FPDiff;
335
336 // Cache the SP register vreg if we need it more than once in this call site.
337 Register SPReg;
338
339 const AArch64Subtarget &Subtarget;
340};
341} // namespace
342
343static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
344 return (CallConv == CallingConv::Fast && TailCallOpt) ||
345 CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
346}
347
349 const Value *Val,
350 ArrayRef<Register> VRegs,
352 Register SwiftErrorVReg) const {
353 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
354 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
355 "Return value without a vreg");
356
357 bool Success = true;
358 if (!FLI.CanLowerReturn) {
359 insertSRetStores(MIRBuilder, Val->getType(), VRegs, FLI.DemoteRegister);
360 } else if (!VRegs.empty()) {
361 MachineFunction &MF = MIRBuilder.getMF();
362 const Function &F = MF.getFunction();
363 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
364
366 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
367 CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
368 auto &DL = F.getParent()->getDataLayout();
369 LLVMContext &Ctx = Val->getType()->getContext();
370
371 SmallVector<EVT, 4> SplitEVTs;
372 ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
373 assert(VRegs.size() == SplitEVTs.size() &&
374 "For each split Type there should be exactly one VReg.");
375
376 SmallVector<ArgInfo, 8> SplitArgs;
377 CallingConv::ID CC = F.getCallingConv();
378
379 for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
380 Register CurVReg = VRegs[i];
381 ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx), 0};
383
384 // i1 is a special case because SDAG i1 true is naturally zero extended
385 // when widened using ANYEXT. We need to do it explicitly here.
386 auto &Flags = CurArgInfo.Flags[0];
387 if (MRI.getType(CurVReg).getSizeInBits() == 1 && !Flags.isSExt() &&
388 !Flags.isZExt()) {
389 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
390 } else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
391 1) {
392 // Some types will need extending as specified by the CC.
393 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
394 if (EVT(NewVT) != SplitEVTs[i]) {
395 unsigned ExtendOp = TargetOpcode::G_ANYEXT;
396 if (F.getAttributes().hasRetAttr(Attribute::SExt))
397 ExtendOp = TargetOpcode::G_SEXT;
398 else if (F.getAttributes().hasRetAttr(Attribute::ZExt))
399 ExtendOp = TargetOpcode::G_ZEXT;
400
401 LLT NewLLT(NewVT);
402 LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
403 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
404 // Instead of an extend, we might have a vector type which needs
405 // padding with more elements, e.g. <2 x half> -> <4 x half>.
406 if (NewVT.isVector()) {
407 if (OldLLT.isVector()) {
408 if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
409
410 CurVReg =
411 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
412 .getReg(0);
413 } else {
414 // Just do a vector extend.
415 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
416 .getReg(0);
417 }
418 } else if (NewLLT.getNumElements() >= 2 &&
419 NewLLT.getNumElements() <= 8) {
420 // We need to pad a <1 x S> type to <2/4/8 x S>. Since we don't
421 // have <1 x S> vector types in GISel we use a build_vector
422 // instead of a vector merge/concat.
423 CurVReg =
424 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
425 .getReg(0);
426 } else {
427 LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
428 return false;
429 }
430 } else {
431 // If the split EVT was a <1 x T> vector, and NewVT is T, then we
432 // don't have to do anything since we don't distinguish between the
433 // two.
434 if (NewLLT != MRI.getType(CurVReg)) {
435 // A scalar extend.
436 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
437 .getReg(0);
438 }
439 }
440 }
441 }
442 if (CurVReg != CurArgInfo.Regs[0]) {
443 CurArgInfo.Regs[0] = CurVReg;
444 // Reset the arg flags after modifying CurVReg.
446 }
447 splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
448 }
449
450 AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget,
451 /*IsReturn*/ true);
452 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
453 Success = determineAndHandleAssignments(Handler, Assigner, SplitArgs,
454 MIRBuilder, CC, F.isVarArg());
455 }
456
457 if (SwiftErrorVReg) {
458 MIB.addUse(AArch64::X21, RegState::Implicit);
459 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
460 }
461
462 MIRBuilder.insertInstr(MIB);
463 return Success;
464}
465
467 CallingConv::ID CallConv,
469 bool IsVarArg) const {
471 const auto &TLI = *getTLI<AArch64TargetLowering>();
472 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
473 MF.getFunction().getContext());
474
475 return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv));
476}
477
478/// Helper function to compute forwarded registers for musttail calls. Computes
479/// the forwarded registers, sets MBB liveness, and emits COPY instructions that
480/// can be used to save + restore registers later.
482 CCAssignFn *AssignFn) {
483 MachineBasicBlock &MBB = MIRBuilder.getMBB();
484 MachineFunction &MF = MIRBuilder.getMF();
485 MachineFrameInfo &MFI = MF.getFrameInfo();
486
487 if (!MFI.hasMustTailInVarArgFunc())
488 return;
489
491 const Function &F = MF.getFunction();
492 assert(F.isVarArg() && "Expected F to be vararg?");
493
494 // Compute the set of forwarded registers. The rest are scratch.
496 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
497 F.getContext());
498 SmallVector<MVT, 2> RegParmTypes;
499 RegParmTypes.push_back(MVT::i64);
500 RegParmTypes.push_back(MVT::f128);
501
502 // Later on, we can use this vector to restore the registers if necessary.
505 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
506
507 // Conservatively forward X8, since it might be used for an aggregate
508 // return.
509 if (!CCInfo.isAllocated(AArch64::X8)) {
510 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
511 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
512 }
513
514 // Add the forwards to the MachineBasicBlock and MachineFunction.
515 for (const auto &F : Forwards) {
516 MBB.addLiveIn(F.PReg);
517 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
518 }
519}
520
522 auto &F = MF.getFunction();
523 if (F.getReturnType()->isScalableTy() ||
524 llvm::any_of(F.args(), [](const Argument &A) {
525 return A.getType()->isScalableTy();
526 }))
527 return true;
528 const auto &ST = MF.getSubtarget<AArch64Subtarget>();
529 if (!ST.hasNEON() || !ST.hasFPARMv8()) {
530 LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON\n");
531 return true;
532 }
533
534 SMEAttrs Attrs(F);
535 if (Attrs.hasZAState() || Attrs.hasStreamingInterfaceOrBody() ||
536 Attrs.hasStreamingCompatibleInterface())
537 return true;
538
539 return false;
540}
541
542void AArch64CallLowering::saveVarArgRegisters(
544 CCState &CCInfo) const {
547
548 MachineFunction &MF = MIRBuilder.getMF();
550 MachineFrameInfo &MFI = MF.getFrameInfo();
552 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
553 bool IsWin64CC =
554 Subtarget.isCallingConvWin64(CCInfo.getCallingConv());
555 const LLT p0 = LLT::pointer(0, 64);
556 const LLT s64 = LLT::scalar(64);
557
558 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
559 unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
560
561 unsigned GPRSaveSize = 8 * (GPRArgRegs.size() - FirstVariadicGPR);
562 int GPRIdx = 0;
563 if (GPRSaveSize != 0) {
564 if (IsWin64CC) {
565 GPRIdx = MFI.CreateFixedObject(GPRSaveSize,
566 -static_cast<int>(GPRSaveSize), false);
567 if (GPRSaveSize & 15)
568 // The extra size here, if triggered, will always be 8.
569 MFI.CreateFixedObject(16 - (GPRSaveSize & 15),
570 -static_cast<int>(alignTo(GPRSaveSize, 16)),
571 false);
572 } else
573 GPRIdx = MFI.CreateStackObject(GPRSaveSize, Align(8), false);
574
575 auto FIN = MIRBuilder.buildFrameIndex(p0, GPRIdx);
576 auto Offset =
577 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 8);
578
579 for (unsigned i = FirstVariadicGPR; i < GPRArgRegs.size(); ++i) {
580 Register Val = MRI.createGenericVirtualRegister(s64);
581 Handler.assignValueToReg(
582 Val, GPRArgRegs[i],
584 GPRArgRegs[i], MVT::i64, CCValAssign::Full));
585 auto MPO = IsWin64CC ? MachinePointerInfo::getFixedStack(
586 MF, GPRIdx, (i - FirstVariadicGPR) * 8)
587 : MachinePointerInfo::getStack(MF, i * 8);
588 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
589
590 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
591 FIN.getReg(0), Offset);
592 }
593 }
594 FuncInfo->setVarArgsGPRIndex(GPRIdx);
595 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
596
597 if (Subtarget.hasFPARMv8() && !IsWin64CC) {
598 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
599
600 unsigned FPRSaveSize = 16 * (FPRArgRegs.size() - FirstVariadicFPR);
601 int FPRIdx = 0;
602 if (FPRSaveSize != 0) {
603 FPRIdx = MFI.CreateStackObject(FPRSaveSize, Align(16), false);
604
605 auto FIN = MIRBuilder.buildFrameIndex(p0, FPRIdx);
606 auto Offset =
607 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 16);
608
609 for (unsigned i = FirstVariadicFPR; i < FPRArgRegs.size(); ++i) {
610 Register Val = MRI.createGenericVirtualRegister(LLT::scalar(128));
611 Handler.assignValueToReg(
612 Val, FPRArgRegs[i],
614 i + MF.getFunction().getNumOperands() + NumVariadicGPRArgRegs,
615 MVT::f128, FPRArgRegs[i], MVT::f128, CCValAssign::Full));
616
617 auto MPO = MachinePointerInfo::getStack(MF, i * 16);
618 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
619
620 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
621 FIN.getReg(0), Offset);
622 }
623 }
624 FuncInfo->setVarArgsFPRIndex(FPRIdx);
625 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
626 }
627}
628
630 MachineIRBuilder &MIRBuilder, const Function &F,
632 MachineFunction &MF = MIRBuilder.getMF();
633 MachineBasicBlock &MBB = MIRBuilder.getMBB();
635 auto &DL = F.getParent()->getDataLayout();
636 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
637 // TODO: Support Arm64EC
638 bool IsWin64 = Subtarget.isCallingConvWin64(F.getCallingConv()) && !Subtarget.isWindowsArm64EC();
639
640 SmallVector<ArgInfo, 8> SplitArgs;
642
643 // Insert the hidden sret parameter if the return value won't fit in the
644 // return registers.
645 if (!FLI.CanLowerReturn)
647
648 unsigned i = 0;
649 for (auto &Arg : F.args()) {
650 if (DL.getTypeStoreSize(Arg.getType()).isZero())
651 continue;
652
653 ArgInfo OrigArg{VRegs[i], Arg, i};
655
656 // i1 arguments are zero-extended to i8 by the caller. Emit a
657 // hint to reflect this.
658 if (OrigArg.Ty->isIntegerTy(1)) {
659 assert(OrigArg.Regs.size() == 1 &&
660 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 &&
661 "Unexpected registers used for i1 arg");
662
663 auto &Flags = OrigArg.Flags[0];
664 if (!Flags.isZExt() && !Flags.isSExt()) {
665 // Lower i1 argument as i8, and insert AssertZExt + Trunc later.
666 Register OrigReg = OrigArg.Regs[0];
667 Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8));
668 OrigArg.Regs[0] = WideReg;
669 BoolArgs.push_back({OrigReg, WideReg});
670 }
671 }
672
673 if (Arg.hasAttribute(Attribute::SwiftAsync))
674 MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
675
676 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
677 ++i;
678 }
679
680 if (!MBB.empty())
681 MIRBuilder.setInstr(*MBB.begin());
682
683 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
684 CCAssignFn *AssignFn = TLI.CCAssignFnForCall(F.getCallingConv(), IsWin64 && F.isVarArg());
685
686 AArch64IncomingValueAssigner Assigner(AssignFn, AssignFn);
687 FormalArgHandler Handler(MIRBuilder, MRI);
689 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
690 if (!determineAssignments(Assigner, SplitArgs, CCInfo) ||
691 !handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, MIRBuilder))
692 return false;
693
694 if (!BoolArgs.empty()) {
695 for (auto &KV : BoolArgs) {
696 Register OrigReg = KV.first;
697 Register WideReg = KV.second;
698 LLT WideTy = MRI.getType(WideReg);
699 assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 &&
700 "Unexpected bit size of a bool arg");
701 MIRBuilder.buildTrunc(
702 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0));
703 }
704 }
705
707 uint64_t StackSize = Assigner.StackSize;
708 if (F.isVarArg()) {
709 if ((!Subtarget.isTargetDarwin() && !Subtarget.isWindowsArm64EC()) || IsWin64) {
710 // The AAPCS variadic function ABI is identical to the non-variadic
711 // one. As a result there may be more arguments in registers and we should
712 // save them for future reference.
713 // Win64 variadic functions also pass arguments in registers, but all
714 // float arguments are passed in integer registers.
715 saveVarArgRegisters(MIRBuilder, Handler, CCInfo);
716 } else if (Subtarget.isWindowsArm64EC()) {
717 return false;
718 }
719
720 // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
721 StackSize = alignTo(Assigner.StackSize, Subtarget.isTargetILP32() ? 4 : 8);
722
723 auto &MFI = MIRBuilder.getMF().getFrameInfo();
724 FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackSize, true));
725 }
726
727 if (doesCalleeRestoreStack(F.getCallingConv(),
729 // We have a non-standard ABI, so why not make full use of the stack that
730 // we're going to pop? It must be aligned to 16 B in any case.
731 StackSize = alignTo(StackSize, 16);
732
733 // If we're expected to restore the stack (e.g. fastcc), then we'll be
734 // adding a multiple of 16.
735 FuncInfo->setArgumentStackToRestore(StackSize);
736
737 // Our own callers will guarantee that the space is free by giving an
738 // aligned value to CALLSEQ_START.
739 }
740
741 // When we tail call, we need to check if the callee's arguments
742 // will fit on the caller's stack. So, whenever we lower formal arguments,
743 // we should keep track of this information, since we might lower a tail call
744 // in this function later.
745 FuncInfo->setBytesInStackArgArea(StackSize);
746
747 if (Subtarget.hasCustomCallingConv())
748 Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
749
750 handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
751
752 // Move back to the end of the basic block.
753 MIRBuilder.setMBB(MBB);
754
755 return true;
756}
757
758/// Return true if the calling convention is one that we can guarantee TCO for.
759static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
760 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
762}
763
764/// Return true if we might ever do TCO for calls with this calling convention.
766 switch (CC) {
767 case CallingConv::C:
774 return true;
775 default:
776 return false;
777 }
778}
779
780/// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
781/// CC.
782static std::pair<CCAssignFn *, CCAssignFn *>
784 return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
785}
786
787bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
788 CallLoweringInfo &Info, MachineFunction &MF,
789 SmallVectorImpl<ArgInfo> &InArgs) const {
790 const Function &CallerF = MF.getFunction();
791 CallingConv::ID CalleeCC = Info.CallConv;
792 CallingConv::ID CallerCC = CallerF.getCallingConv();
793
794 // If the calling conventions match, then everything must be the same.
795 if (CalleeCC == CallerCC)
796 return true;
797
798 // Check if the caller and callee will handle arguments in the same way.
799 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
800 CCAssignFn *CalleeAssignFnFixed;
801 CCAssignFn *CalleeAssignFnVarArg;
802 std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
803 getAssignFnsForCC(CalleeCC, TLI);
804
805 CCAssignFn *CallerAssignFnFixed;
806 CCAssignFn *CallerAssignFnVarArg;
807 std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
808 getAssignFnsForCC(CallerCC, TLI);
809
810 AArch64IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
811 CalleeAssignFnVarArg);
812 AArch64IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
813 CallerAssignFnVarArg);
814
815 if (!resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner))
816 return false;
817
818 // Make sure that the caller and callee preserve all of the same registers.
819 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
820 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
821 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
823 TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
824 TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
825 }
826
827 return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
828}
829
830bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
831 CallLoweringInfo &Info, MachineFunction &MF,
832 SmallVectorImpl<ArgInfo> &OutArgs) const {
833 // If there are no outgoing arguments, then we are done.
834 if (OutArgs.empty())
835 return true;
836
837 const Function &CallerF = MF.getFunction();
838 LLVMContext &Ctx = CallerF.getContext();
839 CallingConv::ID CalleeCC = Info.CallConv;
840 CallingConv::ID CallerCC = CallerF.getCallingConv();
841 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
842 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
843
844 CCAssignFn *AssignFnFixed;
845 CCAssignFn *AssignFnVarArg;
846 std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
847
848 // We have outgoing arguments. Make sure that we can tail call with them.
850 CCState OutInfo(CalleeCC, false, MF, OutLocs, Ctx);
851
852 AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
853 Subtarget, /*IsReturn*/ false);
854 if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo)) {
855 LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
856 return false;
857 }
858
859 // Make sure that they can fit on the caller's stack.
860 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
861 if (OutInfo.getStackSize() > FuncInfo->getBytesInStackArgArea()) {
862 LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
863 return false;
864 }
865
866 // Verify that the parameters in callee-saved registers match.
867 // TODO: Port this over to CallLowering as general code once swiftself is
868 // supported.
869 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
870 const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
872
873 if (Info.IsVarArg) {
874 // Be conservative and disallow variadic memory operands to match SDAG's
875 // behaviour.
876 // FIXME: If the caller's calling convention is C, then we can
877 // potentially use its argument area. However, for cases like fastcc,
878 // we can't do anything.
879 for (unsigned i = 0; i < OutLocs.size(); ++i) {
880 auto &ArgLoc = OutLocs[i];
881 if (ArgLoc.isRegLoc())
882 continue;
883
885 dbgs()
886 << "... Cannot tail call vararg function with stack arguments\n");
887 return false;
888 }
889 }
890
891 return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
892}
893
895 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
897 SmallVectorImpl<ArgInfo> &OutArgs) const {
898
899 // Must pass all target-independent checks in order to tail call optimize.
900 if (!Info.IsTailCall)
901 return false;
902
903 CallingConv::ID CalleeCC = Info.CallConv;
904 MachineFunction &MF = MIRBuilder.getMF();
905 const Function &CallerF = MF.getFunction();
906
907 LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
908
909 if (Info.SwiftErrorVReg) {
910 // TODO: We should handle this.
911 // Note that this is also handled by the check for no outgoing arguments.
912 // Proactively disabling this though, because the swifterror handling in
913 // lowerCall inserts a COPY *after* the location of the call.
914 LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
915 return false;
916 }
917
918 if (!mayTailCallThisCC(CalleeCC)) {
919 LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
920 return false;
921 }
922
923 // Byval parameters hand the function a pointer directly into the stack area
924 // we want to reuse during a tail call. Working around this *is* possible (see
925 // X86).
926 //
927 // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
928 // it?
929 //
930 // On Windows, "inreg" attributes signify non-aggregate indirect returns.
931 // In this case, it is necessary to save/restore X0 in the callee. Tail
932 // call opt interferes with this. So we disable tail call opt when the
933 // caller has an argument with "inreg" attribute.
934 //
935 // FIXME: Check whether the callee also has an "inreg" argument.
936 //
937 // When the caller has a swifterror argument, we don't want to tail call
938 // because would have to move into the swifterror register before the
939 // tail call.
940 if (any_of(CallerF.args(), [](const Argument &A) {
941 return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
942 })) {
943 LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
944 "inreg, or swifterror arguments\n");
945 return false;
946 }
947
948 // Externally-defined functions with weak linkage should not be
949 // tail-called on AArch64 when the OS does not support dynamic
950 // pre-emption of symbols, as the AAELF spec requires normal calls
951 // to undefined weak functions to be replaced with a NOP or jump to the
952 // next instruction. The behaviour of branch instructions in this
953 // situation (as used for tail calls) is implementation-defined, so we
954 // cannot rely on the linker replacing the tail call with a return.
955 if (Info.Callee.isGlobal()) {
956 const GlobalValue *GV = Info.Callee.getGlobal();
957 const Triple &TT = MF.getTarget().getTargetTriple();
958 if (GV->hasExternalWeakLinkage() &&
959 (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
960 TT.isOSBinFormatMachO())) {
961 LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
962 "with weak linkage for this OS.\n");
963 return false;
964 }
965 }
966
967 // If we have -tailcallopt, then we're done.
969 return CalleeCC == CallerF.getCallingConv();
970
971 // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
972 // Try to find cases where we can do that.
973
974 // I want anyone implementing a new calling convention to think long and hard
975 // about this assert.
976 assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
977 "Unexpected variadic calling convention");
978
979 // Verify that the incoming and outgoing arguments from the callee are
980 // safe to tail call.
981 if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
983 dbgs()
984 << "... Caller and callee have incompatible calling conventions.\n");
985 return false;
986 }
987
988 if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
989 return false;
990
992 dbgs() << "... Call is eligible for tail call optimization.\n");
993 return true;
994}
995
996static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
997 bool IsTailCall) {
998 if (!IsTailCall)
999 return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
1000
1001 if (!IsIndirect)
1002 return AArch64::TCRETURNdi;
1003
1004 // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
1005 // x16 or x17.
1007 return AArch64::TCRETURNriBTI;
1008
1009 return AArch64::TCRETURNri;
1010}
1011
1012static const uint32_t *
1016 const uint32_t *Mask;
1017 if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
1018 // For 'this' returns, use the X0-preserving mask if applicable
1019 Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
1020 if (!Mask) {
1021 OutArgs[0].Flags[0].setReturned(false);
1022 Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
1023 }
1024 } else {
1025 Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
1026 }
1027 return Mask;
1028}
1029
1030bool AArch64CallLowering::lowerTailCall(
1031 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1032 SmallVectorImpl<ArgInfo> &OutArgs) const {
1033 MachineFunction &MF = MIRBuilder.getMF();
1034 const Function &F = MF.getFunction();
1036 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1038
1039 // True when we're tail calling, but without -tailcallopt.
1040 bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt &&
1041 Info.CallConv != CallingConv::Tail &&
1042 Info.CallConv != CallingConv::SwiftTail;
1043
1044 // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
1045 // register class. Until we can do that, we should fall back here.
1047 LLVM_DEBUG(
1048 dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
1049 return false;
1050 }
1051
1052 // Find out which ABI gets to decide where things go.
1053 CallingConv::ID CalleeCC = Info.CallConv;
1054 CCAssignFn *AssignFnFixed;
1055 CCAssignFn *AssignFnVarArg;
1056 std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1057
1058 MachineInstrBuilder CallSeqStart;
1059 if (!IsSibCall)
1060 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1061
1062 unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
1063 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1064 MIB.add(Info.Callee);
1065
1066 // Byte offset for the tail call. When we are sibcalling, this will always
1067 // be 0.
1068 MIB.addImm(0);
1069
1070 // Tell the call which registers are clobbered.
1071 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1072 auto TRI = Subtarget.getRegisterInfo();
1073 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
1074 if (Subtarget.hasCustomCallingConv())
1075 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1076 MIB.addRegMask(Mask);
1077
1078 if (Info.CFIType)
1079 MIB->setCFIType(MF, Info.CFIType->getZExtValue());
1080
1081 if (TRI->isAnyArgRegReserved(MF))
1082 TRI->emitReservedArgRegCallError(MF);
1083
1084 // FPDiff is the byte offset of the call's argument area from the callee's.
1085 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1086 // by this amount for a tail call. In a sibling call it must be 0 because the
1087 // caller will deallocate the entire stack and the callee still expects its
1088 // arguments to begin at SP+0.
1089 int FPDiff = 0;
1090
1091 // This will be 0 for sibcalls, potentially nonzero for tail calls produced
1092 // by -tailcallopt. For sibcalls, the memory operands for the call are
1093 // already available in the caller's incoming argument space.
1094 unsigned NumBytes = 0;
1095 if (!IsSibCall) {
1096 // We aren't sibcalling, so we need to compute FPDiff. We need to do this
1097 // before handling assignments, because FPDiff must be known for memory
1098 // arguments.
1099 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1101 CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
1102
1103 AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
1104 Subtarget, /*IsReturn*/ false);
1105 if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
1106 return false;
1107
1108 // The callee will pop the argument stack as a tail call. Thus, we must
1109 // keep it 16-byte aligned.
1110 NumBytes = alignTo(OutInfo.getStackSize(), 16);
1111
1112 // FPDiff will be negative if this tail call requires more space than we
1113 // would automatically have in our incoming argument space. Positive if we
1114 // actually shrink the stack.
1115 FPDiff = NumReusableBytes - NumBytes;
1116
1117 // Update the required reserved area if this is the tail call requiring the
1118 // most argument stack space.
1119 if (FPDiff < 0 && FuncInfo->getTailCallReservedStack() < (unsigned)-FPDiff)
1120 FuncInfo->setTailCallReservedStack(-FPDiff);
1121
1122 // The stack pointer must be 16-byte aligned at all times it's used for a
1123 // memory operation, which in practice means at *all* times and in
1124 // particular across call boundaries. Therefore our own arguments started at
1125 // a 16-byte aligned SP and the delta applied for the tail call should
1126 // satisfy the same constraint.
1127 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1128 }
1129
1130 const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
1131
1132 AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1133 Subtarget, /*IsReturn*/ false);
1134
1135 // Do the actual argument marshalling.
1136 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB,
1137 /*IsTailCall*/ true, FPDiff);
1138 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1139 CalleeCC, Info.IsVarArg))
1140 return false;
1141
1142 Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1143
1144 if (Info.IsVarArg && Info.IsMustTailCall) {
1145 // Now we know what's being passed to the function. Add uses to the call for
1146 // the forwarded registers that we *aren't* passing as parameters. This will
1147 // preserve the copies we build earlier.
1148 for (const auto &F : Forwards) {
1149 Register ForwardedReg = F.PReg;
1150 // If the register is already passed, or aliases a register which is
1151 // already being passed, then skip it.
1152 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
1153 if (!Use.isReg())
1154 return false;
1155 return TRI->regsOverlap(Use.getReg(), ForwardedReg);
1156 }))
1157 continue;
1158
1159 // We aren't passing it already, so we should add it to the call.
1160 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1161 MIB.addReg(ForwardedReg, RegState::Implicit);
1162 }
1163 }
1164
1165 // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1166 // sequence start and end here.
1167 if (!IsSibCall) {
1168 MIB->getOperand(1).setImm(FPDiff);
1169 CallSeqStart.addImm(0).addImm(0);
1170 // End the call sequence *before* emitting the call. Normally, we would
1171 // tidy the frame up after the call. However, here, we've laid out the
1172 // parameters so that when SP is reset, they will be in the correct
1173 // location.
1174 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1175 }
1176
1177 // Now we can add the actual call instruction to the correct basic block.
1178 MIRBuilder.insertInstr(MIB);
1179
1180 // If Callee is a reg, since it is used by a target specific instruction,
1181 // it must have a register class matching the constraint of that instruction.
1182 if (MIB->getOperand(0).isReg())
1184 *MF.getSubtarget().getRegBankInfo(), *MIB,
1185 MIB->getDesc(), MIB->getOperand(0), 0);
1186
1188 Info.LoweredTailCall = true;
1189 return true;
1190}
1191
1193 CallLoweringInfo &Info) const {
1194 MachineFunction &MF = MIRBuilder.getMF();
1195 const Function &F = MF.getFunction();
1197 auto &DL = F.getParent()->getDataLayout();
1198 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1199 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1200
1201 // Arm64EC has extra requirements for varargs calls; bail out for now.
1202 if (Info.IsVarArg && Subtarget.isWindowsArm64EC())
1203 return false;
1204
1206 for (auto &OrigArg : Info.OrigArgs) {
1207 splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1208 // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
1209 auto &Flags = OrigArg.Flags[0];
1210 if (OrigArg.Ty->isIntegerTy(1) && !Flags.isSExt() && !Flags.isZExt()) {
1211 ArgInfo &OutArg = OutArgs.back();
1212 assert(OutArg.Regs.size() == 1 &&
1213 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 &&
1214 "Unexpected registers used for i1 arg");
1215
1216 // We cannot use a ZExt ArgInfo flag here, because it will
1217 // zero-extend the argument to i32 instead of just i8.
1218 OutArg.Regs[0] =
1219 MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
1220 LLVMContext &Ctx = MF.getFunction().getContext();
1221 OutArg.Ty = Type::getInt8Ty(Ctx);
1222 }
1223 }
1224
1226 if (!Info.OrigRet.Ty->isVoidTy())
1227 splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1228
1229 // If we can lower as a tail call, do that instead.
1230 bool CanTailCallOpt =
1231 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1232
1233 // We must emit a tail call if we have musttail.
1234 if (Info.IsMustTailCall && !CanTailCallOpt) {
1235 // There are types of incoming/outgoing arguments we can't handle yet, so
1236 // it doesn't make sense to actually die here like in ISelLowering. Instead,
1237 // fall back to SelectionDAG and let it try to handle this.
1238 LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1239 return false;
1240 }
1241
1242 Info.IsTailCall = CanTailCallOpt;
1243 if (CanTailCallOpt)
1244 return lowerTailCall(MIRBuilder, Info, OutArgs);
1245
1246 // Find out which ABI gets to decide where things go.
1247 CCAssignFn *AssignFnFixed;
1248 CCAssignFn *AssignFnVarArg;
1249 std::tie(AssignFnFixed, AssignFnVarArg) =
1250 getAssignFnsForCC(Info.CallConv, TLI);
1251
1252 MachineInstrBuilder CallSeqStart;
1253 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1254
1255 // Create a temporarily-floating call instruction so we can add the implicit
1256 // uses of arg registers.
1257
1258 unsigned Opc = 0;
1259 // Calls with operand bundle "clang.arc.attachedcall" are special. They should
1260 // be expanded to the call, directly followed by a special marker sequence and
1261 // a call to an ObjC library function.
1263 Opc = AArch64::BLR_RVMARKER;
1264 // A call to a returns twice function like setjmp must be followed by a bti
1265 // instruction.
1266 else if (Info.CB && Info.CB->hasFnAttr(Attribute::ReturnsTwice) &&
1267 !Subtarget.noBTIAtReturnTwice() &&
1269 Opc = AArch64::BLR_BTI;
1270 else
1271 Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1272
1273 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1274 unsigned CalleeOpNo = 0;
1275
1276 if (Opc == AArch64::BLR_RVMARKER) {
1277 // Add a target global address for the retainRV/claimRV runtime function
1278 // just before the call target.
1280 MIB.addGlobalAddress(ARCFn);
1281 ++CalleeOpNo;
1282 } else if (Info.CFIType) {
1283 MIB->setCFIType(MF, Info.CFIType->getZExtValue());
1284 }
1285
1286 MIB.add(Info.Callee);
1287
1288 // Tell the call which registers are clobbered.
1289 const uint32_t *Mask;
1290 const auto *TRI = Subtarget.getRegisterInfo();
1291
1292 AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1293 Subtarget, /*IsReturn*/ false);
1294 // Do the actual argument marshalling.
1295 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, /*IsReturn*/ false);
1296 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1297 Info.CallConv, Info.IsVarArg))
1298 return false;
1299
1300 Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1301
1303 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1304 MIB.addRegMask(Mask);
1305
1306 if (TRI->isAnyArgRegReserved(MF))
1307 TRI->emitReservedArgRegCallError(MF);
1308
1309 // Now we can add the actual call instruction to the correct basic block.
1310 MIRBuilder.insertInstr(MIB);
1311
1312 uint64_t CalleePopBytes =
1315 ? alignTo(Assigner.StackSize, 16)
1316 : 0;
1317
1318 CallSeqStart.addImm(Assigner.StackSize).addImm(0);
1319 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1320 .addImm(Assigner.StackSize)
1321 .addImm(CalleePopBytes);
1322
1323 // If Callee is a reg, since it is used by a target specific
1324 // instruction, it must have a register class matching the
1325 // constraint of that instruction.
1326 if (MIB->getOperand(CalleeOpNo).isReg())
1327 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
1328 *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
1329 MIB->getOperand(CalleeOpNo), CalleeOpNo);
1330
1331 // Finally we can copy the returned value back into its virtual-register. In
1332 // symmetry with the arguments, the physical register must be an
1333 // implicit-define of the call instruction.
1334 if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
1335 CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1336 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1337 bool UsingReturnedArg =
1338 !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1339
1340 AArch64OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn, Subtarget,
1341 /*IsReturn*/ false);
1342 ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB);
1344 UsingReturnedArg ? ReturnedArgHandler : Handler, Assigner, InArgs,
1345 MIRBuilder, Info.CallConv, Info.IsVarArg,
1346 UsingReturnedArg ? ArrayRef(OutArgs[0].Regs) : std::nullopt))
1347 return false;
1348 }
1349
1350 if (Info.SwiftErrorVReg) {
1351 MIB.addDef(AArch64::X21, RegState::Implicit);
1352 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1353 }
1354
1355 if (!Info.CanLowerReturn) {
1356 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
1357 Info.DemoteRegister, Info.DemoteStackIndex);
1358 }
1359 return true;
1360}
1361
1363 return Ty.getSizeInBits() == 64;
1364}
unsigned const MachineRegisterInfo * MRI
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
static LLT getStackValueStoreTypeHack(const CCValAssign &VA)
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, MVT &LocVT)
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
This file describes how to lower LLVM calls to machine code calls.
#define Success
static const MCPhysReg GPRArgRegs[]
static const MCPhysReg FPRArgRegs[]
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Addr
uint64_t Size
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
This file defines ARC utility functions which are used by various parts of the compiler.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const override
This hook must be implemented to check whether the return values described by Outs can fit into the r...
bool fallBackToDAGISel(const MachineFunction &MF) const override
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
AArch64CallLowering(const AArch64TargetLowering &TLI)
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
void setTailCallReservedStack(unsigned bytes)
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
void setBytesInStackArgArea(unsigned bytes)
void setArgumentStackToRestore(unsigned bytes)
const AArch64RegisterInfo * getRegisterInfo() const override
const AArch64InstrInfo * getInstrInfo() const override
bool isCallingConvWin64(CallingConv::ID CC) const
const RegisterBankInfo * getRegBankInfo() const override
bool hasCustomCallingConv() const
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
CallingConv::ID getCallingConv() const
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
bool isVarArg() const
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
CCValAssign - Represent assignment of one arg/retval to a location.
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
iterator_range< arg_iterator > args()
Definition: Function.h:802
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:239
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:320
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:524
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:149
constexpr bool isVector() const
Definition: LowLevelType.h:145
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:49
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:175
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:185
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:573
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasTailCall(bool V=true)
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SMEAttrs is a utility class to parse the SME ACLE attributes on functions.
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
void push_back(const T &Elt)
Definition: SmallVector.h:416
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
const Triple & getTargetTriple() const
TargetOptions Options
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
static IntegerType * getInt8Ty(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned getNumOperands() const
Definition: User.h:191
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
ArrayRef< MCPhysReg > getFPRArgRegs()
ArrayRef< MCPhysReg > getGPRArgRegs()
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:119
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ PreserveMost
Used for runtime calls that preserves most registers.
Definition: CallingConv.h:63
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ Implicit
Not emitted register (e.g. carry, or temporary result).
std::optional< Function * > getAttachedARCFunction(const CallBase *CB)
This function returns operand bundle clang_arc_attachedcall's argument, which is the address of the A...
Definition: ObjCARCUtil.h:43
bool hasAttachedCallOpBundle(const CallBase *CB)
Definition: ObjCARCUtil.h:29
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< TypeSize > *Offsets, TypeSize StartingOffset)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:122
@ Offset
Definition: DWP.cpp:440
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:53
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1734
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:716
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:320
void assignValueToReg(Register ValVReg, Register PhysReg, CCValAssign VA) override
Provides a default implementation for argument handling.
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:335
MachineRegisterInfo & MRI
Definition: CallLowering.h:233
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:194
Describes a register that needs to be forwarded from the prologue to a musttail call.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.