LLVM 19.0.0git
AArch64CallLowering.cpp
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1//===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the lowering of LLVM calls to machine code calls for
11/// GlobalISel.
12///
13//===----------------------------------------------------------------------===//
14
15#include "AArch64CallLowering.h"
16#include "AArch64ISelLowering.h"
18#include "AArch64RegisterInfo.h"
19#include "AArch64Subtarget.h"
20#include "llvm/ADT/ArrayRef.h"
40#include "llvm/IR/Argument.h"
41#include "llvm/IR/Attributes.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include <algorithm>
46#include <cassert>
47#include <cstdint>
48#include <iterator>
49
50#define DEBUG_TYPE "aarch64-call-lowering"
51
52using namespace llvm;
53
55 : CallLowering(&TLI) {}
56
57static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT,
58 MVT &LocVT) {
59 // If ValVT is i1/i8/i16, we should set LocVT to i8/i8/i16. This is a legacy
60 // hack because the DAG calls the assignment function with pre-legalized
61 // register typed values, not the raw type.
62 //
63 // This hack is not applied to return values which are not passed on the
64 // stack.
65 if (OrigVT == MVT::i1 || OrigVT == MVT::i8)
66 ValVT = LocVT = MVT::i8;
67 else if (OrigVT == MVT::i16)
68 ValVT = LocVT = MVT::i16;
69}
70
71// Account for i1/i8/i16 stack passed value hack
73 const MVT ValVT = VA.getValVT();
74 return (ValVT == MVT::i8 || ValVT == MVT::i16) ? LLT(ValVT)
75 : LLT(VA.getLocVT());
76}
77
78namespace {
79
80struct AArch64IncomingValueAssigner
82 AArch64IncomingValueAssigner(CCAssignFn *AssignFn_,
83 CCAssignFn *AssignFnVarArg_)
84 : IncomingValueAssigner(AssignFn_, AssignFnVarArg_) {}
85
86 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
89 CCState &State) override {
90 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
91 return IncomingValueAssigner::assignArg(ValNo, OrigVT, ValVT, LocVT,
92 LocInfo, Info, Flags, State);
93 }
94};
95
96struct AArch64OutgoingValueAssigner
98 const AArch64Subtarget &Subtarget;
99
100 /// Track if this is used for a return instead of function argument
101 /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
102 /// stack passed returns for them and cannot apply the type adjustment.
103 bool IsReturn;
104
105 AArch64OutgoingValueAssigner(CCAssignFn *AssignFn_,
106 CCAssignFn *AssignFnVarArg_,
107 const AArch64Subtarget &Subtarget_,
108 bool IsReturn)
109 : OutgoingValueAssigner(AssignFn_, AssignFnVarArg_),
110 Subtarget(Subtarget_), IsReturn(IsReturn) {}
111
112 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
113 CCValAssign::LocInfo LocInfo,
115 CCState &State) override {
116 bool IsCalleeWin = Subtarget.isCallingConvWin64(State.getCallingConv());
117 bool UseVarArgsCCForFixed = IsCalleeWin && State.isVarArg();
118
119 bool Res;
120 if (Info.IsFixed && !UseVarArgsCCForFixed) {
121 if (!IsReturn)
122 applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
123 Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
124 } else
125 Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
126
127 StackSize = State.getStackSize();
128 return Res;
129 }
130};
131
132struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
133 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
134 : IncomingValueHandler(MIRBuilder, MRI) {}
135
136 Register getStackAddress(uint64_t Size, int64_t Offset,
138 ISD::ArgFlagsTy Flags) override {
139 auto &MFI = MIRBuilder.getMF().getFrameInfo();
140
141 // Byval is assumed to be writable memory, but other stack passed arguments
142 // are not.
143 const bool IsImmutable = !Flags.isByVal();
144
145 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
146 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
147 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI);
148 return AddrReg.getReg(0);
149 }
150
151 LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
152 ISD::ArgFlagsTy Flags) const override {
153 // For pointers, we just need to fixup the integer types reported in the
154 // CCValAssign.
155 if (Flags.isPointer())
158 }
159
160 void assignValueToReg(Register ValVReg, Register PhysReg,
161 const CCValAssign &VA) override {
162 markPhysRegUsed(PhysReg);
163 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
164 }
165
166 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
167 const MachinePointerInfo &MPO,
168 const CCValAssign &VA) override {
169 MachineFunction &MF = MIRBuilder.getMF();
170
171 LLT ValTy(VA.getValVT());
172 LLT LocTy(VA.getLocVT());
173
174 // Fixup the types for the DAG compatibility hack.
175 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
176 std::swap(ValTy, LocTy);
177 else {
178 // The calling code knows if this is a pointer or not, we're only touching
179 // the LocTy for the i8/i16 hack.
180 assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
181 LocTy = MemTy;
182 }
183
184 auto MMO = MF.getMachineMemOperand(
186 inferAlignFromPtrInfo(MF, MPO));
187
188 switch (VA.getLocInfo()) {
189 case CCValAssign::LocInfo::ZExt:
190 MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, ValVReg, Addr, *MMO);
191 return;
192 case CCValAssign::LocInfo::SExt:
193 MIRBuilder.buildLoadInstr(TargetOpcode::G_SEXTLOAD, ValVReg, Addr, *MMO);
194 return;
195 default:
196 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
197 return;
198 }
199 }
200
201 /// How the physical register gets marked varies between formal
202 /// parameters (it's a basic-block live-in), and a call instruction
203 /// (it's an implicit-def of the BL).
204 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
205};
206
207struct FormalArgHandler : public IncomingArgHandler {
209 : IncomingArgHandler(MIRBuilder, MRI) {}
210
211 void markPhysRegUsed(MCRegister PhysReg) override {
212 MIRBuilder.getMRI()->addLiveIn(PhysReg);
213 MIRBuilder.getMBB().addLiveIn(PhysReg);
214 }
215};
216
217struct CallReturnHandler : public IncomingArgHandler {
218 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
220 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
221
222 void markPhysRegUsed(MCRegister PhysReg) override {
223 MIB.addDef(PhysReg, RegState::Implicit);
224 }
225
227};
228
229/// A special return arg handler for "returned" attribute arg calls.
230struct ReturnedArgCallReturnHandler : public CallReturnHandler {
231 ReturnedArgCallReturnHandler(MachineIRBuilder &MIRBuilder,
234 : CallReturnHandler(MIRBuilder, MRI, MIB) {}
235
236 void markPhysRegUsed(MCRegister PhysReg) override {}
237};
238
239struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
240 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
241 MachineInstrBuilder MIB, bool IsTailCall = false,
242 int FPDiff = 0)
243 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall),
244 FPDiff(FPDiff),
245 Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
246
247 Register getStackAddress(uint64_t Size, int64_t Offset,
249 ISD::ArgFlagsTy Flags) override {
250 MachineFunction &MF = MIRBuilder.getMF();
251 LLT p0 = LLT::pointer(0, 64);
252 LLT s64 = LLT::scalar(64);
253
254 if (IsTailCall) {
255 assert(!Flags.isByVal() && "byval unhandled with tail calls");
256
257 Offset += FPDiff;
258 int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
259 auto FIReg = MIRBuilder.buildFrameIndex(p0, FI);
261 return FIReg.getReg(0);
262 }
263
264 if (!SPReg)
265 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0);
266
267 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset);
268
269 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
270
272 return AddrReg.getReg(0);
273 }
274
275 /// We need to fixup the reported store size for certain value types because
276 /// we invert the interpretation of ValVT and LocVT in certain cases. This is
277 /// for compatability with the DAG call lowering implementation, which we're
278 /// currently building on top of.
279 LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
280 ISD::ArgFlagsTy Flags) const override {
281 if (Flags.isPointer())
284 }
285
286 void assignValueToReg(Register ValVReg, Register PhysReg,
287 const CCValAssign &VA) override {
288 MIB.addUse(PhysReg, RegState::Implicit);
289 Register ExtReg = extendRegister(ValVReg, VA);
290 MIRBuilder.buildCopy(PhysReg, ExtReg);
291 }
292
293 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
294 const MachinePointerInfo &MPO,
295 const CCValAssign &VA) override {
296 MachineFunction &MF = MIRBuilder.getMF();
297 auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
298 inferAlignFromPtrInfo(MF, MPO));
299 MIRBuilder.buildStore(ValVReg, Addr, *MMO);
300 }
301
302 void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
303 Register Addr, LLT MemTy,
304 const MachinePointerInfo &MPO,
305 const CCValAssign &VA) override {
306 unsigned MaxSize = MemTy.getSizeInBytes() * 8;
307 // For varargs, we always want to extend them to 8 bytes, in which case
308 // we disable setting a max.
309 if (!Arg.IsFixed)
310 MaxSize = 0;
311
312 Register ValVReg = Arg.Regs[RegIndex];
313 if (VA.getLocInfo() != CCValAssign::LocInfo::FPExt) {
314 MVT LocVT = VA.getLocVT();
315 MVT ValVT = VA.getValVT();
316
317 if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16) {
318 std::swap(ValVT, LocVT);
319 MemTy = LLT(VA.getValVT());
320 }
321
322 ValVReg = extendRegister(ValVReg, VA, MaxSize);
323 } else {
324 // The store does not cover the full allocated stack slot.
325 MemTy = LLT(VA.getValVT());
326 }
327
328 assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
329 }
330
332
333 bool IsTailCall;
334
335 /// For tail calls, the byte offset of the call's argument area from the
336 /// callee's. Unused elsewhere.
337 int FPDiff;
338
339 // Cache the SP register vreg if we need it more than once in this call site.
340 Register SPReg;
341
342 const AArch64Subtarget &Subtarget;
343};
344} // namespace
345
346static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
347 return (CallConv == CallingConv::Fast && TailCallOpt) ||
348 CallConv == CallingConv::Tail || CallConv == CallingConv::SwiftTail;
349}
350
352 const Value *Val,
353 ArrayRef<Register> VRegs,
355 Register SwiftErrorVReg) const {
356 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
357 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
358 "Return value without a vreg");
359
360 bool Success = true;
361 if (!FLI.CanLowerReturn) {
362 insertSRetStores(MIRBuilder, Val->getType(), VRegs, FLI.DemoteRegister);
363 } else if (!VRegs.empty()) {
364 MachineFunction &MF = MIRBuilder.getMF();
365 const Function &F = MF.getFunction();
366 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
367
369 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
370 CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
371 auto &DL = F.getParent()->getDataLayout();
372 LLVMContext &Ctx = Val->getType()->getContext();
373
374 SmallVector<EVT, 4> SplitEVTs;
375 ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
376 assert(VRegs.size() == SplitEVTs.size() &&
377 "For each split Type there should be exactly one VReg.");
378
379 SmallVector<ArgInfo, 8> SplitArgs;
380 CallingConv::ID CC = F.getCallingConv();
381
382 for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
383 Register CurVReg = VRegs[i];
384 ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx), 0};
386
387 // i1 is a special case because SDAG i1 true is naturally zero extended
388 // when widened using ANYEXT. We need to do it explicitly here.
389 auto &Flags = CurArgInfo.Flags[0];
390 if (MRI.getType(CurVReg).getSizeInBits() == 1 && !Flags.isSExt() &&
391 !Flags.isZExt()) {
392 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
393 } else if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) ==
394 1) {
395 // Some types will need extending as specified by the CC.
396 MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
397 if (EVT(NewVT) != SplitEVTs[i]) {
398 unsigned ExtendOp = TargetOpcode::G_ANYEXT;
399 if (F.getAttributes().hasRetAttr(Attribute::SExt))
400 ExtendOp = TargetOpcode::G_SEXT;
401 else if (F.getAttributes().hasRetAttr(Attribute::ZExt))
402 ExtendOp = TargetOpcode::G_ZEXT;
403
404 LLT NewLLT(NewVT);
405 LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
406 CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
407 // Instead of an extend, we might have a vector type which needs
408 // padding with more elements, e.g. <2 x half> -> <4 x half>.
409 if (NewVT.isVector()) {
410 if (OldLLT.isVector()) {
411 if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
412
413 CurVReg =
414 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
415 .getReg(0);
416 } else {
417 // Just do a vector extend.
418 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
419 .getReg(0);
420 }
421 } else if (NewLLT.getNumElements() >= 2 &&
422 NewLLT.getNumElements() <= 8) {
423 // We need to pad a <1 x S> type to <2/4/8 x S>. Since we don't
424 // have <1 x S> vector types in GISel we use a build_vector
425 // instead of a vector merge/concat.
426 CurVReg =
427 MIRBuilder.buildPadVectorWithUndefElements(NewLLT, CurVReg)
428 .getReg(0);
429 } else {
430 LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
431 return false;
432 }
433 } else {
434 // If the split EVT was a <1 x T> vector, and NewVT is T, then we
435 // don't have to do anything since we don't distinguish between the
436 // two.
437 if (NewLLT != MRI.getType(CurVReg)) {
438 // A scalar extend.
439 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
440 .getReg(0);
441 }
442 }
443 }
444 }
445 if (CurVReg != CurArgInfo.Regs[0]) {
446 CurArgInfo.Regs[0] = CurVReg;
447 // Reset the arg flags after modifying CurVReg.
449 }
450 splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
451 }
452
453 AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget,
454 /*IsReturn*/ true);
455 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
456 Success = determineAndHandleAssignments(Handler, Assigner, SplitArgs,
457 MIRBuilder, CC, F.isVarArg());
458 }
459
460 if (SwiftErrorVReg) {
461 MIB.addUse(AArch64::X21, RegState::Implicit);
462 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
463 }
464
465 MIRBuilder.insertInstr(MIB);
466 return Success;
467}
468
470 CallingConv::ID CallConv,
472 bool IsVarArg) const {
474 const auto &TLI = *getTLI<AArch64TargetLowering>();
475 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
476 MF.getFunction().getContext());
477
478 return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv));
479}
480
481/// Helper function to compute forwarded registers for musttail calls. Computes
482/// the forwarded registers, sets MBB liveness, and emits COPY instructions that
483/// can be used to save + restore registers later.
485 CCAssignFn *AssignFn) {
486 MachineBasicBlock &MBB = MIRBuilder.getMBB();
487 MachineFunction &MF = MIRBuilder.getMF();
488 MachineFrameInfo &MFI = MF.getFrameInfo();
489
490 if (!MFI.hasMustTailInVarArgFunc())
491 return;
492
494 const Function &F = MF.getFunction();
495 assert(F.isVarArg() && "Expected F to be vararg?");
496
497 // Compute the set of forwarded registers. The rest are scratch.
499 CCState CCInfo(F.getCallingConv(), /*IsVarArg=*/true, MF, ArgLocs,
500 F.getContext());
501 SmallVector<MVT, 2> RegParmTypes;
502 RegParmTypes.push_back(MVT::i64);
503 RegParmTypes.push_back(MVT::f128);
504
505 // Later on, we can use this vector to restore the registers if necessary.
508 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, AssignFn);
509
510 // Conservatively forward X8, since it might be used for an aggregate
511 // return.
512 if (!CCInfo.isAllocated(AArch64::X8)) {
513 Register X8VReg = MF.addLiveIn(AArch64::X8, &AArch64::GPR64RegClass);
514 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
515 }
516
517 // Add the forwards to the MachineBasicBlock and MachineFunction.
518 for (const auto &F : Forwards) {
519 MBB.addLiveIn(F.PReg);
520 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg));
521 }
522}
523
525 auto &F = MF.getFunction();
526 if (F.getReturnType()->isScalableTy() ||
527 llvm::any_of(F.args(), [](const Argument &A) {
528 return A.getType()->isScalableTy();
529 }))
530 return true;
531 const auto &ST = MF.getSubtarget<AArch64Subtarget>();
532 if (!ST.hasNEON() || !ST.hasFPARMv8()) {
533 LLVM_DEBUG(dbgs() << "Falling back to SDAG because we don't support no-NEON\n");
534 return true;
535 }
536
537 SMEAttrs Attrs(F);
538 if (Attrs.hasZAState() || Attrs.hasStreamingInterfaceOrBody() ||
539 Attrs.hasStreamingCompatibleInterface())
540 return true;
541
542 return false;
543}
544
545void AArch64CallLowering::saveVarArgRegisters(
547 CCState &CCInfo) const {
550
551 MachineFunction &MF = MIRBuilder.getMF();
553 MachineFrameInfo &MFI = MF.getFrameInfo();
555 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
556 bool IsWin64CC =
557 Subtarget.isCallingConvWin64(CCInfo.getCallingConv());
558 const LLT p0 = LLT::pointer(0, 64);
559 const LLT s64 = LLT::scalar(64);
560
561 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
562 unsigned NumVariadicGPRArgRegs = GPRArgRegs.size() - FirstVariadicGPR + 1;
563
564 unsigned GPRSaveSize = 8 * (GPRArgRegs.size() - FirstVariadicGPR);
565 int GPRIdx = 0;
566 if (GPRSaveSize != 0) {
567 if (IsWin64CC) {
568 GPRIdx = MFI.CreateFixedObject(GPRSaveSize,
569 -static_cast<int>(GPRSaveSize), false);
570 if (GPRSaveSize & 15)
571 // The extra size here, if triggered, will always be 8.
572 MFI.CreateFixedObject(16 - (GPRSaveSize & 15),
573 -static_cast<int>(alignTo(GPRSaveSize, 16)),
574 false);
575 } else
576 GPRIdx = MFI.CreateStackObject(GPRSaveSize, Align(8), false);
577
578 auto FIN = MIRBuilder.buildFrameIndex(p0, GPRIdx);
579 auto Offset =
580 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 8);
581
582 for (unsigned i = FirstVariadicGPR; i < GPRArgRegs.size(); ++i) {
583 Register Val = MRI.createGenericVirtualRegister(s64);
584 Handler.assignValueToReg(
585 Val, GPRArgRegs[i],
587 GPRArgRegs[i], MVT::i64, CCValAssign::Full));
588 auto MPO = IsWin64CC ? MachinePointerInfo::getFixedStack(
589 MF, GPRIdx, (i - FirstVariadicGPR) * 8)
590 : MachinePointerInfo::getStack(MF, i * 8);
591 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
592
593 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
594 FIN.getReg(0), Offset);
595 }
596 }
597 FuncInfo->setVarArgsGPRIndex(GPRIdx);
598 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
599
600 if (Subtarget.hasFPARMv8() && !IsWin64CC) {
601 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
602
603 unsigned FPRSaveSize = 16 * (FPRArgRegs.size() - FirstVariadicFPR);
604 int FPRIdx = 0;
605 if (FPRSaveSize != 0) {
606 FPRIdx = MFI.CreateStackObject(FPRSaveSize, Align(16), false);
607
608 auto FIN = MIRBuilder.buildFrameIndex(p0, FPRIdx);
609 auto Offset =
610 MIRBuilder.buildConstant(MRI.createGenericVirtualRegister(s64), 16);
611
612 for (unsigned i = FirstVariadicFPR; i < FPRArgRegs.size(); ++i) {
613 Register Val = MRI.createGenericVirtualRegister(LLT::scalar(128));
614 Handler.assignValueToReg(
615 Val, FPRArgRegs[i],
617 i + MF.getFunction().getNumOperands() + NumVariadicGPRArgRegs,
618 MVT::f128, FPRArgRegs[i], MVT::f128, CCValAssign::Full));
619
620 auto MPO = MachinePointerInfo::getStack(MF, i * 16);
621 MIRBuilder.buildStore(Val, FIN, MPO, inferAlignFromPtrInfo(MF, MPO));
622
623 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),
624 FIN.getReg(0), Offset);
625 }
626 }
627 FuncInfo->setVarArgsFPRIndex(FPRIdx);
628 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
629 }
630}
631
633 MachineIRBuilder &MIRBuilder, const Function &F,
635 MachineFunction &MF = MIRBuilder.getMF();
636 MachineBasicBlock &MBB = MIRBuilder.getMBB();
638 auto &DL = F.getParent()->getDataLayout();
639 auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
640
641 // Arm64EC has extra requirements for varargs calls which are only implemented
642 // in SelectionDAG; bail out for now.
643 if (F.isVarArg() && Subtarget.isWindowsArm64EC())
644 return false;
645
646 // Arm64EC thunks have a special calling convention which is only implemented
647 // in SelectionDAG; bail out for now.
648 if (F.getCallingConv() == CallingConv::ARM64EC_Thunk_Native ||
649 F.getCallingConv() == CallingConv::ARM64EC_Thunk_X64)
650 return false;
651
652 bool IsWin64 = Subtarget.isCallingConvWin64(F.getCallingConv()) && !Subtarget.isWindowsArm64EC();
653
654 SmallVector<ArgInfo, 8> SplitArgs;
656
657 // Insert the hidden sret parameter if the return value won't fit in the
658 // return registers.
659 if (!FLI.CanLowerReturn)
661
662 unsigned i = 0;
663 for (auto &Arg : F.args()) {
664 if (DL.getTypeStoreSize(Arg.getType()).isZero())
665 continue;
666
667 ArgInfo OrigArg{VRegs[i], Arg, i};
669
670 // i1 arguments are zero-extended to i8 by the caller. Emit a
671 // hint to reflect this.
672 if (OrigArg.Ty->isIntegerTy(1)) {
673 assert(OrigArg.Regs.size() == 1 &&
674 MRI.getType(OrigArg.Regs[0]).getSizeInBits() == 1 &&
675 "Unexpected registers used for i1 arg");
676
677 auto &Flags = OrigArg.Flags[0];
678 if (!Flags.isZExt() && !Flags.isSExt()) {
679 // Lower i1 argument as i8, and insert AssertZExt + Trunc later.
680 Register OrigReg = OrigArg.Regs[0];
681 Register WideReg = MRI.createGenericVirtualRegister(LLT::scalar(8));
682 OrigArg.Regs[0] = WideReg;
683 BoolArgs.push_back({OrigReg, WideReg});
684 }
685 }
686
687 if (Arg.hasAttribute(Attribute::SwiftAsync))
688 MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
689
690 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
691 ++i;
692 }
693
694 if (!MBB.empty())
695 MIRBuilder.setInstr(*MBB.begin());
696
697 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
698 CCAssignFn *AssignFn = TLI.CCAssignFnForCall(F.getCallingConv(), IsWin64 && F.isVarArg());
699
700 AArch64IncomingValueAssigner Assigner(AssignFn, AssignFn);
701 FormalArgHandler Handler(MIRBuilder, MRI);
703 CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
704 if (!determineAssignments(Assigner, SplitArgs, CCInfo) ||
705 !handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, MIRBuilder))
706 return false;
707
708 if (!BoolArgs.empty()) {
709 for (auto &KV : BoolArgs) {
710 Register OrigReg = KV.first;
711 Register WideReg = KV.second;
712 LLT WideTy = MRI.getType(WideReg);
713 assert(MRI.getType(OrigReg).getScalarSizeInBits() == 1 &&
714 "Unexpected bit size of a bool arg");
715 MIRBuilder.buildTrunc(
716 OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1).getReg(0));
717 }
718 }
719
721 uint64_t StackSize = Assigner.StackSize;
722 if (F.isVarArg()) {
723 if ((!Subtarget.isTargetDarwin() && !Subtarget.isWindowsArm64EC()) || IsWin64) {
724 // The AAPCS variadic function ABI is identical to the non-variadic
725 // one. As a result there may be more arguments in registers and we should
726 // save them for future reference.
727 // Win64 variadic functions also pass arguments in registers, but all
728 // float arguments are passed in integer registers.
729 saveVarArgRegisters(MIRBuilder, Handler, CCInfo);
730 } else if (Subtarget.isWindowsArm64EC()) {
731 return false;
732 }
733
734 // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
735 StackSize = alignTo(Assigner.StackSize, Subtarget.isTargetILP32() ? 4 : 8);
736
737 auto &MFI = MIRBuilder.getMF().getFrameInfo();
738 FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackSize, true));
739 }
740
741 if (doesCalleeRestoreStack(F.getCallingConv(),
743 // We have a non-standard ABI, so why not make full use of the stack that
744 // we're going to pop? It must be aligned to 16 B in any case.
745 StackSize = alignTo(StackSize, 16);
746
747 // If we're expected to restore the stack (e.g. fastcc), then we'll be
748 // adding a multiple of 16.
749 FuncInfo->setArgumentStackToRestore(StackSize);
750
751 // Our own callers will guarantee that the space is free by giving an
752 // aligned value to CALLSEQ_START.
753 }
754
755 // When we tail call, we need to check if the callee's arguments
756 // will fit on the caller's stack. So, whenever we lower formal arguments,
757 // we should keep track of this information, since we might lower a tail call
758 // in this function later.
759 FuncInfo->setBytesInStackArgArea(StackSize);
760
761 if (Subtarget.hasCustomCallingConv())
762 Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
763
764 handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
765
766 // Move back to the end of the basic block.
767 MIRBuilder.setMBB(MBB);
768
769 return true;
770}
771
772/// Return true if the calling convention is one that we can guarantee TCO for.
773static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls) {
774 return (CC == CallingConv::Fast && GuaranteeTailCalls) ||
776}
777
778/// Return true if we might ever do TCO for calls with this calling convention.
780 switch (CC) {
781 case CallingConv::C:
788 return true;
789 default:
790 return false;
791 }
792}
793
794/// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
795/// CC.
796static std::pair<CCAssignFn *, CCAssignFn *>
798 return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
799}
800
801bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
802 CallLoweringInfo &Info, MachineFunction &MF,
803 SmallVectorImpl<ArgInfo> &InArgs) const {
804 const Function &CallerF = MF.getFunction();
805 CallingConv::ID CalleeCC = Info.CallConv;
806 CallingConv::ID CallerCC = CallerF.getCallingConv();
807
808 // If the calling conventions match, then everything must be the same.
809 if (CalleeCC == CallerCC)
810 return true;
811
812 // Check if the caller and callee will handle arguments in the same way.
813 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
814 CCAssignFn *CalleeAssignFnFixed;
815 CCAssignFn *CalleeAssignFnVarArg;
816 std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
817 getAssignFnsForCC(CalleeCC, TLI);
818
819 CCAssignFn *CallerAssignFnFixed;
820 CCAssignFn *CallerAssignFnVarArg;
821 std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
822 getAssignFnsForCC(CallerCC, TLI);
823
824 AArch64IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
825 CalleeAssignFnVarArg);
826 AArch64IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
827 CallerAssignFnVarArg);
828
829 if (!resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner))
830 return false;
831
832 // Make sure that the caller and callee preserve all of the same registers.
833 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
834 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
835 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
837 TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
838 TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
839 }
840
841 return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
842}
843
844bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
845 CallLoweringInfo &Info, MachineFunction &MF,
846 SmallVectorImpl<ArgInfo> &OrigOutArgs) const {
847 // If there are no outgoing arguments, then we are done.
848 if (OrigOutArgs.empty())
849 return true;
850
851 const Function &CallerF = MF.getFunction();
852 LLVMContext &Ctx = CallerF.getContext();
853 CallingConv::ID CalleeCC = Info.CallConv;
854 CallingConv::ID CallerCC = CallerF.getCallingConv();
855 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
856 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
857
858 CCAssignFn *AssignFnFixed;
859 CCAssignFn *AssignFnVarArg;
860 std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
861
862 // We have outgoing arguments. Make sure that we can tail call with them.
864 CCState OutInfo(CalleeCC, false, MF, OutLocs, Ctx);
865
866 AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
867 Subtarget, /*IsReturn*/ false);
868 // determineAssignments() may modify argument flags, so make a copy.
870 append_range(OutArgs, OrigOutArgs);
871 if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo)) {
872 LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
873 return false;
874 }
875
876 // Make sure that they can fit on the caller's stack.
877 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
878 if (OutInfo.getStackSize() > FuncInfo->getBytesInStackArgArea()) {
879 LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
880 return false;
881 }
882
883 // Verify that the parameters in callee-saved registers match.
884 // TODO: Port this over to CallLowering as general code once swiftself is
885 // supported.
886 auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
887 const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
889
890 if (Info.IsVarArg) {
891 // Be conservative and disallow variadic memory operands to match SDAG's
892 // behaviour.
893 // FIXME: If the caller's calling convention is C, then we can
894 // potentially use its argument area. However, for cases like fastcc,
895 // we can't do anything.
896 for (unsigned i = 0; i < OutLocs.size(); ++i) {
897 auto &ArgLoc = OutLocs[i];
898 if (ArgLoc.isRegLoc())
899 continue;
900
902 dbgs()
903 << "... Cannot tail call vararg function with stack arguments\n");
904 return false;
905 }
906 }
907
908 return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
909}
910
912 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
914 SmallVectorImpl<ArgInfo> &OutArgs) const {
915
916 // Must pass all target-independent checks in order to tail call optimize.
917 if (!Info.IsTailCall)
918 return false;
919
920 CallingConv::ID CalleeCC = Info.CallConv;
921 MachineFunction &MF = MIRBuilder.getMF();
922 const Function &CallerF = MF.getFunction();
923
924 LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
925
926 if (Info.SwiftErrorVReg) {
927 // TODO: We should handle this.
928 // Note that this is also handled by the check for no outgoing arguments.
929 // Proactively disabling this though, because the swifterror handling in
930 // lowerCall inserts a COPY *after* the location of the call.
931 LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
932 return false;
933 }
934
935 if (!mayTailCallThisCC(CalleeCC)) {
936 LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
937 return false;
938 }
939
940 // Byval parameters hand the function a pointer directly into the stack area
941 // we want to reuse during a tail call. Working around this *is* possible (see
942 // X86).
943 //
944 // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
945 // it?
946 //
947 // On Windows, "inreg" attributes signify non-aggregate indirect returns.
948 // In this case, it is necessary to save/restore X0 in the callee. Tail
949 // call opt interferes with this. So we disable tail call opt when the
950 // caller has an argument with "inreg" attribute.
951 //
952 // FIXME: Check whether the callee also has an "inreg" argument.
953 //
954 // When the caller has a swifterror argument, we don't want to tail call
955 // because would have to move into the swifterror register before the
956 // tail call.
957 if (any_of(CallerF.args(), [](const Argument &A) {
958 return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
959 })) {
960 LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
961 "inreg, or swifterror arguments\n");
962 return false;
963 }
964
965 // Externally-defined functions with weak linkage should not be
966 // tail-called on AArch64 when the OS does not support dynamic
967 // pre-emption of symbols, as the AAELF spec requires normal calls
968 // to undefined weak functions to be replaced with a NOP or jump to the
969 // next instruction. The behaviour of branch instructions in this
970 // situation (as used for tail calls) is implementation-defined, so we
971 // cannot rely on the linker replacing the tail call with a return.
972 if (Info.Callee.isGlobal()) {
973 const GlobalValue *GV = Info.Callee.getGlobal();
974 const Triple &TT = MF.getTarget().getTargetTriple();
975 if (GV->hasExternalWeakLinkage() &&
976 (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
977 TT.isOSBinFormatMachO())) {
978 LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
979 "with weak linkage for this OS.\n");
980 return false;
981 }
982 }
983
984 // If we have -tailcallopt, then we're done.
986 return CalleeCC == CallerF.getCallingConv();
987
988 // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
989 // Try to find cases where we can do that.
990
991 // I want anyone implementing a new calling convention to think long and hard
992 // about this assert.
993 assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
994 "Unexpected variadic calling convention");
995
996 // Verify that the incoming and outgoing arguments from the callee are
997 // safe to tail call.
998 if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
1000 dbgs()
1001 << "... Caller and callee have incompatible calling conventions.\n");
1002 return false;
1003 }
1004
1005 if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
1006 return false;
1007
1008 LLVM_DEBUG(
1009 dbgs() << "... Call is eligible for tail call optimization.\n");
1010 return true;
1011}
1012
1013static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
1014 bool IsTailCall) {
1015 const AArch64FunctionInfo *FuncInfo = CallerF.getInfo<AArch64FunctionInfo>();
1016
1017 if (!IsTailCall)
1018 return IsIndirect ? getBLRCallOpcode(CallerF) : (unsigned)AArch64::BL;
1019
1020 if (!IsIndirect)
1021 return AArch64::TCRETURNdi;
1022
1023 // When BTI or PAuthLR are enabled, there are restrictions on using x16 and
1024 // x17 to hold the function pointer.
1025 if (FuncInfo->branchTargetEnforcement()) {
1026 if (FuncInfo->branchProtectionPAuthLR())
1027 return AArch64::TCRETURNrix17;
1028 else
1029 return AArch64::TCRETURNrix16x17;
1030 } else if (FuncInfo->branchProtectionPAuthLR())
1031 return AArch64::TCRETURNrinotx16;
1032
1033 return AArch64::TCRETURNri;
1034}
1035
1036static const uint32_t *
1040 const uint32_t *Mask;
1041 if (!OutArgs.empty() && OutArgs[0].Flags[0].isReturned()) {
1042 // For 'this' returns, use the X0-preserving mask if applicable
1043 Mask = TRI.getThisReturnPreservedMask(MF, Info.CallConv);
1044 if (!Mask) {
1045 OutArgs[0].Flags[0].setReturned(false);
1046 Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
1047 }
1048 } else {
1049 Mask = TRI.getCallPreservedMask(MF, Info.CallConv);
1050 }
1051 return Mask;
1052}
1053
1054bool AArch64CallLowering::lowerTailCall(
1055 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1056 SmallVectorImpl<ArgInfo> &OutArgs) const {
1057 MachineFunction &MF = MIRBuilder.getMF();
1058 const Function &F = MF.getFunction();
1060 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1062
1063 // True when we're tail calling, but without -tailcallopt.
1064 bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt &&
1065 Info.CallConv != CallingConv::Tail &&
1066 Info.CallConv != CallingConv::SwiftTail;
1067
1068 // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
1069 // register class. Until we can do that, we should fall back here.
1071 LLVM_DEBUG(
1072 dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
1073 return false;
1074 }
1075
1076 // Find out which ABI gets to decide where things go.
1077 CallingConv::ID CalleeCC = Info.CallConv;
1078 CCAssignFn *AssignFnFixed;
1079 CCAssignFn *AssignFnVarArg;
1080 std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1081
1082 MachineInstrBuilder CallSeqStart;
1083 if (!IsSibCall)
1084 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1085
1086 unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
1087 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1088 MIB.add(Info.Callee);
1089
1090 // Byte offset for the tail call. When we are sibcalling, this will always
1091 // be 0.
1092 MIB.addImm(0);
1093
1094 // Tell the call which registers are clobbered.
1095 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1096 auto TRI = Subtarget.getRegisterInfo();
1097 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
1098 if (Subtarget.hasCustomCallingConv())
1099 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1100 MIB.addRegMask(Mask);
1101
1102 if (Info.CFIType)
1103 MIB->setCFIType(MF, Info.CFIType->getZExtValue());
1104
1105 if (TRI->isAnyArgRegReserved(MF))
1106 TRI->emitReservedArgRegCallError(MF);
1107
1108 // FPDiff is the byte offset of the call's argument area from the callee's.
1109 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1110 // by this amount for a tail call. In a sibling call it must be 0 because the
1111 // caller will deallocate the entire stack and the callee still expects its
1112 // arguments to begin at SP+0.
1113 int FPDiff = 0;
1114
1115 // This will be 0 for sibcalls, potentially nonzero for tail calls produced
1116 // by -tailcallopt. For sibcalls, the memory operands for the call are
1117 // already available in the caller's incoming argument space.
1118 unsigned NumBytes = 0;
1119 if (!IsSibCall) {
1120 // We aren't sibcalling, so we need to compute FPDiff. We need to do this
1121 // before handling assignments, because FPDiff must be known for memory
1122 // arguments.
1123 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1125 CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
1126
1127 AArch64OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg,
1128 Subtarget, /*IsReturn*/ false);
1129 if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
1130 return false;
1131
1132 // The callee will pop the argument stack as a tail call. Thus, we must
1133 // keep it 16-byte aligned.
1134 NumBytes = alignTo(OutInfo.getStackSize(), 16);
1135
1136 // FPDiff will be negative if this tail call requires more space than we
1137 // would automatically have in our incoming argument space. Positive if we
1138 // actually shrink the stack.
1139 FPDiff = NumReusableBytes - NumBytes;
1140
1141 // Update the required reserved area if this is the tail call requiring the
1142 // most argument stack space.
1143 if (FPDiff < 0 && FuncInfo->getTailCallReservedStack() < (unsigned)-FPDiff)
1144 FuncInfo->setTailCallReservedStack(-FPDiff);
1145
1146 // The stack pointer must be 16-byte aligned at all times it's used for a
1147 // memory operation, which in practice means at *all* times and in
1148 // particular across call boundaries. Therefore our own arguments started at
1149 // a 16-byte aligned SP and the delta applied for the tail call should
1150 // satisfy the same constraint.
1151 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1152 }
1153
1154 const auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
1155
1156 AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1157 Subtarget, /*IsReturn*/ false);
1158
1159 // Do the actual argument marshalling.
1160 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB,
1161 /*IsTailCall*/ true, FPDiff);
1162 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1163 CalleeCC, Info.IsVarArg))
1164 return false;
1165
1166 Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1167
1168 if (Info.IsVarArg && Info.IsMustTailCall) {
1169 // Now we know what's being passed to the function. Add uses to the call for
1170 // the forwarded registers that we *aren't* passing as parameters. This will
1171 // preserve the copies we build earlier.
1172 for (const auto &F : Forwards) {
1173 Register ForwardedReg = F.PReg;
1174 // If the register is already passed, or aliases a register which is
1175 // already being passed, then skip it.
1176 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) {
1177 if (!Use.isReg())
1178 return false;
1179 return TRI->regsOverlap(Use.getReg(), ForwardedReg);
1180 }))
1181 continue;
1182
1183 // We aren't passing it already, so we should add it to the call.
1184 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg));
1185 MIB.addReg(ForwardedReg, RegState::Implicit);
1186 }
1187 }
1188
1189 // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1190 // sequence start and end here.
1191 if (!IsSibCall) {
1192 MIB->getOperand(1).setImm(FPDiff);
1193 CallSeqStart.addImm(0).addImm(0);
1194 // End the call sequence *before* emitting the call. Normally, we would
1195 // tidy the frame up after the call. However, here, we've laid out the
1196 // parameters so that when SP is reset, they will be in the correct
1197 // location.
1198 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(0).addImm(0);
1199 }
1200
1201 // Now we can add the actual call instruction to the correct basic block.
1202 MIRBuilder.insertInstr(MIB);
1203
1204 // If Callee is a reg, since it is used by a target specific instruction,
1205 // it must have a register class matching the constraint of that instruction.
1206 if (MIB->getOperand(0).isReg())
1208 *MF.getSubtarget().getRegBankInfo(), *MIB,
1209 MIB->getDesc(), MIB->getOperand(0), 0);
1210
1212 Info.LoweredTailCall = true;
1213 return true;
1214}
1215
1217 CallLoweringInfo &Info) const {
1218 MachineFunction &MF = MIRBuilder.getMF();
1219 const Function &F = MF.getFunction();
1221 auto &DL = F.getParent()->getDataLayout();
1222 const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
1223 const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
1224
1225 // Arm64EC has extra requirements for varargs calls; bail out for now.
1226 //
1227 // Arm64EC has special mangling rules for calls; bail out on all calls for
1228 // now.
1229 if (Subtarget.isWindowsArm64EC())
1230 return false;
1231
1232 // Arm64EC thunks have a special calling convention which is only implemented
1233 // in SelectionDAG; bail out for now.
1234 if (Info.CallConv == CallingConv::ARM64EC_Thunk_Native ||
1236 return false;
1237
1239 for (auto &OrigArg : Info.OrigArgs) {
1240 splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1241 // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
1242 auto &Flags = OrigArg.Flags[0];
1243 if (OrigArg.Ty->isIntegerTy(1) && !Flags.isSExt() && !Flags.isZExt()) {
1244 ArgInfo &OutArg = OutArgs.back();
1245 assert(OutArg.Regs.size() == 1 &&
1246 MRI.getType(OutArg.Regs[0]).getSizeInBits() == 1 &&
1247 "Unexpected registers used for i1 arg");
1248
1249 // We cannot use a ZExt ArgInfo flag here, because it will
1250 // zero-extend the argument to i32 instead of just i8.
1251 OutArg.Regs[0] =
1252 MIRBuilder.buildZExt(LLT::scalar(8), OutArg.Regs[0]).getReg(0);
1253 LLVMContext &Ctx = MF.getFunction().getContext();
1254 OutArg.Ty = Type::getInt8Ty(Ctx);
1255 }
1256 }
1257
1259 if (!Info.OrigRet.Ty->isVoidTy())
1260 splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1261
1262 // If we can lower as a tail call, do that instead.
1263 bool CanTailCallOpt =
1264 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1265
1266 // We must emit a tail call if we have musttail.
1267 if (Info.IsMustTailCall && !CanTailCallOpt) {
1268 // There are types of incoming/outgoing arguments we can't handle yet, so
1269 // it doesn't make sense to actually die here like in ISelLowering. Instead,
1270 // fall back to SelectionDAG and let it try to handle this.
1271 LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1272 return false;
1273 }
1274
1275 Info.IsTailCall = CanTailCallOpt;
1276 if (CanTailCallOpt)
1277 return lowerTailCall(MIRBuilder, Info, OutArgs);
1278
1279 // Find out which ABI gets to decide where things go.
1280 CCAssignFn *AssignFnFixed;
1281 CCAssignFn *AssignFnVarArg;
1282 std::tie(AssignFnFixed, AssignFnVarArg) =
1283 getAssignFnsForCC(Info.CallConv, TLI);
1284
1285 MachineInstrBuilder CallSeqStart;
1286 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
1287
1288 // Create a temporarily-floating call instruction so we can add the implicit
1289 // uses of arg registers.
1290
1291 unsigned Opc = 0;
1292 // Calls with operand bundle "clang.arc.attachedcall" are special. They should
1293 // be expanded to the call, directly followed by a special marker sequence and
1294 // a call to an ObjC library function.
1296 Opc = AArch64::BLR_RVMARKER;
1297 // A call to a returns twice function like setjmp must be followed by a bti
1298 // instruction.
1299 else if (Info.CB && Info.CB->hasFnAttr(Attribute::ReturnsTwice) &&
1300 !Subtarget.noBTIAtReturnTwice() &&
1302 Opc = AArch64::BLR_BTI;
1303 else
1304 Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1305
1306 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1307 unsigned CalleeOpNo = 0;
1308
1309 if (Opc == AArch64::BLR_RVMARKER) {
1310 // Add a target global address for the retainRV/claimRV runtime function
1311 // just before the call target.
1313 MIB.addGlobalAddress(ARCFn);
1314 ++CalleeOpNo;
1315 } else if (Info.CFIType) {
1316 MIB->setCFIType(MF, Info.CFIType->getZExtValue());
1317 }
1318
1319 MIB.add(Info.Callee);
1320
1321 // Tell the call which registers are clobbered.
1322 const uint32_t *Mask;
1323 const auto *TRI = Subtarget.getRegisterInfo();
1324
1325 AArch64OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg,
1326 Subtarget, /*IsReturn*/ false);
1327 // Do the actual argument marshalling.
1328 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, /*IsReturn*/ false);
1329 if (!determineAndHandleAssignments(Handler, Assigner, OutArgs, MIRBuilder,
1330 Info.CallConv, Info.IsVarArg))
1331 return false;
1332
1333 Mask = getMaskForArgs(OutArgs, Info, *TRI, MF);
1334
1336 TRI->UpdateCustomCallPreservedMask(MF, &Mask);
1337 MIB.addRegMask(Mask);
1338
1339 if (TRI->isAnyArgRegReserved(MF))
1340 TRI->emitReservedArgRegCallError(MF);
1341
1342 // Now we can add the actual call instruction to the correct basic block.
1343 MIRBuilder.insertInstr(MIB);
1344
1345 uint64_t CalleePopBytes =
1348 ? alignTo(Assigner.StackSize, 16)
1349 : 0;
1350
1351 CallSeqStart.addImm(Assigner.StackSize).addImm(0);
1352 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
1353 .addImm(Assigner.StackSize)
1354 .addImm(CalleePopBytes);
1355
1356 // If Callee is a reg, since it is used by a target specific
1357 // instruction, it must have a register class matching the
1358 // constraint of that instruction.
1359 if (MIB->getOperand(CalleeOpNo).isReg())
1360 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(),
1361 *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(),
1362 MIB->getOperand(CalleeOpNo), CalleeOpNo);
1363
1364 // Finally we can copy the returned value back into its virtual-register. In
1365 // symmetry with the arguments, the physical register must be an
1366 // implicit-define of the call instruction.
1367 if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
1368 CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv);
1369 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1370 bool UsingReturnedArg =
1371 !OutArgs.empty() && OutArgs[0].Flags[0].isReturned();
1372
1373 AArch64OutgoingValueAssigner Assigner(RetAssignFn, RetAssignFn, Subtarget,
1374 /*IsReturn*/ false);
1375 ReturnedArgCallReturnHandler ReturnedArgHandler(MIRBuilder, MRI, MIB);
1377 UsingReturnedArg ? ReturnedArgHandler : Handler, Assigner, InArgs,
1378 MIRBuilder, Info.CallConv, Info.IsVarArg,
1379 UsingReturnedArg ? ArrayRef(OutArgs[0].Regs) : std::nullopt))
1380 return false;
1381 }
1382
1383 if (Info.SwiftErrorVReg) {
1384 MIB.addDef(AArch64::X21, RegState::Implicit);
1385 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
1386 }
1387
1388 if (!Info.CanLowerReturn) {
1389 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
1390 Info.DemoteRegister, Info.DemoteStackIndex);
1391 }
1392 return true;
1393}
1394
1396 return Ty.getSizeInBits() == 64;
1397}
unsigned const MachineRegisterInfo * MRI
static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, CCAssignFn *AssignFn)
Helper function to compute forwarded registers for musttail calls.
static LLT getStackValueStoreTypeHack(const CCValAssign &VA)
static const uint32_t * getMaskForArgs(SmallVectorImpl< AArch64CallLowering::ArgInfo > &OutArgs, AArch64CallLowering::CallLoweringInfo &Info, const AArch64RegisterInfo &TRI, MachineFunction &MF)
static void applyStackPassedSmallTypeDAGHack(EVT OrigVT, MVT &ValVT, MVT &LocVT)
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const AArch64TargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
This file describes how to lower LLVM calls to machine code calls.
#define Success
static const MCPhysReg GPRArgRegs[]
static const MCPhysReg FPRArgRegs[]
static bool canGuaranteeTCO(CallingConv::ID CC, bool GuaranteeTailCalls)
Return true if the calling convention is one that we can guarantee TCO for.
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Addr
uint64_t Size
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
This file declares the MachineIRBuilder class.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
This file defines ARC utility functions which are used by various parts of the compiler.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const override
This hook must be implemented to check whether the return values described by Outs can fit into the r...
bool fallBackToDAGISel(const MachineFunction &MF) const override
bool isTypeIsValidForThisReturn(EVT Ty) const override
For targets which support the "returned" parameter attribute, returns true if the given type is a val...
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
AArch64CallLowering(const AArch64TargetLowering &TLI)
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
void setTailCallReservedStack(unsigned bytes)
SmallVectorImpl< ForwardedRegister > & getForwardedMustTailRegParms()
void setBytesInStackArgArea(unsigned bytes)
void setArgumentStackToRestore(unsigned bytes)
const AArch64RegisterInfo * getRegisterInfo() const override
const AArch64InstrInfo * getInstrInfo() const override
bool isCallingConvWin64(CallingConv::ID CC) const
const RegisterBankInfo * getRegBankInfo() const override
bool hasCustomCallingConv() const
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain targets require unusual breakdowns of certain types.
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
CCState - This class holds information needed while lowering arguments and return values.
unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const
getFirstUnallocated - Return the index of the first unallocated register in the set,...
void analyzeMustTailForwardedRegisters(SmallVectorImpl< ForwardedRegister > &Forwards, ArrayRef< MVT > RegParmTypes, CCAssignFn Fn)
Compute the set of registers that need to be preserved and forwarded to any musttail calls.
CallingConv::ID getCallingConv() const
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
bool isVarArg() const
bool isAllocated(MCRegister Reg) const
isAllocated - Return true if the specified register (or an alias) is allocated.
CCValAssign - Represent assignment of one arg/retval to a location.
LocInfo getLocInfo() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP, bool IsCustom=false)
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Use Handler to insert code to handle the argument/return values represented by Args.
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=std::nullopt) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
iterator_range< arg_iterator > args()
Definition: Function.h:834
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:262
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:342
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:528
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelType.h:42
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
Definition: LowLevelType.h:151
constexpr bool isVector() const
Definition: LowLevelType.h:147
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelType.h:49
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Definition: LowLevelType.h:185
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
Definition: LowLevelType.h:195
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Machine Value Type.
bool isVector() const
Return true if this is a vector value type.
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:583
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasTailCall(bool V=true)
bool hasMustTailInVarArgFunc() const
Returns true if the function is variadic and contains a musttail call.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Helper class to build MachineInstr.
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
MachineInstrBuilder buildAssertZExt(const DstOp &Res, const SrcOp &Op, unsigned Size)
Build and insert Res = G_ASSERT_ZEXT Op, Size.
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_PTR_ADD Op0, Op1.
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)
Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
MachineFunction & getMF()
Getter for the function we currently build.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:553
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SMEAttrs is a utility class to parse the SME ACLE attributes on functions.
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
const Triple & getTargetTriple() const
TargetOptions Options
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
static IntegerType * getInt8Ty(LLVMContext &C)
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned getNumOperands() const
Definition: User.h:191
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
ArrayRef< MCPhysReg > getFPRArgRegs()
ArrayRef< MCPhysReg > getGPRArgRegs()
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ ARM64EC_Thunk_Native
Calling convention used in the ARM64EC ABI to implement calls between ARM64 code and thunks.
Definition: CallingConv.h:265
@ Swift
Calling convention for Swift.
Definition: CallingConv.h:69
@ PreserveMost
Used for runtime calls that preserves most registers.
Definition: CallingConv.h:63
@ PreserveAll
Used for runtime calls that preserves (almost) all registers.
Definition: CallingConv.h:66
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ SwiftTail
This follows the Swift calling convention in how arguments are passed but guarantees tail calls will ...
Definition: CallingConv.h:87
@ ARM64EC_Thunk_X64
Calling convention used in the ARM64EC ABI to implement calls between x64 code and thunks.
Definition: CallingConv.h:260
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ Implicit
Not emitted register (e.g. carry, or temporary result).
std::optional< Function * > getAttachedARCFunction(const CallBase *CB)
This function returns operand bundle clang_arc_attachedcall's argument, which is the address of the A...
Definition: ObjCARCUtil.h:43
bool hasAttachedCallOpBundle(const CallBase *CB)
Definition: ObjCARCUtil.h:29
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Definition: STLExtras.h:2053
unsigned getBLRCallOpcode(const MachineFunction &MF)
Return opcode to be used for indirect calls.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:866
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:860
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:63
SmallVector< ISD::ArgFlagsTy, 4 > Flags
Definition: CallLowering.h:51
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:320
void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override
Provides a default implementation for argument handling.
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:336
MachineRegisterInfo & MRI
Definition: CallLowering.h:233
virtual LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Return the in-memory size to write for the argument at VA.
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
Describes a register that needs to be forwarded from the prologue to a musttail call.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.