LLVM  10.0.0svn
AArch64CallLowering.cpp
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1 //===--- AArch64CallLowering.cpp - Call lowering --------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AArch64CallLowering.h"
16 #include "AArch64ISelLowering.h"
18 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Argument.h"
37 #include "llvm/IR/Attributes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/IR/Value.h"
42 #include <algorithm>
43 #include <cassert>
44 #include <cstdint>
45 #include <iterator>
46 
47 #define DEBUG_TYPE "aarch64-call-lowering"
48 
49 using namespace llvm;
50 
52  : CallLowering(&TLI) {}
53 
54 namespace {
55 struct IncomingArgHandler : public CallLowering::ValueHandler {
56  IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
57  CCAssignFn *AssignFn)
58  : ValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {}
59 
60  Register getStackAddress(uint64_t Size, int64_t Offset,
61  MachinePointerInfo &MPO) override {
62  auto &MFI = MIRBuilder.getMF().getFrameInfo();
63  int FI = MFI.CreateFixedObject(Size, Offset, true);
64  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
66  MIRBuilder.buildFrameIndex(AddrReg, FI);
67  StackUsed = std::max(StackUsed, Size + Offset);
68  return AddrReg;
69  }
70 
71  void assignValueToReg(Register ValVReg, Register PhysReg,
72  CCValAssign &VA) override {
73  markPhysRegUsed(PhysReg);
74  switch (VA.getLocInfo()) {
75  default:
76  MIRBuilder.buildCopy(ValVReg, PhysReg);
77  break;
78  case CCValAssign::LocInfo::SExt:
79  case CCValAssign::LocInfo::ZExt:
80  case CCValAssign::LocInfo::AExt: {
81  auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
82  MIRBuilder.buildTrunc(ValVReg, Copy);
83  break;
84  }
85  }
86  }
87 
88  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
89  MachinePointerInfo &MPO, CCValAssign &VA) override {
90  // FIXME: Get alignment
91  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
93  1);
94  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
95  }
96 
97  /// How the physical register gets marked varies between formal
98  /// parameters (it's a basic-block live-in), and a call instruction
99  /// (it's an implicit-def of the BL).
100  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
101 
102  bool isIncomingArgumentHandler() const override { return true; }
103 
104  uint64_t StackUsed;
105 };
106 
107 struct FormalArgHandler : public IncomingArgHandler {
108  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
109  CCAssignFn *AssignFn)
110  : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
111 
112  void markPhysRegUsed(unsigned PhysReg) override {
113  MIRBuilder.getMRI()->addLiveIn(PhysReg);
114  MIRBuilder.getMBB().addLiveIn(PhysReg);
115  }
116 };
117 
118 struct CallReturnHandler : public IncomingArgHandler {
119  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
120  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
121  : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
122 
123  void markPhysRegUsed(unsigned PhysReg) override {
124  MIB.addDef(PhysReg, RegState::Implicit);
125  }
126 
128 };
129 
130 struct OutgoingArgHandler : public CallLowering::ValueHandler {
131  OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
132  MachineInstrBuilder MIB, CCAssignFn *AssignFn,
133  CCAssignFn *AssignFnVarArg, bool IsTailCall = false,
134  int FPDiff = 0)
135  : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
136  AssignFnVarArg(AssignFnVarArg), IsTailCall(IsTailCall), FPDiff(FPDiff),
137  StackSize(0) {}
138 
139  Register getStackAddress(uint64_t Size, int64_t Offset,
140  MachinePointerInfo &MPO) override {
141  MachineFunction &MF = MIRBuilder.getMF();
142  LLT p0 = LLT::pointer(0, 64);
143  LLT s64 = LLT::scalar(64);
144 
145  if (IsTailCall) {
146  Offset += FPDiff;
147  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
148  Register FIReg = MRI.createGenericVirtualRegister(p0);
149  MIRBuilder.buildFrameIndex(FIReg, FI);
150  MPO = MachinePointerInfo::getFixedStack(MF, FI);
151  return FIReg;
152  }
153 
154  Register SPReg = MRI.createGenericVirtualRegister(p0);
155  MIRBuilder.buildCopy(SPReg, Register(AArch64::SP));
156 
157  Register OffsetReg = MRI.createGenericVirtualRegister(s64);
158  MIRBuilder.buildConstant(OffsetReg, Offset);
159 
160  Register AddrReg = MRI.createGenericVirtualRegister(p0);
161  MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
162 
163  MPO = MachinePointerInfo::getStack(MF, Offset);
164  return AddrReg;
165  }
166 
167  void assignValueToReg(Register ValVReg, Register PhysReg,
168  CCValAssign &VA) override {
169  MIB.addUse(PhysReg, RegState::Implicit);
170  Register ExtReg = extendRegister(ValVReg, VA);
171  MIRBuilder.buildCopy(PhysReg, ExtReg);
172  }
173 
174  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
175  MachinePointerInfo &MPO, CCValAssign &VA) override {
176  if (VA.getLocInfo() == CCValAssign::LocInfo::AExt) {
177  Size = VA.getLocVT().getSizeInBits() / 8;
178  ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg)
179  ->getOperand(0)
180  .getReg();
181  }
182  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
183  MPO, MachineMemOperand::MOStore, Size, 1);
184  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
185  }
186 
187  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
188  CCValAssign::LocInfo LocInfo,
190  ISD::ArgFlagsTy Flags,
191  CCState &State) override {
192  bool Res;
193  if (Info.IsFixed)
194  Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
195  else
196  Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
197 
198  StackSize = State.getNextStackOffset();
199  return Res;
200  }
201 
203  CCAssignFn *AssignFnVarArg;
204  bool IsTailCall;
205 
206  /// For tail calls, the byte offset of the call's argument area from the
207  /// callee's. Unused elsewhere.
208  int FPDiff;
209  uint64_t StackSize;
210 };
211 } // namespace
212 
213 static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt) {
214  return CallConv == CallingConv::Fast && TailCallOpt;
215 }
216 
217 void AArch64CallLowering::splitToValueTypes(
218  const ArgInfo &OrigArg, SmallVectorImpl<ArgInfo> &SplitArgs,
219  const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv) const {
220  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
221  LLVMContext &Ctx = OrigArg.Ty->getContext();
222 
223  if (OrigArg.Ty->isVoidTy())
224  return;
225 
226  SmallVector<EVT, 4> SplitVTs;
228  ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
229 
230  if (SplitVTs.size() == 1) {
231  // No splitting to do, but we want to replace the original type (e.g. [1 x
232  // double] -> double).
233  SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
234  OrigArg.Flags[0], OrigArg.IsFixed);
235  return;
236  }
237 
238  // Create one ArgInfo for each virtual register in the original ArgInfo.
239  assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
240 
241  bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
242  OrigArg.Ty, CallConv, false);
243  for (unsigned i = 0, e = SplitVTs.size(); i < e; ++i) {
244  Type *SplitTy = SplitVTs[i].getTypeForEVT(Ctx);
245  SplitArgs.emplace_back(OrigArg.Regs[i], SplitTy, OrigArg.Flags[0],
246  OrigArg.IsFixed);
247  if (NeedsRegBlock)
248  SplitArgs.back().Flags[0].setInConsecutiveRegs();
249  }
250 
251  SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
252 }
253 
255  const Value *Val,
256  ArrayRef<Register> VRegs,
257  Register SwiftErrorVReg) const {
258  auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
259  assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
260  "Return value without a vreg");
261 
262  bool Success = true;
263  if (!VRegs.empty()) {
264  MachineFunction &MF = MIRBuilder.getMF();
265  const Function &F = MF.getFunction();
266 
267  MachineRegisterInfo &MRI = MF.getRegInfo();
268  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
269  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
270  auto &DL = F.getParent()->getDataLayout();
271  LLVMContext &Ctx = Val->getType()->getContext();
272 
273  SmallVector<EVT, 4> SplitEVTs;
274  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
275  assert(VRegs.size() == SplitEVTs.size() &&
276  "For each split Type there should be exactly one VReg.");
277 
278  SmallVector<ArgInfo, 8> SplitArgs;
280 
281  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
282  if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
283  LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
284  return false;
285  }
286 
287  Register CurVReg = VRegs[i];
288  ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
289  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
290 
291  // i1 is a special case because SDAG i1 true is naturally zero extended
292  // when widened using ANYEXT. We need to do it explicitly here.
293  if (MRI.getType(CurVReg).getSizeInBits() == 1) {
294  CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
295  } else {
296  // Some types will need extending as specified by the CC.
297  MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
298  if (EVT(NewVT) != SplitEVTs[i]) {
299  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
301  Attribute::SExt))
302  ExtendOp = TargetOpcode::G_SEXT;
304  Attribute::ZExt))
305  ExtendOp = TargetOpcode::G_ZEXT;
306 
307  LLT NewLLT(NewVT);
308  LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
309  CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
310  // Instead of an extend, we might have a vector type which needs
311  // padding with more elements, e.g. <2 x half> -> <4 x half>.
312  if (NewVT.isVector()) {
313  if (OldLLT.isVector()) {
314  if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
315  // We don't handle VA types which are not exactly twice the
316  // size, but can easily be done in future.
317  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
318  LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
319  return false;
320  }
321  auto Undef = MIRBuilder.buildUndef({OldLLT});
322  CurVReg =
323  MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)})
324  .getReg(0);
325  } else {
326  // Just do a vector extend.
327  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
328  .getReg(0);
329  }
330  } else if (NewLLT.getNumElements() == 2) {
331  // We need to pad a <1 x S> type to <2 x S>. Since we don't have
332  // <1 x S> vector types in GISel we use a build_vector instead
333  // of a vector merge/concat.
334  auto Undef = MIRBuilder.buildUndef({OldLLT});
335  CurVReg =
336  MIRBuilder
337  .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
338  .getReg(0);
339  } else {
340  LLVM_DEBUG(dbgs() << "Could not handle ret ty");
341  return false;
342  }
343  } else {
344  // A scalar extend.
345  CurVReg =
346  MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0);
347  }
348  }
349  }
350  if (CurVReg != CurArgInfo.Regs[0]) {
351  CurArgInfo.Regs[0] = CurVReg;
352  // Reset the arg flags after modifying CurVReg.
353  setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
354  }
355  splitToValueTypes(CurArgInfo, SplitArgs, DL, MRI, CC);
356  }
357 
358  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn);
359  Success = handleAssignments(MIRBuilder, SplitArgs, Handler);
360  }
361 
362  if (SwiftErrorVReg) {
363  MIB.addUse(AArch64::X21, RegState::Implicit);
364  MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
365  }
366 
367  MIRBuilder.insertInstr(MIB);
368  return Success;
369 }
370 
372  MachineIRBuilder &MIRBuilder, const Function &F,
373  ArrayRef<ArrayRef<Register>> VRegs) const {
374  MachineFunction &MF = MIRBuilder.getMF();
375  MachineBasicBlock &MBB = MIRBuilder.getMBB();
376  MachineRegisterInfo &MRI = MF.getRegInfo();
377  auto &DL = F.getParent()->getDataLayout();
378 
379  SmallVector<ArgInfo, 8> SplitArgs;
380  unsigned i = 0;
381  for (auto &Arg : F.args()) {
382  if (DL.getTypeStoreSize(Arg.getType()) == 0)
383  continue;
384 
385  ArgInfo OrigArg{VRegs[i], Arg.getType()};
386  setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
387 
388  splitToValueTypes(OrigArg, SplitArgs, DL, MRI, F.getCallingConv());
389  ++i;
390  }
391 
392  if (!MBB.empty())
393  MIRBuilder.setInstr(*MBB.begin());
394 
395  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
396  CCAssignFn *AssignFn =
397  TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
398 
399  FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
400  if (!handleAssignments(MIRBuilder, SplitArgs, Handler))
401  return false;
402 
404  uint64_t StackOffset = Handler.StackUsed;
405  if (F.isVarArg()) {
406  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
407  if (!Subtarget.isTargetDarwin()) {
408  // FIXME: we need to reimplement saveVarArgsRegisters from
409  // AArch64ISelLowering.
410  return false;
411  }
412 
413  // We currently pass all varargs at 8-byte alignment, or 4 in ILP32.
414  StackOffset = alignTo(Handler.StackUsed, Subtarget.isTargetILP32() ? 4 : 8);
415 
416  auto &MFI = MIRBuilder.getMF().getFrameInfo();
417  FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
418  }
419 
422  // We have a non-standard ABI, so why not make full use of the stack that
423  // we're going to pop? It must be aligned to 16 B in any case.
424  StackOffset = alignTo(StackOffset, 16);
425 
426  // If we're expected to restore the stack (e.g. fastcc), then we'll be
427  // adding a multiple of 16.
428  FuncInfo->setArgumentStackToRestore(StackOffset);
429 
430  // Our own callers will guarantee that the space is free by giving an
431  // aligned value to CALLSEQ_START.
432  }
433 
434  // When we tail call, we need to check if the callee's arguments
435  // will fit on the caller's stack. So, whenever we lower formal arguments,
436  // we should keep track of this information, since we might lower a tail call
437  // in this function later.
438  FuncInfo->setBytesInStackArgArea(StackOffset);
439 
440  auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
441  if (Subtarget.hasCustomCallingConv())
443 
444  // Move back to the end of the basic block.
445  MIRBuilder.setMBB(MBB);
446 
447  return true;
448 }
449 
450 /// Return true if the calling convention is one that we can guarantee TCO for.
452  return CC == CallingConv::Fast;
453 }
454 
455 /// Return true if we might ever do TCO for calls with this calling convention.
457  switch (CC) {
458  case CallingConv::C:
460  case CallingConv::Swift:
461  return true;
462  default:
463  return canGuaranteeTCO(CC);
464  }
465 }
466 
467 bool AArch64CallLowering::doCallerAndCalleePassArgsTheSameWay(
468  CallLoweringInfo &Info, MachineFunction &MF,
469  SmallVectorImpl<ArgInfo> &InArgs) const {
470  const Function &CallerF = MF.getFunction();
471  CallingConv::ID CalleeCC = Info.CallConv;
472  CallingConv::ID CallerCC = CallerF.getCallingConv();
473 
474  // If the calling conventions match, then everything must be the same.
475  if (CalleeCC == CallerCC)
476  return true;
477 
478  // Check if the caller and callee will handle arguments in the same way.
479  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
480  CCAssignFn *CalleeAssignFn = TLI.CCAssignFnForCall(CalleeCC, Info.IsVarArg);
481  CCAssignFn *CallerAssignFn =
482  TLI.CCAssignFnForCall(CallerCC, CallerF.isVarArg());
483 
484  if (!resultsCompatible(Info, MF, InArgs, *CalleeAssignFn, *CallerAssignFn))
485  return false;
486 
487  // Make sure that the caller and callee preserve all of the same registers.
488  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
489  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
490  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
492  TRI->UpdateCustomCallPreservedMask(MF, &CallerPreserved);
493  TRI->UpdateCustomCallPreservedMask(MF, &CalleePreserved);
494  }
495 
496  return TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved);
497 }
498 
499 bool AArch64CallLowering::areCalleeOutgoingArgsTailCallable(
500  CallLoweringInfo &Info, MachineFunction &MF,
501  SmallVectorImpl<ArgInfo> &OutArgs) const {
502  // If there are no outgoing arguments, then we are done.
503  if (OutArgs.empty())
504  return true;
505 
506  const Function &CallerF = MF.getFunction();
507  CallingConv::ID CalleeCC = Info.CallConv;
508  CallingConv::ID CallerCC = CallerF.getCallingConv();
509  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
510 
511  // We have outgoing arguments. Make sure that we can tail call with them.
513  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
514 
515  if (!analyzeArgInfo(OutInfo, OutArgs,
516  *TLI.CCAssignFnForCall(CalleeCC, Info.IsVarArg))) {
517  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
518  return false;
519  }
520 
521  // Make sure that they can fit on the caller's stack.
522  const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
523  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
524  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
525  return false;
526  }
527 
528  // Verify that the parameters in callee-saved registers match.
529  // TODO: Port this over to CallLowering as general code once swiftself is
530  // supported.
531  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
532  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
533  MachineRegisterInfo &MRI = MF.getRegInfo();
534 
535  for (unsigned i = 0; i < OutLocs.size(); ++i) {
536  auto &ArgLoc = OutLocs[i];
537  // If it's not a register, it's fine.
538  if (!ArgLoc.isRegLoc()) {
539  if (Info.IsVarArg) {
540  // Be conservative and disallow variadic memory operands to match SDAG's
541  // behaviour.
542  // FIXME: If the caller's calling convention is C, then we can
543  // potentially use its argument area. However, for cases like fastcc,
544  // we can't do anything.
545  LLVM_DEBUG(
546  dbgs()
547  << "... Cannot tail call vararg function with stack arguments\n");
548  return false;
549  }
550  continue;
551  }
552 
553  Register Reg = ArgLoc.getLocReg();
554 
555  // Only look at callee-saved registers.
556  if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
557  continue;
558 
559  LLVM_DEBUG(
560  dbgs()
561  << "... Call has an argument passed in a callee-saved register.\n");
562 
563  // Check if it was copied from.
564  ArgInfo &OutInfo = OutArgs[i];
565 
566  if (OutInfo.Regs.size() > 1) {
567  LLVM_DEBUG(
568  dbgs() << "... Cannot handle arguments in multiple registers.\n");
569  return false;
570  }
571 
572  // Check if we copy the register, walking through copies from virtual
573  // registers. Note that getDefIgnoringCopies does not ignore copies from
574  // physical registers.
575  MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI);
576  if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
577  LLVM_DEBUG(
578  dbgs()
579  << "... Parameter was not copied into a VReg, cannot tail call.\n");
580  return false;
581  }
582 
583  // Got a copy. Verify that it's the same as the register we want.
584  Register CopyRHS = RegDef->getOperand(1).getReg();
585  if (CopyRHS != Reg) {
586  LLVM_DEBUG(dbgs() << "... Callee-saved register was not copied into "
587  "VReg, cannot tail call.\n");
588  return false;
589  }
590  }
591 
592  return true;
593 }
594 
596  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
597  SmallVectorImpl<ArgInfo> &InArgs,
598  SmallVectorImpl<ArgInfo> &OutArgs) const {
599  CallingConv::ID CalleeCC = Info.CallConv;
600  MachineFunction &MF = MIRBuilder.getMF();
601  const Function &CallerF = MF.getFunction();
602 
603  LLVM_DEBUG(dbgs() << "Attempting to lower call as tail call\n");
604 
605  if (Info.SwiftErrorVReg) {
606  // TODO: We should handle this.
607  // Note that this is also handled by the check for no outgoing arguments.
608  // Proactively disabling this though, because the swifterror handling in
609  // lowerCall inserts a COPY *after* the location of the call.
610  LLVM_DEBUG(dbgs() << "... Cannot handle tail calls with swifterror yet.\n");
611  return false;
612  }
613 
614  if (!mayTailCallThisCC(CalleeCC)) {
615  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
616  return false;
617  }
618 
619  // Byval parameters hand the function a pointer directly into the stack area
620  // we want to reuse during a tail call. Working around this *is* possible (see
621  // X86).
622  //
623  // FIXME: In AArch64ISelLowering, this isn't worked around. Can/should we try
624  // it?
625  //
626  // On Windows, "inreg" attributes signify non-aggregate indirect returns.
627  // In this case, it is necessary to save/restore X0 in the callee. Tail
628  // call opt interferes with this. So we disable tail call opt when the
629  // caller has an argument with "inreg" attribute.
630  //
631  // FIXME: Check whether the callee also has an "inreg" argument.
632  //
633  // When the caller has a swifterror argument, we don't want to tail call
634  // because would have to move into the swifterror register before the
635  // tail call.
636  if (any_of(CallerF.args(), [](const Argument &A) {
637  return A.hasByValAttr() || A.hasInRegAttr() || A.hasSwiftErrorAttr();
638  })) {
639  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval, "
640  "inreg, or swifterror arguments\n");
641  return false;
642  }
643 
644  // Externally-defined functions with weak linkage should not be
645  // tail-called on AArch64 when the OS does not support dynamic
646  // pre-emption of symbols, as the AAELF spec requires normal calls
647  // to undefined weak functions to be replaced with a NOP or jump to the
648  // next instruction. The behaviour of branch instructions in this
649  // situation (as used for tail calls) is implementation-defined, so we
650  // cannot rely on the linker replacing the tail call with a return.
651  if (Info.Callee.isGlobal()) {
652  const GlobalValue *GV = Info.Callee.getGlobal();
653  const Triple &TT = MF.getTarget().getTargetTriple();
654  if (GV->hasExternalWeakLinkage() &&
655  (!TT.isOSWindows() || TT.isOSBinFormatELF() ||
656  TT.isOSBinFormatMachO())) {
657  LLVM_DEBUG(dbgs() << "... Cannot tail call externally-defined function "
658  "with weak linkage for this OS.\n");
659  return false;
660  }
661  }
662 
663  // If we have -tailcallopt, then we're done.
665  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
666 
667  // We don't have -tailcallopt, so we're allowed to change the ABI (sibcall).
668  // Try to find cases where we can do that.
669 
670  // I want anyone implementing a new calling convention to think long and hard
671  // about this assert.
672  assert((!Info.IsVarArg || CalleeCC == CallingConv::C) &&
673  "Unexpected variadic calling convention");
674 
675  // Before we can musttail varargs, we need to forward parameters like in
676  // r345641. Make sure that we don't enable musttail with varargs without
677  // addressing that!
678  assert(!(Info.IsVarArg && Info.IsMustTailCall) &&
679  "musttail support for varargs not implemented yet!");
680 
681  // Verify that the incoming and outgoing arguments from the callee are
682  // safe to tail call.
683  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
684  LLVM_DEBUG(
685  dbgs()
686  << "... Caller and callee have incompatible calling conventions.\n");
687  return false;
688  }
689 
690  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
691  return false;
692 
693  LLVM_DEBUG(
694  dbgs() << "... Call is eligible for tail call optimization.\n");
695  return true;
696 }
697 
698 static unsigned getCallOpcode(const Function &CallerF, bool IsIndirect,
699  bool IsTailCall) {
700  if (!IsTailCall)
701  return IsIndirect ? AArch64::BLR : AArch64::BL;
702 
703  if (!IsIndirect)
704  return AArch64::TCRETURNdi;
705 
706  // When BTI is enabled, we need to use TCRETURNriBTI to make sure that we use
707  // x16 or x17.
708  if (CallerF.hasFnAttribute("branch-target-enforcement"))
709  return AArch64::TCRETURNriBTI;
710 
711  return AArch64::TCRETURNri;
712 }
713 
714 bool AArch64CallLowering::lowerTailCall(
715  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
716  SmallVectorImpl<ArgInfo> &OutArgs) const {
717  MachineFunction &MF = MIRBuilder.getMF();
718  const Function &F = MF.getFunction();
719  MachineRegisterInfo &MRI = MF.getRegInfo();
720  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
721 
722  // True when we're tail calling, but without -tailcallopt.
723  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
724 
725  // TODO: Right now, regbankselect doesn't know how to handle the rtcGPR64
726  // register class. Until we can do that, we should fall back here.
727  if (F.hasFnAttribute("branch-target-enforcement")) {
728  LLVM_DEBUG(
729  dbgs() << "Cannot lower indirect tail calls with BTI enabled yet.\n");
730  return false;
731  }
732 
733  // Find out which ABI gets to decide where things go.
734  CallingConv::ID CalleeCC = Info.CallConv;
735  CCAssignFn *AssignFnFixed =
736  TLI.CCAssignFnForCall(CalleeCC, /*IsVarArg=*/false);
737  CCAssignFn *AssignFnVarArg =
738  TLI.CCAssignFnForCall(CalleeCC, /*IsVarArg=*/true);
739 
740  MachineInstrBuilder CallSeqStart;
741  if (!IsSibCall)
742  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
743 
744  unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), true);
745  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
746  MIB.add(Info.Callee);
747 
748  // Byte offset for the tail call. When we are sibcalling, this will always
749  // be 0.
750  MIB.addImm(0);
751 
752  // Tell the call which registers are clobbered.
753  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
754  const uint32_t *Mask = TRI->getCallPreservedMask(MF, F.getCallingConv());
756  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
757  MIB.addRegMask(Mask);
758 
759  if (TRI->isAnyArgRegReserved(MF))
760  TRI->emitReservedArgRegCallError(MF);
761 
762  // FPDiff is the byte offset of the call's argument area from the callee's.
763  // Stores to callee stack arguments will be placed in FixedStackSlots offset
764  // by this amount for a tail call. In a sibling call it must be 0 because the
765  // caller will deallocate the entire stack and the callee still expects its
766  // arguments to begin at SP+0.
767  int FPDiff = 0;
768 
769  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
770  // by -tailcallopt. For sibcalls, the memory operands for the call are
771  // already available in the caller's incoming argument space.
772  unsigned NumBytes = 0;
773  if (!IsSibCall) {
774  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
775  // before handling assignments, because FPDiff must be known for memory
776  // arguments.
778  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
780  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
781  analyzeArgInfo(OutInfo, OutArgs,
782  *TLI.CCAssignFnForCall(CalleeCC, Info.IsVarArg));
783 
784  // The callee will pop the argument stack as a tail call. Thus, we must
785  // keep it 16-byte aligned.
786  NumBytes = alignTo(OutInfo.getNextStackOffset(), 16);
787 
788  // FPDiff will be negative if this tail call requires more space than we
789  // would automatically have in our incoming argument space. Positive if we
790  // actually shrink the stack.
791  FPDiff = NumReusableBytes - NumBytes;
792 
793  // The stack pointer must be 16-byte aligned at all times it's used for a
794  // memory operation, which in practice means at *all* times and in
795  // particular across call boundaries. Therefore our own arguments started at
796  // a 16-byte aligned SP and the delta applied for the tail call should
797  // satisfy the same constraint.
798  assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
799  }
800 
801  // Do the actual argument marshalling.
802  SmallVector<unsigned, 8> PhysRegs;
803  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
804  AssignFnVarArg, true, FPDiff);
805  if (!handleAssignments(MIRBuilder, OutArgs, Handler))
806  return false;
807 
808  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
809  // sequence start and end here.
810  if (!IsSibCall) {
811  MIB->getOperand(1).setImm(FPDiff);
812  CallSeqStart.addImm(NumBytes).addImm(0);
813  // End the call sequence *before* emitting the call. Normally, we would
814  // tidy the frame up after the call. However, here, we've laid out the
815  // parameters so that when SP is reset, they will be in the correct
816  // location.
817  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0);
818  }
819 
820  // Now we can add the actual call instruction to the correct basic block.
821  MIRBuilder.insertInstr(MIB);
822 
823  // If Callee is a reg, since it is used by a target specific instruction,
824  // it must have a register class matching the constraint of that instruction.
825  if (Info.Callee.isReg())
827  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
828  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
829  0));
830 
832  Info.LoweredTailCall = true;
833  return true;
834 }
835 
837  CallLoweringInfo &Info) const {
838  MachineFunction &MF = MIRBuilder.getMF();
839  const Function &F = MF.getFunction();
840  MachineRegisterInfo &MRI = MF.getRegInfo();
841  auto &DL = F.getParent()->getDataLayout();
842  const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
843 
844  if (Info.IsMustTailCall) {
845  // TODO: Until we lower all tail calls, we should fall back on this.
846  LLVM_DEBUG(dbgs() << "Cannot lower musttail calls yet.\n");
847  return false;
848  }
849 
850  SmallVector<ArgInfo, 8> OutArgs;
851  for (auto &OrigArg : Info.OrigArgs) {
852  splitToValueTypes(OrigArg, OutArgs, DL, MRI, Info.CallConv);
853  // AAPCS requires that we zero-extend i1 to 8 bits by the caller.
854  if (OrigArg.Ty->isIntegerTy(1))
855  OutArgs.back().Flags[0].setZExt();
856  }
857 
859  if (!Info.OrigRet.Ty->isVoidTy())
860  splitToValueTypes(Info.OrigRet, InArgs, DL, MRI, F.getCallingConv());
861 
862  // If we can lower as a tail call, do that instead.
863  if (Info.IsTailCall &&
864  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs))
865  return lowerTailCall(MIRBuilder, Info, OutArgs);
866 
867  // Find out which ABI gets to decide where things go.
868  CCAssignFn *AssignFnFixed =
869  TLI.CCAssignFnForCall(Info.CallConv, /*IsVarArg=*/false);
870  CCAssignFn *AssignFnVarArg =
871  TLI.CCAssignFnForCall(Info.CallConv, /*IsVarArg=*/true);
872 
873  MachineInstrBuilder CallSeqStart;
874  CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN);
875 
876  // Create a temporarily-floating call instruction so we can add the implicit
877  // uses of arg registers.
878  unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), false);
879 
880  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
881  MIB.add(Info.Callee);
882 
883  // Tell the call which registers are clobbered.
884  auto TRI = MF.getSubtarget<AArch64Subtarget>().getRegisterInfo();
885  const uint32_t *Mask = TRI->getCallPreservedMask(MF, F.getCallingConv());
887  TRI->UpdateCustomCallPreservedMask(MF, &Mask);
888  MIB.addRegMask(Mask);
889 
890  if (TRI->isAnyArgRegReserved(MF))
891  TRI->emitReservedArgRegCallError(MF);
892 
893  // Do the actual argument marshalling.
894  SmallVector<unsigned, 8> PhysRegs;
895  OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,
896  AssignFnVarArg, false);
897  if (!handleAssignments(MIRBuilder, OutArgs, Handler))
898  return false;
899 
900  // Now we can add the actual call instruction to the correct basic block.
901  MIRBuilder.insertInstr(MIB);
902 
903  // If Callee is a reg, since it is used by a target specific
904  // instruction, it must have a register class matching the
905  // constraint of that instruction.
906  if (Info.Callee.isReg())
908  MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
909  *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
910  0));
911 
912  // Finally we can copy the returned value back into its virtual-register. In
913  // symmetry with the arugments, the physical register must be an
914  // implicit-define of the call instruction.
915  if (!Info.OrigRet.Ty->isVoidTy()) {
916  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
917  CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);
918  if (!handleAssignments(MIRBuilder, InArgs, Handler))
919  return false;
920  }
921 
922  if (Info.SwiftErrorVReg) {
923  MIB.addDef(AArch64::X21, RegState::Implicit);
924  MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21));
925  }
926 
927  uint64_t CalleePopBytes =
930  ? alignTo(Handler.StackSize, 16)
931  : 0;
932 
933  CallSeqStart.addImm(Handler.StackSize).addImm(0);
934  MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
935  .addImm(Handler.StackSize)
936  .addImm(CalleePopBytes);
937 
938  return true;
939 }
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:176
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:641
MachineOperand Callee
Destination of the call.
Definition: CallLowering.h:77
bool analyzeArgInfo(CCState &CCState, SmallVectorImpl< ArgInfo > &Args, CCAssignFn &Fn) const
Analyze passed or returned values from a call, supplied in ArgInfo, incorporating info about the pass...
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:40
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasCustomCallingConv() const
Register getReg(unsigned Idx) const
Get the register for the operand index.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool isVector() const
Return true if this is a vector value type.
void addLiveIn(unsigned Reg, unsigned vreg=0)
addLiveIn - Add the specified register as a live-in.
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler) const
Invoke Handler::assignArg on each of the given Args and then use Callback to move them to the assigne...
unsigned Reg
bool IsMustTailCall
True if the call must be tail call optimized.
Definition: CallLowering.h:92
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Offsets
Offsets in bytes from the start of the input buffer.
Definition: SIInstrInfo.h:1127
LLT getType(unsigned Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
unsigned const TargetRegisterInfo * TRI
F(f)
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:446
static bool doesCalleeRestoreStack(CallingConv::ID CallConv, bool TailCallOpt)
Register SwiftErrorVReg
Valid if the call has a swifterror inout parameter, and contains the vreg that the swifterror should ...
Definition: CallLowering.h:87
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:284
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs...
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
bool isVector() const
static unsigned getCallOpcode(const Function &CallerF, bool IsIndirect, bool IsTailCall)
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
const DataLayout & getDataLayout() const
Get the data layout for the module&#39;s target platform.
Definition: Module.cpp:369
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:263
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
This file contains the simple types necessary to represent the attributes associated with functions a...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LocInfo getLocInfo() const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
unsigned getSizeInBits() const
void setArgumentStackToRestore(unsigned bytes)
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:245
const AArch64RegisterInfo * getRegisterInfo() const override
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don&#39;t insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
void setReg(Register Reg)
Change the register this operand corresponds to.
virtual const TargetInstrInfo * getInstrInfo() const
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override
For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
bool isVoidTy() const
Return true if this is &#39;void&#39;.
Definition: Type.h:140
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
MachineRegisterInfo * getMRI()
Getter for MRI.
unsigned const MachineRegisterInfo * MRI
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ZEXT Op.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_BUILD_VECTOR Op0, ...
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, CCAssignFn &CalleeAssignFn, CCAssignFn &CallerAssignFn) const
const GlobalValue * getGlobal() const
Helper class to build MachineInstr.
CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC) const
Selects the correct CCAssignFn for a given CallingConvention value.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1172
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, Register SwiftErrorVReg) const override
This hook must be implemented to lower outgoing return values, described by Val, into the specified v...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline...
const Triple & getTargetTriple() const
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
Definition: ValueTypes.cpp:446
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_GEP Op0, Op1.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function. ...
Definition: Function.cpp:205
Extended Value Type.
Definition: ValueTypes.h:33
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
size_t size() const
Definition: SmallVector.h:52
Argument handling is mostly uniform between the four places that make these decisions: function forma...
Definition: CallLowering.h:112
This class contains a discriminated union of information about pointers in memory operands...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
The memory access writes data.
SmallVector< ArgInfo, 8 > OrigArgs
List of descriptors of the arguments passed to the function.
Definition: CallLowering.h:83
bool IsVarArg
True if the call is to a vararg function.
Definition: CallLowering.h:103
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
CCState - This class holds information needed while lowering arguments and return values...
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:212
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
unsigned getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Promote Memory to Register
Definition: Mem2Reg.cpp:109
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
const Function & getFunction() const
Return the LLVM function that this machine code represents.
This file declares the MachineIRBuilder class.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
The memory access reads data.
#define Success
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const
Selects the correct CCAssignFn for a given CallingConvention value.
Representation of each machine instruction.
Definition: MachineInstr.h:64
void UpdateCustomCalleeSavedRegs(MachineFunction &MF) const
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:126
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
LLVM_NODISCARD bool empty() const
Definition: SmallVector.h:55
CallingConv::ID CallConv
Calling convention to be used for the call.
Definition: CallLowering.h:73
TargetOptions Options
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
The memory access always returns the same value (or traps).
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
uint32_t Size
Definition: Profile.cpp:46
This file describes how to lower LLVM calls to machine code calls.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isReg() const
isReg - Tests if this is a MO_Register operand.
void setBytesInStackArgArea(unsigned bytes)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool IsTailCall
True if the call passes all target-independent checks for tail call optimization. ...
Definition: CallLowering.h:96
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:73
uint64_t getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type...
Definition: DataLayout.h:445
uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
AArch64CallLowering(const AArch64TargetLowering &TLI)
SmallVector< Register, 4 > Regs
Definition: CallLowering.h:47
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
ArgInfo OrigRet
Descriptor for the return type of the function.
Definition: CallLowering.h:80
iterator_range< arg_iterator > args()
Definition: Function.h:719
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143