LLVM  15.0.0git
HexagonPeephole.cpp
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1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 // This peephole pass optimizes in the following cases.
8 // 1. Optimizes redundant sign extends for the following case
9 // Transform the following pattern
10 // %170 = SXTW %166
11 // ...
12 // %176 = COPY %170:isub_lo
13 //
14 // Into
15 // %176 = COPY %166
16 //
17 // 2. Optimizes redundant negation of predicates.
18 // %15 = CMPGTrr %6, %2
19 // ...
20 // %16 = NOT_p killed %15
21 // ...
22 // JMP_c killed %16, <%bb.1>, implicit dead %pc
23 //
24 // Into
25 // %15 = CMPGTrr %6, %2;
26 // ...
27 // JMP_cNot killed %15, <%bb.1>, implicit dead %pc;
28 //
29 // Note: The peephole pass makes the instrucstions like
30 // %170 = SXTW %166 or %16 = NOT_p killed %15
31 // redundant and relies on some form of dead removal instructions, like
32 // DCE or DIE to actually eliminate them.
33 
34 //===----------------------------------------------------------------------===//
35 
36 #include "Hexagon.h"
37 #include "HexagonTargetMachine.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/Statistic.h"
44 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/Pass.h"
50 #include "llvm/Support/Debug.h"
53 #include <algorithm>
54 
55 using namespace llvm;
56 
57 #define DEBUG_TYPE "hexagon-peephole"
58 
59 static cl::opt<bool>
60  DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden,
61  cl::desc("Disable Peephole Optimization"));
62 
63 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", cl::Hidden,
64  cl::desc("Disable Optimization of PNotP"));
65 
66 static cl::opt<bool>
67  DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true),
68  cl::desc("Disable Optimization of Sign/Zero Extends"));
69 
70 static cl::opt<bool>
71  DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden,
72  cl::init(true),
73  cl::desc("Disable Optimization of extensions to i64."));
74 
75 namespace llvm {
78 }
79 
80 namespace {
81  struct HexagonPeephole : public MachineFunctionPass {
82  const HexagonInstrInfo *QII;
83  const HexagonRegisterInfo *QRI;
84  const MachineRegisterInfo *MRI;
85 
86  public:
87  static char ID;
88  HexagonPeephole() : MachineFunctionPass(ID) {
90  }
91 
92  bool runOnMachineFunction(MachineFunction &MF) override;
93 
94  StringRef getPassName() const override {
95  return "Hexagon optimize redundant zero and size extends";
96  }
97 
98  void getAnalysisUsage(AnalysisUsage &AU) const override {
100  }
101  };
102 }
103 
104 char HexagonPeephole::ID = 0;
105 
106 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
107  false, false)
108 
109 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
110  if (skipFunction(MF.getFunction()))
111  return false;
112 
113  QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
114  QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
115  MRI = &MF.getRegInfo();
116 
117  DenseMap<unsigned, unsigned> PeepholeMap;
118  DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
119 
120  if (DisableHexagonPeephole) return false;
121 
122  // Loop over all of the basic blocks.
123  for (MachineBasicBlock &MBB : MF) {
124  PeepholeMap.clear();
125  PeepholeDoubleRegsMap.clear();
126 
127  // Traverse the basic block.
129  // Look for sign extends:
130  // %170 = SXTW %166
131  if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
132  assert(MI.getNumOperands() == 2);
133  MachineOperand &Dst = MI.getOperand(0);
134  MachineOperand &Src = MI.getOperand(1);
135  Register DstReg = Dst.getReg();
136  Register SrcReg = Src.getReg();
137  // Just handle virtual registers.
138  if (DstReg.isVirtual() && SrcReg.isVirtual()) {
139  // Map the following:
140  // %170 = SXTW %166
141  // PeepholeMap[170] = %166
142  PeepholeMap[DstReg] = SrcReg;
143  }
144  }
145 
146  // Look for %170 = COMBINE_ir_V4 (0, %169)
147  // %170:DoublRegs, %169:IntRegs
148  if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
149  assert(MI.getNumOperands() == 3);
150  MachineOperand &Dst = MI.getOperand(0);
151  MachineOperand &Src1 = MI.getOperand(1);
152  MachineOperand &Src2 = MI.getOperand(2);
153  if (Src1.getImm() != 0)
154  continue;
155  Register DstReg = Dst.getReg();
156  Register SrcReg = Src2.getReg();
157  PeepholeMap[DstReg] = SrcReg;
158  }
159 
160  // Look for this sequence below
161  // %DoubleReg1 = LSRd_ri %DoubleReg0, 32
162  // %IntReg = COPY %DoubleReg1:isub_lo.
163  // and convert into
164  // %IntReg = COPY %DoubleReg0:isub_hi.
165  if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
166  assert(MI.getNumOperands() == 3);
167  MachineOperand &Dst = MI.getOperand(0);
168  MachineOperand &Src1 = MI.getOperand(1);
169  MachineOperand &Src2 = MI.getOperand(2);
170  if (Src2.getImm() != 32)
171  continue;
172  Register DstReg = Dst.getReg();
173  Register SrcReg = Src1.getReg();
174  PeepholeDoubleRegsMap[DstReg] =
175  std::make_pair(*&SrcReg, Hexagon::isub_hi);
176  }
177 
178  // Look for P=NOT(P).
179  if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
180  assert(MI.getNumOperands() == 2);
181  MachineOperand &Dst = MI.getOperand(0);
182  MachineOperand &Src = MI.getOperand(1);
183  Register DstReg = Dst.getReg();
184  Register SrcReg = Src.getReg();
185  // Just handle virtual registers.
186  if (DstReg.isVirtual() && SrcReg.isVirtual()) {
187  // Map the following:
188  // %170 = NOT_xx %166
189  // PeepholeMap[170] = %166
190  PeepholeMap[DstReg] = SrcReg;
191  }
192  }
193 
194  // Look for copy:
195  // %176 = COPY %170:isub_lo
196  if (!DisableOptSZExt && MI.isCopy()) {
197  assert(MI.getNumOperands() == 2);
198  MachineOperand &Dst = MI.getOperand(0);
199  MachineOperand &Src = MI.getOperand(1);
200 
201  // Make sure we are copying the lower 32 bits.
202  if (Src.getSubReg() != Hexagon::isub_lo)
203  continue;
204 
205  Register DstReg = Dst.getReg();
206  Register SrcReg = Src.getReg();
207  if (DstReg.isVirtual() && SrcReg.isVirtual()) {
208  // Try to find in the map.
209  if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
210  // Change the 1st operand.
211  MI.removeOperand(1);
212  MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
213  } else {
215  PeepholeDoubleRegsMap.find(SrcReg);
216  if (DI != PeepholeDoubleRegsMap.end()) {
217  std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
218  MI.removeOperand(1);
219  MI.addOperand(MachineOperand::CreateReg(
220  PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
221  false /*isKill*/, false /*isDead*/, false /*isUndef*/,
222  false /*isEarlyClobber*/, PeepholeSrc.second));
223  }
224  }
225  }
226  }
227 
228  // Look for Predicated instructions.
229  if (!DisablePNotP) {
230  bool Done = false;
231  if (QII->isPredicated(MI)) {
232  MachineOperand &Op0 = MI.getOperand(0);
233  Register Reg0 = Op0.getReg();
234  const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
235  if (RC0->getID() == Hexagon::PredRegsRegClassID) {
236  // Handle instructions that have a prediate register in op0
237  // (most cases of predicable instructions).
238  if (Reg0.isVirtual()) {
239  // Try to find in the map.
240  if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
241  // Change the 1st operand and, flip the opcode.
242  MI.getOperand(0).setReg(PeepholeSrc);
243  MRI->clearKillFlags(PeepholeSrc);
244  int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
245  MI.setDesc(QII->get(NewOp));
246  Done = true;
247  }
248  }
249  }
250  }
251 
252  if (!Done) {
253  // Handle special instructions.
254  unsigned Op = MI.getOpcode();
255  unsigned NewOp = 0;
256  unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
257 
258  switch (Op) {
259  case Hexagon::C2_mux:
260  case Hexagon::C2_muxii:
261  NewOp = Op;
262  break;
263  case Hexagon::C2_muxri:
264  NewOp = Hexagon::C2_muxir;
265  break;
266  case Hexagon::C2_muxir:
267  NewOp = Hexagon::C2_muxri;
268  break;
269  }
270  if (NewOp) {
271  Register PSrc = MI.getOperand(PR).getReg();
272  if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
273  BuildMI(MBB, MI.getIterator(), MI.getDebugLoc(), QII->get(NewOp),
274  MI.getOperand(0).getReg())
275  .addReg(POrig)
276  .add(MI.getOperand(S2))
277  .add(MI.getOperand(S1));
278  MRI->clearKillFlags(POrig);
279  MI.eraseFromParent();
280  }
281  } // if (NewOp)
282  } // if (!Done)
283 
284  } // if (!DisablePNotP)
285 
286  } // Instruction
287  } // Basic Block
288  return true;
289 }
290 
292  return new HexagonPeephole();
293 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
DisableHexagonPeephole
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::desc("Disable Peephole Optimization"))
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::DenseMapBase::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:199
Pass.h
Statistic.h
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
DenseMap.h
TargetInstrInfo.h
DisablePNotP
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::desc("Disable Optimization of PNotP"))
HexagonTargetMachine.h
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
MachineRegisterInfo.h
INITIALIZE_PASS
INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole", false, false) bool HexagonPeephole
Definition: HexagonPeephole.cpp:106
CommandLine.h
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
Constants.h
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
DisableOptExtTo64
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
Hexagon.h
DisableOptSZExt
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:642
Passes.h
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::MachineRegisterInfo::clearKillFlags
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Definition: MachineRegisterInfo.cpp:427
llvm::cl::opt< bool >
llvm::DenseMapBase::clear
void clear()
Definition: DenseMap.h:112
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::DenseMap< unsigned, unsigned >
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:618
MachineFunctionPass.h
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:152
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:257
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Definition: HexagonInstrInfo.h:38
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
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MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
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Op
Definition: SIDefines.h:348
llvm::initializeHexagonPeepholePass
void initializeHexagonPeepholePass(PassRegistry &)
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::createHexagonPeephole
FunctionPass * createHexagonPeephole()
Definition: HexagonPeephole.cpp:291
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
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Definition: HexagonRegisterInfo.h:29
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Definition: CommandLine.h:405
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TargetRegisterInfo.h
Debug.h
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unsigned ID
Definition: TargetTransformInfo.h:38