Go to the documentation of this file.
57 #define DEBUG_TYPE "hexagon-peephole"
61 cl::desc(
"Disable Peephole Optimization"));
64 cl::desc(
"Disable Optimization of PNotP"));
68 cl::desc(
"Disable Optimization of Sign/Zero Extends"));
73 cl::desc(
"Disable Optimization of extensions to i64."));
95 return "Hexagon optimize redundant zero and size extends";
110 if (skipFunction(MF.getFunction()))
113 QII =
static_cast<const HexagonInstrInfo *
>(MF.getSubtarget().getInstrInfo());
115 MRI = &MF.getRegInfo();
125 PeepholeDoubleRegsMap.
clear();
142 PeepholeMap[DstReg] = SrcReg;
157 PeepholeMap[DstReg] = SrcReg;
165 if (
MI.getOpcode() == Hexagon::S2_lsr_i_p) {
174 PeepholeDoubleRegsMap[DstReg] =
175 std::make_pair(*&SrcReg, Hexagon::isub_hi);
190 PeepholeMap[DstReg] = SrcReg;
202 if (Src.getSubReg() != Hexagon::isub_lo)
209 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(SrcReg)) {
215 PeepholeDoubleRegsMap.
find(SrcReg);
216 if (DI != PeepholeDoubleRegsMap.
end()) {
217 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
220 PeepholeSrc.first,
false ,
false ,
221 false ,
false ,
false ,
222 false , PeepholeSrc.second));
231 if (QII->isPredicated(
MI)) {
235 if (RC0->
getID() == Hexagon::PredRegsRegClassID) {
240 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(Reg0)) {
242 MI.getOperand(0).setReg(PeepholeSrc);
244 int NewOp = QII->getInvertedPredicatedOpcode(
MI.getOpcode());
245 MI.setDesc(QII->get(NewOp));
254 unsigned Op =
MI.getOpcode();
256 unsigned PR = 1, S1 = 2, S2 = 3;
259 case Hexagon::C2_mux:
260 case Hexagon::C2_muxii:
263 case Hexagon::C2_muxri:
264 NewOp = Hexagon::C2_muxir;
266 case Hexagon::C2_muxir:
267 NewOp = Hexagon::C2_muxri;
272 if (
unsigned POrig = PeepholeMap.
lookup(PSrc)) {
274 MI.getOperand(0).getReg())
276 .
add(
MI.getOperand(S2))
277 .
add(
MI.getOperand(S1));
279 MI.eraseFromParent();
292 return new HexagonPeephole();
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::desc("Disable Peephole Optimization"))
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::desc("Disable Optimization of PNotP"))
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole", false, false) bool HexagonPeephole
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Represent the analysis usage information of a pass.
MachineOperand class - Representation of each machine instruction operand.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Representation of each machine instruction.
initializer< Ty > init(const Ty &Val)
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
StringRef - Represent a constant reference to a string, i.e.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void initializeHexagonPeepholePass(PassRegistry &)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createHexagonPeephole()
FunctionPass class - This class is used to implement most global optimizations.