14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H 15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H 25 class MachineFunction;
28 class MachineOptimizationRemarkEmitter;
29 class MachineOptimizationRemarkMissed;
30 class MachineRegisterInfo;
33 class TargetInstrInfo;
34 class TargetPassConfig;
35 class TargetRegisterInfo;
36 class TargetRegisterClass;
46 const TargetInstrInfo &
TII,
48 const TargetRegisterClass &RegClass);
58 const TargetRegisterInfo &
TRI,
59 MachineRegisterInfo &
MRI,
60 const TargetInstrInfo &
TII,
62 MachineInstr &InsertPt,
63 const TargetRegisterClass &RegClass,
64 const MachineOperand &RegMO,
unsigned OpIdx);
76 const TargetRegisterInfo &
TRI,
77 MachineRegisterInfo &
MRI,
78 const TargetInstrInfo &
TII,
80 MachineInstr &InsertPt,
const MCInstrDesc &II,
81 const MachineOperand &RegMO,
unsigned OpIdx);
93 const TargetInstrInfo &
TII,
94 const TargetRegisterInfo &
TRI,
103 MachineOptimizationRemarkEmitter &
MORE,
104 MachineOptimizationRemarkMissed &
R);
107 MachineOptimizationRemarkEmitter &
MORE,
108 const char *PassName, StringRef Msg,
109 const MachineInstr &
MI);
114 const MachineRegisterInfo &
MRI);
130 bool LookThroughInstrs =
true,
131 bool HandleFConstants =
true);
Simple struct used to hold a constant integer value and a virtual register.
unsigned constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO, unsigned OpIdx)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
This class represents lattice values for constants.
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
const ConstantFP * getConstantFPVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
unsigned const TargetRegisterInfo * TRI
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
const HexagonInstrInfo * TII
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const unsigned Op1, const unsigned Op2, const MachineRegisterInfo &MRI)
unsigned constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, unsigned Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
MVT getMVTForLLT(LLT Ty)
Get a rough equivalent of an MVT for a given LLT.
unsigned const MachineRegisterInfo * MRI
LLT getLLTForMVT(MVT Ty)
Get a rough equivalent of an LLT for a given MVT.
ConstantFP - Floating Point Values [float, double].
Represent the analysis usage information of a pass.
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
Optional< int64_t > getConstantVRegVal(unsigned VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Representation of each machine instruction.
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const unsigned Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream...
Wrapper class representing virtual and physical registers.