LLVM  14.0.0git
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "GISelWorkList.h"
18 #include "LostDebugLocObserver.h"
19 #include "llvm/ADT/StringRef.h"
21 #include "llvm/CodeGen/Register.h"
22 #include "llvm/Support/Alignment.h"
24 #include <cstdint>
25 
26 namespace llvm {
27 
28 class AnalysisUsage;
29 class BlockFrequencyInfo;
30 class GISelKnownBits;
31 class MachineFunction;
32 class MachineInstr;
33 class MachineOperand;
34 class MachineOptimizationRemarkEmitter;
35 class MachineOptimizationRemarkMissed;
36 struct MachinePointerInfo;
37 class MachineRegisterInfo;
38 class MCInstrDesc;
39 class ProfileSummaryInfo;
40 class RegisterBankInfo;
41 class TargetInstrInfo;
42 class TargetLowering;
43 class TargetPassConfig;
44 class TargetRegisterInfo;
45 class TargetRegisterClass;
46 class ConstantInt;
47 class ConstantFP;
48 class APFloat;
49 
50 // Convenience macros for dealing with vector reduction opcodes.
51 #define GISEL_VECREDUCE_CASES_ALL \
52  case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
53  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
54  case TargetOpcode::G_VECREDUCE_FADD: \
55  case TargetOpcode::G_VECREDUCE_FMUL: \
56  case TargetOpcode::G_VECREDUCE_FMAX: \
57  case TargetOpcode::G_VECREDUCE_FMIN: \
58  case TargetOpcode::G_VECREDUCE_ADD: \
59  case TargetOpcode::G_VECREDUCE_MUL: \
60  case TargetOpcode::G_VECREDUCE_AND: \
61  case TargetOpcode::G_VECREDUCE_OR: \
62  case TargetOpcode::G_VECREDUCE_XOR: \
63  case TargetOpcode::G_VECREDUCE_SMAX: \
64  case TargetOpcode::G_VECREDUCE_SMIN: \
65  case TargetOpcode::G_VECREDUCE_UMAX: \
66  case TargetOpcode::G_VECREDUCE_UMIN:
67 
68 #define GISEL_VECREDUCE_CASES_NONSEQ \
69  case TargetOpcode::G_VECREDUCE_FADD: \
70  case TargetOpcode::G_VECREDUCE_FMUL: \
71  case TargetOpcode::G_VECREDUCE_FMAX: \
72  case TargetOpcode::G_VECREDUCE_FMIN: \
73  case TargetOpcode::G_VECREDUCE_ADD: \
74  case TargetOpcode::G_VECREDUCE_MUL: \
75  case TargetOpcode::G_VECREDUCE_AND: \
76  case TargetOpcode::G_VECREDUCE_OR: \
77  case TargetOpcode::G_VECREDUCE_XOR: \
78  case TargetOpcode::G_VECREDUCE_SMAX: \
79  case TargetOpcode::G_VECREDUCE_SMIN: \
80  case TargetOpcode::G_VECREDUCE_UMAX: \
81  case TargetOpcode::G_VECREDUCE_UMIN:
82 
83 /// Try to constrain Reg to the specified register class. If this fails,
84 /// create a new virtual register in the correct class.
85 ///
86 /// \return The virtual register constrained to the right register class.
87 Register constrainRegToClass(MachineRegisterInfo &MRI,
88  const TargetInstrInfo &TII,
89  const RegisterBankInfo &RBI, Register Reg,
90  const TargetRegisterClass &RegClass);
91 
92 /// Constrain the Register operand OpIdx, so that it is now constrained to the
93 /// TargetRegisterClass passed as an argument (RegClass).
94 /// If this fails, create a new virtual register in the correct class and insert
95 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
96 /// In both cases, the function also updates the register of RegMo. The debug
97 /// location of \p InsertPt is used for the new copy.
98 ///
99 /// \return The virtual register constrained to the right register class.
100 Register constrainOperandRegClass(const MachineFunction &MF,
101  const TargetRegisterInfo &TRI,
102  MachineRegisterInfo &MRI,
103  const TargetInstrInfo &TII,
104  const RegisterBankInfo &RBI,
105  MachineInstr &InsertPt,
106  const TargetRegisterClass &RegClass,
107  MachineOperand &RegMO);
108 
109 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
110 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
111 /// correct class and insert a COPY before \p InsertPt if it is a use or after
112 /// if it is a definition. In both cases, the function also updates the register
113 /// of RegMo.
114 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
115 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
116 /// InsertPt is used for the new copy.
117 ///
118 /// \return The virtual register constrained to the right register class.
119 Register constrainOperandRegClass(const MachineFunction &MF,
120  const TargetRegisterInfo &TRI,
121  MachineRegisterInfo &MRI,
122  const TargetInstrInfo &TII,
123  const RegisterBankInfo &RBI,
124  MachineInstr &InsertPt, const MCInstrDesc &II,
125  MachineOperand &RegMO, unsigned OpIdx);
126 
127 /// Mutate the newly-selected instruction \p I to constrain its (possibly
128 /// generic) virtual register operands to the instruction's register class.
129 /// This could involve inserting COPYs before (for uses) or after (for defs).
130 /// This requires the number of operands to match the instruction description.
131 /// \returns whether operand regclass constraining succeeded.
132 ///
133 // FIXME: Not all instructions have the same number of operands. We should
134 // probably expose a constrain helper per operand and let the target selector
135 // constrain individual registers, like fast-isel.
136 bool constrainSelectedInstRegOperands(MachineInstr &I,
137  const TargetInstrInfo &TII,
138  const TargetRegisterInfo &TRI,
139  const RegisterBankInfo &RBI);
140 
141 /// Check if DstReg can be replaced with SrcReg depending on the register
142 /// constraints.
143 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
144 
145 /// Check whether an instruction \p MI is dead: it only defines dead virtual
146 /// registers, and doesn't have other side effects.
147 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
148 
149 /// Report an ISel error as a missed optimization remark to the LLVMContext's
150 /// diagnostic stream. Set the FailedISel MachineFunction property.
151 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
152  MachineOptimizationRemarkEmitter &MORE,
153  MachineOptimizationRemarkMissed &R);
154 
155 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
156  MachineOptimizationRemarkEmitter &MORE,
157  const char *PassName, StringRef Msg,
158  const MachineInstr &MI);
159 
160 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
161 /// diagnostic stream.
162 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
163  MachineOptimizationRemarkEmitter &MORE,
164  MachineOptimizationRemarkMissed &R);
165 
166 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
167 Optional<APInt> getIConstantVRegVal(Register VReg,
168  const MachineRegisterInfo &MRI);
169 
170 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
171 Optional<int64_t> getIConstantVRegSExtVal(Register VReg,
172  const MachineRegisterInfo &MRI);
173 
174 /// Simple struct used to hold a constant integer value and a virtual
175 /// register.
176 struct ValueAndVReg {
179 };
180 
181 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
182 /// on a G_CONSTANT returns its APInt value and def register.
185  const MachineRegisterInfo &MRI,
186  bool LookThroughInstrs = true);
187 
188 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
189 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
191  Register VReg, const MachineRegisterInfo &MRI,
192  bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
193 
197 };
198 
199 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
200 /// on a G_FCONSTANT returns its APFloat value and def register.
203  const MachineRegisterInfo &MRI,
204  bool LookThroughInstrs = true);
205 
207  const MachineRegisterInfo &MRI);
208 
209 /// See if Reg is defined by an single def instruction that is
210 /// Opcode. Also try to do trivial folding if it's a COPY with
211 /// same types. Returns null otherwise.
212 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
213  const MachineRegisterInfo &MRI);
214 
215 /// Simple struct used to hold a Register value and the instruction which
216 /// defines it.
220 };
221 
222 /// Find the def instruction for \p Reg, and underlying value Register folding
223 /// away any copies.
224 ///
225 /// Also walks through hints such as G_ASSERT_ZEXT.
228 
229 /// Find the def instruction for \p Reg, folding away any trivial copies. May
230 /// return nullptr if \p Reg is not a generic virtual register.
231 ///
232 /// Also walks through hints such as G_ASSERT_ZEXT.
234  const MachineRegisterInfo &MRI);
235 
236 /// Find the source register for \p Reg, folding away any trivial copies. It
237 /// will be an output register of the instruction that getDefIgnoringCopies
238 /// returns. May return an invalid register if \p Reg is not a generic virtual
239 /// register.
240 ///
241 /// Also walks through hints such as G_ASSERT_ZEXT.
243 
244 // Templated variant of getOpcodeDef returning a MachineInstr derived T.
245 /// See if Reg is defined by an single def instruction of type T
246 /// Also try to do trivial folding if it's a COPY with
247 /// same types. Returns null otherwise.
248 template <class T>
251  return dyn_cast_or_null<T>(DefMI);
252 }
253 
254 /// Returns an APFloat from Val converted to the appropriate size.
255 APFloat getAPFloatFromSize(double Val, unsigned Size);
256 
257 /// Modify analysis usage so it preserves passes required for the SelectionDAG
258 /// fallback.
259 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
260 
261 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
262  const Register Op2,
263  const MachineRegisterInfo &MRI);
264 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
265  const Register Op2,
266  const MachineRegisterInfo &MRI);
267 
268 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
269  uint64_t Imm, const MachineRegisterInfo &MRI);
270 
271 Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
272  Register Src,
273  const MachineRegisterInfo &MRI);
274 
275 /// Test if the given value is known to have exactly one bit set. This differs
276 /// from computeKnownBits in that it doesn't necessarily determine which bit is
277 /// set.
278 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
279  GISelKnownBits *KnownBits = nullptr);
280 
281 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
282 /// this returns if \p Val can be assumed to never be a signaling NaN.
283 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
284  bool SNaN = false);
285 
286 /// Returns true if \p Val can be assumed to never be a signaling NaN.
288  return isKnownNeverNaN(Val, MRI, true);
289 }
290 
291 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
292 
293 /// Return a virtual register corresponding to the incoming argument register \p
294 /// PhysReg. This register is expected to have class \p RC, and optional type \p
295 /// RegTy. This assumes all references to the register will use the same type.
296 ///
297 /// If there is an existing live-in argument register, it will be returned.
298 /// This will also ensure there is a valid copy
299 Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII,
300  MCRegister PhysReg,
301  const TargetRegisterClass &RC,
302  LLT RegTy = LLT());
303 
304 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
305 /// number of vector elements or scalar bitwidth. The intent is a
306 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
307 /// \p OrigTy elements, and unmerged into \p TargetTy
309 LLT getLCMType(LLT OrigTy, LLT TargetTy);
310 
311 /// Return a type where the total size is the greatest common divisor of \p
312 /// OrigTy and \p TargetTy. This will try to either change the number of vector
313 /// elements, or bitwidth of scalars. The intent is the result type can be used
314 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
315 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
316 /// with intermediate casts) can re-form \p TargetTy.
317 ///
318 /// If these are vectors with different element types, this will try to produce
319 /// a vector with a compatible total size, but the element type of \p OrigTy. If
320 /// this can't be satisfied, this will produce a scalar smaller than the
321 /// original vector elements.
322 ///
323 /// In the worst case, this returns LLT::scalar(1)
325 LLT getGCDType(LLT OrigTy, LLT TargetTy);
326 
327 /// Represents a value which can be a Register or a constant.
328 ///
329 /// This is useful in situations where an instruction may have an interesting
330 /// register operand or interesting constant operand. For a concrete example,
331 /// \see getVectorSplat.
333  int64_t Cst;
334  Register Reg;
335  bool IsReg;
336 
337 public:
338  explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
339  explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
340  bool isReg() const { return IsReg; }
341  bool isCst() const { return !IsReg; }
342  Register getReg() const {
343  assert(isReg() && "Expected a register!");
344  return Reg;
345  }
346  int64_t getCst() const {
347  assert(isCst() && "Expected a constant!");
348  return Cst;
349  }
350 };
351 
352 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
353 /// If \p MI is not a splat, returns None.
354 Optional<int> getSplatIndex(MachineInstr &MI);
355 
356 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
357 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
358  const MachineRegisterInfo &MRI);
359 
360 /// Returns a floating point scalar constant of a build vector splat if it
361 /// exists. When \p AllowUndef == true some elements can be undef but not all.
362 Optional<FPValueAndVReg> getFConstantSplat(Register VReg,
363  const MachineRegisterInfo &MRI,
364  bool AllowUndef = true);
365 
366 /// Return true if the specified instruction is a G_BUILD_VECTOR or
367 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
368 bool isBuildVectorAllZeros(const MachineInstr &MI,
369  const MachineRegisterInfo &MRI,
370  bool AllowUndef = false);
371 
372 /// Return true if the specified instruction is a G_BUILD_VECTOR or
373 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
374 bool isBuildVectorAllOnes(const MachineInstr &MI,
375  const MachineRegisterInfo &MRI,
376  bool AllowUndef = false);
377 
378 /// \returns a value when \p MI is a vector splat. The splat can be either a
379 /// Register or a constant.
380 ///
381 /// Examples:
382 ///
383 /// \code
384 /// %reg = COPY $physreg
385 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
386 /// \endcode
387 ///
388 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
389 /// containing %reg.
390 ///
391 /// \code
392 /// %cst = G_CONSTANT iN 4
393 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
394 /// \endcode
395 ///
396 /// In the above case, this will return a RegOrConstant containing 4.
397 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
398  const MachineRegisterInfo &MRI);
399 
400 /// Attempt to match a unary predicate against a scalar/splat constant or every
401 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
402 /// value was undef.
403 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
404  std::function<bool(const Constant *ConstVal)> Match,
405  bool AllowUndefs = false);
406 
407 /// Returns true if given the TargetLowering's boolean contents information,
408 /// the value \p Val contains a true value.
409 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
410  bool IsFP);
411 
412 /// Returns an integer representing true, as defined by the
413 /// TargetBooleanContents.
414 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
415 
416 /// Returns true if the given block should be optimized for size.
417 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
418  BlockFrequencyInfo *BFI);
419 
422  LostDebugLocObserver *LocObserver,
423  SmallInstListTy &DeadInstChain);
425  LostDebugLocObserver *LocObserver = nullptr);
427  LostDebugLocObserver *LocObserver = nullptr);
428 
429 } // End namespace llvm.
430 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:492
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:283
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1102
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:444
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::FPValueAndVReg::Value
APFloat Value
Definition: Utils.h:195
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:176
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:464
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
StringRef.h
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:458
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:451
MachineBasicBlock.h
llvm::RegOrConstant::isCst
bool isCst() const
Definition: Utils.h:341
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1076
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:665
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1119
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:532
llvm::RegOrConstant::getCst
int64_t getCst() const
Definition: Utils.h:346
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:802
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:245
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:332
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:177
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:135
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1064
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:198
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:178
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:858
llvm::RegOrConstant::getReg
Register getReg() const
Definition: Utils.h:342
LostDebugLocObserver.h
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:699
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:716
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::FPValueAndVReg::VReg
Register VReg
Definition: Utils.h:196
llvm::RegOrConstant::isReg
bool isReg() const
Definition: Utils.h:340
LowLevelTypeImpl.h
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1019
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:812
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:194
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1134
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1051
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:648
I
#define I(x, y, z)
Definition: MD5.cpp:59
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:271
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:195
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:398
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:39
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:392
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:421
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3739
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
GISelWorkList.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:999
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:205
Alignment.h
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:977
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:217
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:181
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:287
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1005
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:406
llvm::RegOrConstant::RegOrConstant
RegOrConstant(int64_t Cst)
Definition: Utils.h:339
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:251
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:344
llvm::GISelWorkList
Definition: GISelWorkList.h:28
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:985
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:49
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:417
Register.h
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:292
llvm::RegOrConstant::RegOrConstant
RegOrConstant(Register Reg)
Definition: Utils.h:338
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:219
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:218
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1853
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:425
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:669
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:993
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:477