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Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "GISelWorkList.h"
18 #include "llvm/ADT/APFloat.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Register.h"
21 #include "llvm/IR/DebugLoc.h"
22 #include "llvm/Support/Alignment.h"
23 #include "llvm/Support/Casting.h"
25 #include <cstdint>
26 
27 namespace llvm {
28 
29 class AnalysisUsage;
30 class LostDebugLocObserver;
31 class MachineBasicBlock;
32 class BlockFrequencyInfo;
33 class GISelKnownBits;
34 class MachineFunction;
35 class MachineInstr;
36 class MachineOperand;
37 class MachineOptimizationRemarkEmitter;
38 class MachineOptimizationRemarkMissed;
39 struct MachinePointerInfo;
40 class MachineRegisterInfo;
41 class MCInstrDesc;
42 class ProfileSummaryInfo;
43 class RegisterBankInfo;
44 class TargetInstrInfo;
45 class TargetLowering;
46 class TargetPassConfig;
47 class TargetRegisterInfo;
48 class TargetRegisterClass;
49 class ConstantFP;
50 class APFloat;
51 class MachineIRBuilder;
52 
53 // Convenience macros for dealing with vector reduction opcodes.
54 #define GISEL_VECREDUCE_CASES_ALL \
55  case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
56  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
57  case TargetOpcode::G_VECREDUCE_FADD: \
58  case TargetOpcode::G_VECREDUCE_FMUL: \
59  case TargetOpcode::G_VECREDUCE_FMAX: \
60  case TargetOpcode::G_VECREDUCE_FMIN: \
61  case TargetOpcode::G_VECREDUCE_ADD: \
62  case TargetOpcode::G_VECREDUCE_MUL: \
63  case TargetOpcode::G_VECREDUCE_AND: \
64  case TargetOpcode::G_VECREDUCE_OR: \
65  case TargetOpcode::G_VECREDUCE_XOR: \
66  case TargetOpcode::G_VECREDUCE_SMAX: \
67  case TargetOpcode::G_VECREDUCE_SMIN: \
68  case TargetOpcode::G_VECREDUCE_UMAX: \
69  case TargetOpcode::G_VECREDUCE_UMIN:
70 
71 #define GISEL_VECREDUCE_CASES_NONSEQ \
72  case TargetOpcode::G_VECREDUCE_FADD: \
73  case TargetOpcode::G_VECREDUCE_FMUL: \
74  case TargetOpcode::G_VECREDUCE_FMAX: \
75  case TargetOpcode::G_VECREDUCE_FMIN: \
76  case TargetOpcode::G_VECREDUCE_ADD: \
77  case TargetOpcode::G_VECREDUCE_MUL: \
78  case TargetOpcode::G_VECREDUCE_AND: \
79  case TargetOpcode::G_VECREDUCE_OR: \
80  case TargetOpcode::G_VECREDUCE_XOR: \
81  case TargetOpcode::G_VECREDUCE_SMAX: \
82  case TargetOpcode::G_VECREDUCE_SMIN: \
83  case TargetOpcode::G_VECREDUCE_UMAX: \
84  case TargetOpcode::G_VECREDUCE_UMIN:
85 
86 /// Try to constrain Reg to the specified register class. If this fails,
87 /// create a new virtual register in the correct class.
88 ///
89 /// \return The virtual register constrained to the right register class.
90 Register constrainRegToClass(MachineRegisterInfo &MRI,
91  const TargetInstrInfo &TII,
92  const RegisterBankInfo &RBI, Register Reg,
93  const TargetRegisterClass &RegClass);
94 
95 /// Constrain the Register operand OpIdx, so that it is now constrained to the
96 /// TargetRegisterClass passed as an argument (RegClass).
97 /// If this fails, create a new virtual register in the correct class and insert
98 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
99 /// In both cases, the function also updates the register of RegMo. The debug
100 /// location of \p InsertPt is used for the new copy.
101 ///
102 /// \return The virtual register constrained to the right register class.
103 Register constrainOperandRegClass(const MachineFunction &MF,
104  const TargetRegisterInfo &TRI,
105  MachineRegisterInfo &MRI,
106  const TargetInstrInfo &TII,
107  const RegisterBankInfo &RBI,
108  MachineInstr &InsertPt,
109  const TargetRegisterClass &RegClass,
110  MachineOperand &RegMO);
111 
112 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
113 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
114 /// correct class and insert a COPY before \p InsertPt if it is a use or after
115 /// if it is a definition. In both cases, the function also updates the register
116 /// of RegMo.
117 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
118 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
119 /// InsertPt is used for the new copy.
120 ///
121 /// \return The virtual register constrained to the right register class.
122 Register constrainOperandRegClass(const MachineFunction &MF,
123  const TargetRegisterInfo &TRI,
124  MachineRegisterInfo &MRI,
125  const TargetInstrInfo &TII,
126  const RegisterBankInfo &RBI,
127  MachineInstr &InsertPt, const MCInstrDesc &II,
128  MachineOperand &RegMO, unsigned OpIdx);
129 
130 /// Mutate the newly-selected instruction \p I to constrain its (possibly
131 /// generic) virtual register operands to the instruction's register class.
132 /// This could involve inserting COPYs before (for uses) or after (for defs).
133 /// This requires the number of operands to match the instruction description.
134 /// \returns whether operand regclass constraining succeeded.
135 ///
136 // FIXME: Not all instructions have the same number of operands. We should
137 // probably expose a constrain helper per operand and let the target selector
138 // constrain individual registers, like fast-isel.
139 bool constrainSelectedInstRegOperands(MachineInstr &I,
140  const TargetInstrInfo &TII,
141  const TargetRegisterInfo &TRI,
142  const RegisterBankInfo &RBI);
143 
144 /// Check if DstReg can be replaced with SrcReg depending on the register
145 /// constraints.
146 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
147 
148 /// Check whether an instruction \p MI is dead: it only defines dead virtual
149 /// registers, and doesn't have other side effects.
150 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
151 
152 /// Report an ISel error as a missed optimization remark to the LLVMContext's
153 /// diagnostic stream. Set the FailedISel MachineFunction property.
154 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
155  MachineOptimizationRemarkEmitter &MORE,
156  MachineOptimizationRemarkMissed &R);
157 
158 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
159  MachineOptimizationRemarkEmitter &MORE,
160  const char *PassName, StringRef Msg,
161  const MachineInstr &MI);
162 
163 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
164 /// diagnostic stream.
165 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
166  MachineOptimizationRemarkEmitter &MORE,
167  MachineOptimizationRemarkMissed &R);
168 
169 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
170 Optional<APInt> getIConstantVRegVal(Register VReg,
171  const MachineRegisterInfo &MRI);
172 
173 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
174 Optional<int64_t> getIConstantVRegSExtVal(Register VReg,
175  const MachineRegisterInfo &MRI);
176 
177 /// Simple struct used to hold a constant integer value and a virtual
178 /// register.
179 struct ValueAndVReg {
182 };
183 
184 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
185 /// on a G_CONSTANT returns its APInt value and def register.
188  const MachineRegisterInfo &MRI,
189  bool LookThroughInstrs = true);
190 
191 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
192 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
194  Register VReg, const MachineRegisterInfo &MRI,
195  bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
196 
200 };
201 
202 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
203 /// on a G_FCONSTANT returns its APFloat value and def register.
206  const MachineRegisterInfo &MRI,
207  bool LookThroughInstrs = true);
208 
210  const MachineRegisterInfo &MRI);
211 
212 /// See if Reg is defined by an single def instruction that is
213 /// Opcode. Also try to do trivial folding if it's a COPY with
214 /// same types. Returns null otherwise.
215 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
216  const MachineRegisterInfo &MRI);
217 
218 /// Simple struct used to hold a Register value and the instruction which
219 /// defines it.
223 };
224 
225 /// Find the def instruction for \p Reg, and underlying value Register folding
226 /// away any copies.
227 ///
228 /// Also walks through hints such as G_ASSERT_ZEXT.
231 
232 /// Find the def instruction for \p Reg, folding away any trivial copies. May
233 /// return nullptr if \p Reg is not a generic virtual register.
234 ///
235 /// Also walks through hints such as G_ASSERT_ZEXT.
237  const MachineRegisterInfo &MRI);
238 
239 /// Find the source register for \p Reg, folding away any trivial copies. It
240 /// will be an output register of the instruction that getDefIgnoringCopies
241 /// returns. May return an invalid register if \p Reg is not a generic virtual
242 /// register.
243 ///
244 /// Also walks through hints such as G_ASSERT_ZEXT.
246 
247 // Templated variant of getOpcodeDef returning a MachineInstr derived T.
248 /// See if Reg is defined by an single def instruction of type T
249 /// Also try to do trivial folding if it's a COPY with
250 /// same types. Returns null otherwise.
251 template <class T>
254  return dyn_cast_or_null<T>(DefMI);
255 }
256 
257 /// Returns an APFloat from Val converted to the appropriate size.
258 APFloat getAPFloatFromSize(double Val, unsigned Size);
259 
260 /// Modify analysis usage so it preserves passes required for the SelectionDAG
261 /// fallback.
262 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
263 
264 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
265  const Register Op2,
266  const MachineRegisterInfo &MRI);
267 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
268  const Register Op2,
269  const MachineRegisterInfo &MRI);
270 
271 /// Tries to constant fold a vector binop with sources \p Op1 and \p Op2.
272 /// Returns an empty vector on failure.
273 SmallVector<APInt> ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
274  const Register Op2,
275  const MachineRegisterInfo &MRI);
276 
277 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
278  uint64_t Imm, const MachineRegisterInfo &MRI);
279 
280 Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
281  Register Src,
282  const MachineRegisterInfo &MRI);
283 
284 /// Tries to constant fold a G_CTLZ operation on \p Src. If \p Src is a vector
285 /// then it tries to do an element-wise constant fold.
286 Optional<SmallVector<unsigned>>
287 ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI);
288 
289 /// Test if the given value is known to have exactly one bit set. This differs
290 /// from computeKnownBits in that it doesn't necessarily determine which bit is
291 /// set.
292 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
293  GISelKnownBits *KnownBits = nullptr);
294 
295 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
296 /// this returns if \p Val can be assumed to never be a signaling NaN.
297 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
298  bool SNaN = false);
299 
300 /// Returns true if \p Val can be assumed to never be a signaling NaN.
302  return isKnownNeverNaN(Val, MRI, true);
303 }
304 
305 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
306 
307 /// Return a virtual register corresponding to the incoming argument register \p
308 /// PhysReg. This register is expected to have class \p RC, and optional type \p
309 /// RegTy. This assumes all references to the register will use the same type.
310 ///
311 /// If there is an existing live-in argument register, it will be returned.
312 /// This will also ensure there is a valid copy
313 Register getFunctionLiveInPhysReg(MachineFunction &MF,
314  const TargetInstrInfo &TII,
315  MCRegister PhysReg,
316  const TargetRegisterClass &RC,
317  const DebugLoc &DL, LLT RegTy = LLT());
318 
319 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
320 /// number of vector elements or scalar bitwidth. The intent is a
321 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
322 /// \p OrigTy elements, and unmerged into \p TargetTy
324 LLT getLCMType(LLT OrigTy, LLT TargetTy);
325 
327 /// Return smallest type that covers both \p OrigTy and \p TargetTy and is
328 /// multiple of TargetTy.
329 LLT getCoverTy(LLT OrigTy, LLT TargetTy);
330 
331 /// Return a type where the total size is the greatest common divisor of \p
332 /// OrigTy and \p TargetTy. This will try to either change the number of vector
333 /// elements, or bitwidth of scalars. The intent is the result type can be used
334 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
335 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
336 /// with intermediate casts) can re-form \p TargetTy.
337 ///
338 /// If these are vectors with different element types, this will try to produce
339 /// a vector with a compatible total size, but the element type of \p OrigTy. If
340 /// this can't be satisfied, this will produce a scalar smaller than the
341 /// original vector elements.
342 ///
343 /// In the worst case, this returns LLT::scalar(1)
345 LLT getGCDType(LLT OrigTy, LLT TargetTy);
346 
347 /// Represents a value which can be a Register or a constant.
348 ///
349 /// This is useful in situations where an instruction may have an interesting
350 /// register operand or interesting constant operand. For a concrete example,
351 /// \see getVectorSplat.
353  int64_t Cst;
354  Register Reg;
355  bool IsReg;
356 
357 public:
358  explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
359  explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
360  bool isReg() const { return IsReg; }
361  bool isCst() const { return !IsReg; }
362  Register getReg() const {
363  assert(isReg() && "Expected a register!");
364  return Reg;
365  }
366  int64_t getCst() const {
367  assert(isCst() && "Expected a constant!");
368  return Cst;
369  }
370 };
371 
372 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
373 /// If \p MI is not a splat, returns None.
374 Optional<int> getSplatIndex(MachineInstr &MI);
375 
376 /// \returns the scalar integral splat value of \p Reg if possible.
377 Optional<APInt> getIConstantSplatVal(const Register Reg,
378  const MachineRegisterInfo &MRI);
379 
380 /// \returns the scalar integral splat value defined by \p MI if possible.
381 Optional<APInt> getIConstantSplatVal(const MachineInstr &MI,
382  const MachineRegisterInfo &MRI);
383 
384 /// \returns the scalar sign extended integral splat value of \p Reg if
385 /// possible.
386 Optional<int64_t> getIConstantSplatSExtVal(const Register Reg,
387  const MachineRegisterInfo &MRI);
388 
389 /// \returns the scalar sign extended integral splat value defined by \p MI if
390 /// possible.
391 Optional<int64_t> getIConstantSplatSExtVal(const MachineInstr &MI,
392  const MachineRegisterInfo &MRI);
393 
394 /// Returns a floating point scalar constant of a build vector splat if it
395 /// exists. When \p AllowUndef == true some elements can be undef but not all.
396 Optional<FPValueAndVReg> getFConstantSplat(Register VReg,
397  const MachineRegisterInfo &MRI,
398  bool AllowUndef = true);
399 
400 /// Return true if the specified register is defined by G_BUILD_VECTOR or
401 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
402 bool isBuildVectorConstantSplat(const Register Reg,
403  const MachineRegisterInfo &MRI,
404  int64_t SplatValue, bool AllowUndef);
405 
406 /// Return true if the specified instruction is a G_BUILD_VECTOR or
407 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
408 bool isBuildVectorConstantSplat(const MachineInstr &MI,
409  const MachineRegisterInfo &MRI,
410  int64_t SplatValue, bool AllowUndef);
411 
412 /// Return true if the specified instruction is a G_BUILD_VECTOR or
413 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
414 bool isBuildVectorAllZeros(const MachineInstr &MI,
415  const MachineRegisterInfo &MRI,
416  bool AllowUndef = false);
417 
418 /// Return true if the specified instruction is a G_BUILD_VECTOR or
419 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
420 bool isBuildVectorAllOnes(const MachineInstr &MI,
421  const MachineRegisterInfo &MRI,
422  bool AllowUndef = false);
423 
424 /// Return true if the specified instruction is known to be a constant, or a
425 /// vector of constants.
426 ///
427 /// If \p AllowFP is true, this will consider G_FCONSTANT in addition to
428 /// G_CONSTANT. If \p AllowOpaqueConstants is true, constant-like instructions
429 /// such as G_GLOBAL_VALUE will also be considered.
430 bool isConstantOrConstantVector(const MachineInstr &MI,
431  const MachineRegisterInfo &MRI,
432  bool AllowFP = true,
433  bool AllowOpaqueConstants = true);
434 
435 /// Return true if the value is a constant 0 integer or a splatted vector of a
436 /// constant 0 integer (with no undefs if \p AllowUndefs is false). This will
437 /// handle G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC as truncation is not an issue
438 /// for null values.
439 bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI,
440  bool AllowUndefs = false);
441 
442 /// Return true if the value is a constant -1 integer or a splatted vector of a
443 /// constant -1 integer (with no undefs if \p AllowUndefs is false).
444 bool isAllOnesOrAllOnesSplat(const MachineInstr &MI,
445  const MachineRegisterInfo &MRI,
446  bool AllowUndefs = false);
447 
448 /// \returns a value when \p MI is a vector splat. The splat can be either a
449 /// Register or a constant.
450 ///
451 /// Examples:
452 ///
453 /// \code
454 /// %reg = COPY $physreg
455 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
456 /// \endcode
457 ///
458 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
459 /// containing %reg.
460 ///
461 /// \code
462 /// %cst = G_CONSTANT iN 4
463 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
464 /// \endcode
465 ///
466 /// In the above case, this will return a RegOrConstant containing 4.
467 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
468  const MachineRegisterInfo &MRI);
469 
470 /// Determines if \p MI defines a constant integer or a build vector of
471 /// constant integers. Treats undef values as constants.
472 bool isConstantOrConstantVector(MachineInstr &MI,
473  const MachineRegisterInfo &MRI);
474 
475 /// Determines if \p MI defines a constant integer or a splat vector of
476 /// constant integers.
477 /// \returns the scalar constant or None.
478 Optional<APInt> isConstantOrConstantSplatVector(MachineInstr &MI,
479  const MachineRegisterInfo &MRI);
480 
481 /// Attempt to match a unary predicate against a scalar/splat constant or every
482 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
483 /// value was undef.
484 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
485  std::function<bool(const Constant *ConstVal)> Match,
486  bool AllowUndefs = false);
487 
488 /// Returns true if given the TargetLowering's boolean contents information,
489 /// the value \p Val contains a true value.
490 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
491  bool IsFP);
492 
493 /// Returns an integer representing true, as defined by the
494 /// TargetBooleanContents.
495 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
496 
497 /// Returns true if the given block should be optimized for size.
498 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
499  BlockFrequencyInfo *BFI);
500 
503  LostDebugLocObserver *LocObserver,
504  SmallInstListTy &DeadInstChain);
506  LostDebugLocObserver *LocObserver = nullptr);
508  LostDebugLocObserver *LocObserver = nullptr);
509 
510 } // End namespace llvm.
511 #endif
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:437
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:298
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1305
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:459
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::FPValueAndVReg::Value
APFloat Value
Definition: Utils.h:198
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:179
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:479
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
StringRef.h
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:473
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:466
llvm::isAllOnesOrAllOnesSplat
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1226
llvm::RegOrConstant::isCst
bool isCst() const
Definition: Utils.h:361
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1176
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1298
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1319
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:556
llvm::RegOrConstant::getCst
int64_t getCst() const
Definition: Utils.h:366
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:878
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:260
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:352
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:180
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:150
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1286
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:240
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:181
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:712
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:949
llvm::RegOrConstant::getReg
Register getReg() const
Definition: Utils.h:362
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:745
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:762
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1196
DebugLoc.h
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::FPValueAndVReg::VReg
Register VReg
Definition: Utils.h:199
llvm::RegOrConstant::isReg
bool isReg() const
Definition: Utils.h:360
LowLevelTypeImpl.h
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1241
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:888
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:197
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1334
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1273
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:695
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:934
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:286
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:210
llvm::getIConstantSplatSExtVal
Optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1091
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:413
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:41
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:407
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:429
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3787
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::isNullOrNullSplat
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1208
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
GISelWorkList.h
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:776
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1119
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:199
Alignment.h
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:220
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:196
llvm::getIConstantSplatVal
Optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1073
Casting.h
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:301
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1125
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:421
llvm::RegOrConstant::RegOrConstant
RegOrConstant(int64_t Cst)
Definition: Utils.h:359
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:266
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:349
llvm::GISelWorkList
Definition: GISelWorkList.h:27
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1105
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:51
llvm::ConstantFoldVectorBinop
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:611
llvm::isBuildVectorConstantSplat
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1058
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:432
Register.h
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:327
llvm::RegOrConstant::RegOrConstant
RegOrConstant(Register Reg)
Definition: Utils.h:358
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:222
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:221
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:440
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1113
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:492