LLVM  14.0.0git
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "GISelWorkList.h"
18 #include "LostDebugLocObserver.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/StringRef.h"
22 #include "llvm/CodeGen/Register.h"
23 #include "llvm/Support/Alignment.h"
25 #include <cstdint>
26 
27 namespace llvm {
28 
29 class AnalysisUsage;
30 class BlockFrequencyInfo;
31 class GISelKnownBits;
32 class MachineFunction;
33 class MachineInstr;
34 class MachineOperand;
35 class MachineOptimizationRemarkEmitter;
36 class MachineOptimizationRemarkMissed;
37 struct MachinePointerInfo;
38 class MachineRegisterInfo;
39 class MCInstrDesc;
40 class ProfileSummaryInfo;
41 class RegisterBankInfo;
42 class TargetInstrInfo;
43 class TargetLowering;
44 class TargetPassConfig;
45 class TargetRegisterInfo;
46 class TargetRegisterClass;
47 class ConstantFP;
48 class APFloat;
49 class MachineIRBuilder;
50 
51 // Convenience macros for dealing with vector reduction opcodes.
52 #define GISEL_VECREDUCE_CASES_ALL \
53  case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
54  case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
55  case TargetOpcode::G_VECREDUCE_FADD: \
56  case TargetOpcode::G_VECREDUCE_FMUL: \
57  case TargetOpcode::G_VECREDUCE_FMAX: \
58  case TargetOpcode::G_VECREDUCE_FMIN: \
59  case TargetOpcode::G_VECREDUCE_ADD: \
60  case TargetOpcode::G_VECREDUCE_MUL: \
61  case TargetOpcode::G_VECREDUCE_AND: \
62  case TargetOpcode::G_VECREDUCE_OR: \
63  case TargetOpcode::G_VECREDUCE_XOR: \
64  case TargetOpcode::G_VECREDUCE_SMAX: \
65  case TargetOpcode::G_VECREDUCE_SMIN: \
66  case TargetOpcode::G_VECREDUCE_UMAX: \
67  case TargetOpcode::G_VECREDUCE_UMIN:
68 
69 #define GISEL_VECREDUCE_CASES_NONSEQ \
70  case TargetOpcode::G_VECREDUCE_FADD: \
71  case TargetOpcode::G_VECREDUCE_FMUL: \
72  case TargetOpcode::G_VECREDUCE_FMAX: \
73  case TargetOpcode::G_VECREDUCE_FMIN: \
74  case TargetOpcode::G_VECREDUCE_ADD: \
75  case TargetOpcode::G_VECREDUCE_MUL: \
76  case TargetOpcode::G_VECREDUCE_AND: \
77  case TargetOpcode::G_VECREDUCE_OR: \
78  case TargetOpcode::G_VECREDUCE_XOR: \
79  case TargetOpcode::G_VECREDUCE_SMAX: \
80  case TargetOpcode::G_VECREDUCE_SMIN: \
81  case TargetOpcode::G_VECREDUCE_UMAX: \
82  case TargetOpcode::G_VECREDUCE_UMIN:
83 
84 /// Try to constrain Reg to the specified register class. If this fails,
85 /// create a new virtual register in the correct class.
86 ///
87 /// \return The virtual register constrained to the right register class.
88 Register constrainRegToClass(MachineRegisterInfo &MRI,
89  const TargetInstrInfo &TII,
90  const RegisterBankInfo &RBI, Register Reg,
91  const TargetRegisterClass &RegClass);
92 
93 /// Constrain the Register operand OpIdx, so that it is now constrained to the
94 /// TargetRegisterClass passed as an argument (RegClass).
95 /// If this fails, create a new virtual register in the correct class and insert
96 /// a COPY before \p InsertPt if it is a use or after if it is a definition.
97 /// In both cases, the function also updates the register of RegMo. The debug
98 /// location of \p InsertPt is used for the new copy.
99 ///
100 /// \return The virtual register constrained to the right register class.
101 Register constrainOperandRegClass(const MachineFunction &MF,
102  const TargetRegisterInfo &TRI,
103  MachineRegisterInfo &MRI,
104  const TargetInstrInfo &TII,
105  const RegisterBankInfo &RBI,
106  MachineInstr &InsertPt,
107  const TargetRegisterClass &RegClass,
108  MachineOperand &RegMO);
109 
110 /// Try to constrain Reg so that it is usable by argument OpIdx of the provided
111 /// MCInstrDesc \p II. If this fails, create a new virtual register in the
112 /// correct class and insert a COPY before \p InsertPt if it is a use or after
113 /// if it is a definition. In both cases, the function also updates the register
114 /// of RegMo.
115 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
116 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
117 /// InsertPt is used for the new copy.
118 ///
119 /// \return The virtual register constrained to the right register class.
120 Register constrainOperandRegClass(const MachineFunction &MF,
121  const TargetRegisterInfo &TRI,
122  MachineRegisterInfo &MRI,
123  const TargetInstrInfo &TII,
124  const RegisterBankInfo &RBI,
125  MachineInstr &InsertPt, const MCInstrDesc &II,
126  MachineOperand &RegMO, unsigned OpIdx);
127 
128 /// Mutate the newly-selected instruction \p I to constrain its (possibly
129 /// generic) virtual register operands to the instruction's register class.
130 /// This could involve inserting COPYs before (for uses) or after (for defs).
131 /// This requires the number of operands to match the instruction description.
132 /// \returns whether operand regclass constraining succeeded.
133 ///
134 // FIXME: Not all instructions have the same number of operands. We should
135 // probably expose a constrain helper per operand and let the target selector
136 // constrain individual registers, like fast-isel.
137 bool constrainSelectedInstRegOperands(MachineInstr &I,
138  const TargetInstrInfo &TII,
139  const TargetRegisterInfo &TRI,
140  const RegisterBankInfo &RBI);
141 
142 /// Check if DstReg can be replaced with SrcReg depending on the register
143 /// constraints.
144 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
145 
146 /// Check whether an instruction \p MI is dead: it only defines dead virtual
147 /// registers, and doesn't have other side effects.
148 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
149 
150 /// Report an ISel error as a missed optimization remark to the LLVMContext's
151 /// diagnostic stream. Set the FailedISel MachineFunction property.
152 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
153  MachineOptimizationRemarkEmitter &MORE,
154  MachineOptimizationRemarkMissed &R);
155 
156 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
157  MachineOptimizationRemarkEmitter &MORE,
158  const char *PassName, StringRef Msg,
159  const MachineInstr &MI);
160 
161 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
162 /// diagnostic stream.
163 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
164  MachineOptimizationRemarkEmitter &MORE,
165  MachineOptimizationRemarkMissed &R);
166 
167 /// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
168 Optional<APInt> getIConstantVRegVal(Register VReg,
169  const MachineRegisterInfo &MRI);
170 
171 /// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
172 Optional<int64_t> getIConstantVRegSExtVal(Register VReg,
173  const MachineRegisterInfo &MRI);
174 
175 /// Simple struct used to hold a constant integer value and a virtual
176 /// register.
177 struct ValueAndVReg {
180 };
181 
182 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
183 /// on a G_CONSTANT returns its APInt value and def register.
186  const MachineRegisterInfo &MRI,
187  bool LookThroughInstrs = true);
188 
189 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
190 /// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
192  Register VReg, const MachineRegisterInfo &MRI,
193  bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
194 
198 };
199 
200 /// If \p VReg is defined by a statically evaluable chain of instructions rooted
201 /// on a G_FCONSTANT returns its APFloat value and def register.
204  const MachineRegisterInfo &MRI,
205  bool LookThroughInstrs = true);
206 
208  const MachineRegisterInfo &MRI);
209 
210 /// See if Reg is defined by an single def instruction that is
211 /// Opcode. Also try to do trivial folding if it's a COPY with
212 /// same types. Returns null otherwise.
213 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
214  const MachineRegisterInfo &MRI);
215 
216 /// Simple struct used to hold a Register value and the instruction which
217 /// defines it.
221 };
222 
223 /// Find the def instruction for \p Reg, and underlying value Register folding
224 /// away any copies.
225 ///
226 /// Also walks through hints such as G_ASSERT_ZEXT.
229 
230 /// Find the def instruction for \p Reg, folding away any trivial copies. May
231 /// return nullptr if \p Reg is not a generic virtual register.
232 ///
233 /// Also walks through hints such as G_ASSERT_ZEXT.
235  const MachineRegisterInfo &MRI);
236 
237 /// Find the source register for \p Reg, folding away any trivial copies. It
238 /// will be an output register of the instruction that getDefIgnoringCopies
239 /// returns. May return an invalid register if \p Reg is not a generic virtual
240 /// register.
241 ///
242 /// Also walks through hints such as G_ASSERT_ZEXT.
244 
245 // Templated variant of getOpcodeDef returning a MachineInstr derived T.
246 /// See if Reg is defined by an single def instruction of type T
247 /// Also try to do trivial folding if it's a COPY with
248 /// same types. Returns null otherwise.
249 template <class T>
252  return dyn_cast_or_null<T>(DefMI);
253 }
254 
255 /// Returns an APFloat from Val converted to the appropriate size.
256 APFloat getAPFloatFromSize(double Val, unsigned Size);
257 
258 /// Modify analysis usage so it preserves passes required for the SelectionDAG
259 /// fallback.
260 void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
261 
262 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
263  const Register Op2,
264  const MachineRegisterInfo &MRI);
265 Optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
266  const Register Op2,
267  const MachineRegisterInfo &MRI);
268 
269 /// Tries to constant fold a vector binop with sources \p Op1 and \p Op2.
270 /// If successful, returns the G_BUILD_VECTOR representing the folded vector
271 /// constant. \p MIB should have an insertion point already set to create new
272 /// G_CONSTANT instructions as needed.
273 Optional<MachineInstr *>
274 ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2,
275  const MachineRegisterInfo &MRI, MachineIRBuilder &MIB);
276 
277 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
278  uint64_t Imm, const MachineRegisterInfo &MRI);
279 
280 Optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
281  Register Src,
282  const MachineRegisterInfo &MRI);
283 
284 /// Tries to constant fold a G_CTLZ operation on \p Src. If \p Src is a vector
285 /// then it tries to do an element-wise constant fold.
286 Optional<SmallVector<unsigned>>
287 ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI);
288 
289 /// Test if the given value is known to have exactly one bit set. This differs
290 /// from computeKnownBits in that it doesn't necessarily determine which bit is
291 /// set.
292 bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
293  GISelKnownBits *KnownBits = nullptr);
294 
295 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
296 /// this returns if \p Val can be assumed to never be a signaling NaN.
297 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
298  bool SNaN = false);
299 
300 /// Returns true if \p Val can be assumed to never be a signaling NaN.
302  return isKnownNeverNaN(Val, MRI, true);
303 }
304 
305 Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
306 
307 /// Return a virtual register corresponding to the incoming argument register \p
308 /// PhysReg. This register is expected to have class \p RC, and optional type \p
309 /// RegTy. This assumes all references to the register will use the same type.
310 ///
311 /// If there is an existing live-in argument register, it will be returned.
312 /// This will also ensure there is a valid copy
313 Register getFunctionLiveInPhysReg(MachineFunction &MF,
314  const TargetInstrInfo &TII,
315  MCRegister PhysReg,
316  const TargetRegisterClass &RC,
317  const DebugLoc &DL, LLT RegTy = LLT());
318 
319 /// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
320 /// number of vector elements or scalar bitwidth. The intent is a
321 /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
322 /// \p OrigTy elements, and unmerged into \p TargetTy
324 LLT getLCMType(LLT OrigTy, LLT TargetTy);
325 
327 /// Return smallest type that covers both \p OrigTy and \p TargetTy and is
328 /// multiple of TargetTy.
329 LLT getCoverTy(LLT OrigTy, LLT TargetTy);
330 
331 /// Return a type where the total size is the greatest common divisor of \p
332 /// OrigTy and \p TargetTy. This will try to either change the number of vector
333 /// elements, or bitwidth of scalars. The intent is the result type can be used
334 /// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
335 /// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
336 /// with intermediate casts) can re-form \p TargetTy.
337 ///
338 /// If these are vectors with different element types, this will try to produce
339 /// a vector with a compatible total size, but the element type of \p OrigTy. If
340 /// this can't be satisfied, this will produce a scalar smaller than the
341 /// original vector elements.
342 ///
343 /// In the worst case, this returns LLT::scalar(1)
345 LLT getGCDType(LLT OrigTy, LLT TargetTy);
346 
347 /// Represents a value which can be a Register or a constant.
348 ///
349 /// This is useful in situations where an instruction may have an interesting
350 /// register operand or interesting constant operand. For a concrete example,
351 /// \see getVectorSplat.
353  int64_t Cst;
354  Register Reg;
355  bool IsReg;
356 
357 public:
358  explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
359  explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
360  bool isReg() const { return IsReg; }
361  bool isCst() const { return !IsReg; }
362  Register getReg() const {
363  assert(isReg() && "Expected a register!");
364  return Reg;
365  }
366  int64_t getCst() const {
367  assert(isCst() && "Expected a constant!");
368  return Cst;
369  }
370 };
371 
372 /// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
373 /// If \p MI is not a splat, returns None.
374 Optional<int> getSplatIndex(MachineInstr &MI);
375 
376 /// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
377 Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
378  const MachineRegisterInfo &MRI);
379 
380 /// Returns a floating point scalar constant of a build vector splat if it
381 /// exists. When \p AllowUndef == true some elements can be undef but not all.
382 Optional<FPValueAndVReg> getFConstantSplat(Register VReg,
383  const MachineRegisterInfo &MRI,
384  bool AllowUndef = true);
385 
386 /// Return true if the specified register is defined by G_BUILD_VECTOR or
387 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
388 bool isBuildVectorConstantSplat(const Register Reg,
389  const MachineRegisterInfo &MRI,
390  int64_t SplatValue, bool AllowUndef);
391 
392 /// Return true if the specified instruction is a G_BUILD_VECTOR or
393 /// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
394 bool isBuildVectorConstantSplat(const MachineInstr &MI,
395  const MachineRegisterInfo &MRI,
396  int64_t SplatValue, bool AllowUndef);
397 
398 /// Return true if the specified instruction is a G_BUILD_VECTOR or
399 /// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
400 bool isBuildVectorAllZeros(const MachineInstr &MI,
401  const MachineRegisterInfo &MRI,
402  bool AllowUndef = false);
403 
404 /// Return true if the specified instruction is a G_BUILD_VECTOR or
405 /// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
406 bool isBuildVectorAllOnes(const MachineInstr &MI,
407  const MachineRegisterInfo &MRI,
408  bool AllowUndef = false);
409 
410 /// \returns a value when \p MI is a vector splat. The splat can be either a
411 /// Register or a constant.
412 ///
413 /// Examples:
414 ///
415 /// \code
416 /// %reg = COPY $physreg
417 /// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
418 /// \endcode
419 ///
420 /// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
421 /// containing %reg.
422 ///
423 /// \code
424 /// %cst = G_CONSTANT iN 4
425 /// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
426 /// \endcode
427 ///
428 /// In the above case, this will return a RegOrConstant containing 4.
429 Optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
430  const MachineRegisterInfo &MRI);
431 
432 /// Determines if \p MI defines a constant integer or a build vector of
433 /// constant integers. Treats undef values as constants.
434 bool isConstantOrConstantVector(MachineInstr &MI,
435  const MachineRegisterInfo &MRI);
436 
437 /// Determines if \p MI defines a constant integer or a splat vector of
438 /// constant integers.
439 /// \returns the scalar constant or None.
440 Optional<APInt> isConstantOrConstantSplatVector(MachineInstr &MI,
441  const MachineRegisterInfo &MRI);
442 
443 /// Attempt to match a unary predicate against a scalar/splat constant or every
444 /// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
445 /// value was undef.
446 bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
447  std::function<bool(const Constant *ConstVal)> Match,
448  bool AllowUndefs = false);
449 
450 /// Returns true if given the TargetLowering's boolean contents information,
451 /// the value \p Val contains a true value.
452 bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
453  bool IsFP);
454 
455 /// Returns an integer representing true, as defined by the
456 /// TargetBooleanContents.
457 int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
458 
459 /// Returns true if the given block should be optimized for size.
460 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
461  BlockFrequencyInfo *BFI);
462 
465  LostDebugLocObserver *LocObserver,
466  SmallInstListTy &DeadInstChain);
468  LostDebugLocObserver *LocObserver = nullptr);
470  LostDebugLocObserver *LocObserver = nullptr);
471 
472 } // End namespace llvm.
473 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::lltok::APFloat
@ APFloat
Definition: LLToken.h:497
llvm::getIConstantVRegSExtVal
Optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:292
llvm::saveUsesAndErase
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1201
llvm::getDefIgnoringCopies
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:453
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::LostDebugLocObserver
Definition: LostDebugLocObserver.h:19
llvm::FPValueAndVReg::Value
APFloat Value
Definition: Utils.h:196
llvm::ValueAndVReg
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:177
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::getAPFloatFromSize
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:473
llvm::ISD::ConstantFP
@ ConstantFP
Definition: ISDOpcodes.h:77
StringRef.h
llvm::getOpcodeDef
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:467
llvm::getSrcRegIgnoringCopies
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:460
MachineBasicBlock.h
llvm::RegOrConstant::isCst
bool isCst() const
Definition: Utils.h:361
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
llvm::shouldOptForSize
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1194
llvm::eraseInstrs
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1215
llvm::ConstantFoldFPBinOp
Optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:541
llvm::RegOrConstant::getCst
int64_t getCst() const
Definition: Utils.h:366
llvm::Optional
Definition: APInt.h:33
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::getSelectionDAGFallbackAnalysisUsage
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:869
llvm::reportGISelWarning
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:254
llvm::RegOrConstant
Represents a value which can be a Register or a constant.
Definition: Utils.h:352
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::ValueAndVReg::Value
APInt Value
Definition: Utils.h:178
llvm::constrainSelectedInstRegOperands
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:144
llvm::getICmpTrueVal
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1182
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:207
llvm::ValueAndVReg::VReg
Register VReg
Definition: Utils.h:179
llvm::getFunctionLiveInPhysReg
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:703
llvm::getGCDType
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:940
llvm::RegOrConstant::getReg
Register getReg() const
Definition: Utils.h:362
LostDebugLocObserver.h
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::ConstantFoldExtOp
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:736
llvm::ConstantFP
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:257
APFloat.h
This file declares a class to represent arbitrary precision floating point values and provide a varie...
llvm::ConstantFoldIntToFloat
Optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:753
llvm::isConstantOrConstantSplatVector
Optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1125
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
Register
Promote Memory to Register
Definition: Mem2Reg.cpp:110
llvm::FPValueAndVReg::VReg
Register VReg
Definition: Utils.h:197
llvm::RegOrConstant::isReg
bool isReg() const
Definition: Utils.h:360
LowLevelTypeImpl.h
llvm::matchUnaryPredicate
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1137
llvm::getLCMType
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:879
llvm::isConstantOrConstantVector
bool isConstantOrConstantVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a build vector of constant integers.
Definition: Utils.cpp:1107
llvm::APFloat
Definition: APFloat.h:701
llvm::FPValueAndVReg
Definition: Utils.h:195
llvm::eraseInstr
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1230
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::isConstTrueVal
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1169
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:686
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::getCoverTy
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:925
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:83
llvm::getIConstantVRegVal
Optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:280
llvm::isTriviallyDead
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:204
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::getAnyConstantVRegValWithLookThrough
Optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:407
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::constrainRegToClass
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:40
llvm::getIConstantVRegValWithLookThrough
Optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:401
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:431
llvm::ConstantFoldVectorBinop
Optional< MachineInstr * > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI, MachineIRBuilder &MIB)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:596
llvm::isKnownNeverNaN
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Definition: ValueTracking.cpp:3760
MORE
#define MORE()
Definition: regcomp.c:252
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
GISelWorkList.h
llvm::ConstantFoldCTLZ
Optional< SmallVector< unsigned > > ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI)
Tries to constant fold a G_CTLZ operation on Src.
Definition: Utils.cpp:767
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1087
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:209
Alignment.h
llvm::getBuildVectorConstantSplat
Optional< int64_t > getBuildVectorConstantSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
Definition: Utils.cpp:1065
llvm::DefinitionAndSourceRegister
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:218
llvm::canReplaceReg
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:190
llvm::isKnownNeverSNaN
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:301
llvm::getVectorSplat
Optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1093
llvm::getFConstantVRegValWithLookThrough
Optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:415
llvm::RegOrConstant::RegOrConstant
RegOrConstant(int64_t Cst)
Definition: Utils.h:359
llvm::reportGISelFailure
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:260
llvm::getSplatIndex
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
Definition: VectorUtils.cpp:344
llvm::GISelWorkList
Definition: GISelWorkList.h:27
llvm::getFConstantSplat
Optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1073
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:50
llvm::isBuildVectorConstantSplat
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1049
llvm::getConstantFPVRegVal
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:426
Register.h
llvm::isKnownToBeAPowerOfTwo
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
Definition: ValueTracking.cpp:303
llvm::RegOrConstant::RegOrConstant
RegOrConstant(Register Reg)
Definition: Utils.h:358
llvm::DefinitionAndSourceRegister::Reg
Register Reg
Definition: Utils.h:220
llvm::DefinitionAndSourceRegister::MI
MachineInstr * MI
Definition: Utils.h:219
llvm::getDefSrcRegIgnoringCopies
Optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:434
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:670
llvm::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1081
llvm::ConstantFoldBinOp
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:486