LLVM 19.0.0git
Utils.h
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1//==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file declares the API of helper functions used throughout the
10/// GlobalISel pipeline.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15#define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16
17#include "GISelWorkList.h"
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/StringRef.h"
22#include "llvm/IR/DebugLoc.h"
25#include <cstdint>
26
27namespace llvm {
28
29class AnalysisUsage;
30class LostDebugLocObserver;
31class MachineBasicBlock;
32class BlockFrequencyInfo;
33class GISelKnownBits;
34class MachineFunction;
35class MachineInstr;
36class MachineIRBuilder;
37class MachineOperand;
38class MachineOptimizationRemarkEmitter;
39class MachineOptimizationRemarkMissed;
40struct MachinePointerInfo;
41class MachineRegisterInfo;
42class MCInstrDesc;
43class ProfileSummaryInfo;
44class RegisterBankInfo;
45class TargetInstrInfo;
46class TargetLowering;
47class TargetPassConfig;
48class TargetRegisterInfo;
49class TargetRegisterClass;
50class ConstantFP;
51class APFloat;
52
53// Convenience macros for dealing with vector reduction opcodes.
54#define GISEL_VECREDUCE_CASES_ALL \
55 case TargetOpcode::G_VECREDUCE_SEQ_FADD: \
56 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: \
57 case TargetOpcode::G_VECREDUCE_FADD: \
58 case TargetOpcode::G_VECREDUCE_FMUL: \
59 case TargetOpcode::G_VECREDUCE_FMAX: \
60 case TargetOpcode::G_VECREDUCE_FMIN: \
61 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
62 case TargetOpcode::G_VECREDUCE_FMINIMUM: \
63 case TargetOpcode::G_VECREDUCE_ADD: \
64 case TargetOpcode::G_VECREDUCE_MUL: \
65 case TargetOpcode::G_VECREDUCE_AND: \
66 case TargetOpcode::G_VECREDUCE_OR: \
67 case TargetOpcode::G_VECREDUCE_XOR: \
68 case TargetOpcode::G_VECREDUCE_SMAX: \
69 case TargetOpcode::G_VECREDUCE_SMIN: \
70 case TargetOpcode::G_VECREDUCE_UMAX: \
71 case TargetOpcode::G_VECREDUCE_UMIN:
72
73#define GISEL_VECREDUCE_CASES_NONSEQ \
74 case TargetOpcode::G_VECREDUCE_FADD: \
75 case TargetOpcode::G_VECREDUCE_FMUL: \
76 case TargetOpcode::G_VECREDUCE_FMAX: \
77 case TargetOpcode::G_VECREDUCE_FMIN: \
78 case TargetOpcode::G_VECREDUCE_FMAXIMUM: \
79 case TargetOpcode::G_VECREDUCE_FMINIMUM: \
80 case TargetOpcode::G_VECREDUCE_ADD: \
81 case TargetOpcode::G_VECREDUCE_MUL: \
82 case TargetOpcode::G_VECREDUCE_AND: \
83 case TargetOpcode::G_VECREDUCE_OR: \
84 case TargetOpcode::G_VECREDUCE_XOR: \
85 case TargetOpcode::G_VECREDUCE_SMAX: \
86 case TargetOpcode::G_VECREDUCE_SMIN: \
87 case TargetOpcode::G_VECREDUCE_UMAX: \
88 case TargetOpcode::G_VECREDUCE_UMIN:
89
90/// Try to constrain Reg to the specified register class. If this fails,
91/// create a new virtual register in the correct class.
92///
93/// \return The virtual register constrained to the right register class.
94Register constrainRegToClass(MachineRegisterInfo &MRI,
95 const TargetInstrInfo &TII,
96 const RegisterBankInfo &RBI, Register Reg,
97 const TargetRegisterClass &RegClass);
98
99/// Constrain the Register operand OpIdx, so that it is now constrained to the
100/// TargetRegisterClass passed as an argument (RegClass).
101/// If this fails, create a new virtual register in the correct class and insert
102/// a COPY before \p InsertPt if it is a use or after if it is a definition.
103/// In both cases, the function also updates the register of RegMo. The debug
104/// location of \p InsertPt is used for the new copy.
105///
106/// \return The virtual register constrained to the right register class.
107Register constrainOperandRegClass(const MachineFunction &MF,
108 const TargetRegisterInfo &TRI,
109 MachineRegisterInfo &MRI,
110 const TargetInstrInfo &TII,
111 const RegisterBankInfo &RBI,
112 MachineInstr &InsertPt,
113 const TargetRegisterClass &RegClass,
114 MachineOperand &RegMO);
115
116/// Try to constrain Reg so that it is usable by argument OpIdx of the provided
117/// MCInstrDesc \p II. If this fails, create a new virtual register in the
118/// correct class and insert a COPY before \p InsertPt if it is a use or after
119/// if it is a definition. In both cases, the function also updates the register
120/// of RegMo.
121/// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
122/// with RegClass obtained from the MCInstrDesc. The debug location of \p
123/// InsertPt is used for the new copy.
124///
125/// \return The virtual register constrained to the right register class.
126Register constrainOperandRegClass(const MachineFunction &MF,
127 const TargetRegisterInfo &TRI,
128 MachineRegisterInfo &MRI,
129 const TargetInstrInfo &TII,
130 const RegisterBankInfo &RBI,
131 MachineInstr &InsertPt, const MCInstrDesc &II,
132 MachineOperand &RegMO, unsigned OpIdx);
133
134/// Mutate the newly-selected instruction \p I to constrain its (possibly
135/// generic) virtual register operands to the instruction's register class.
136/// This could involve inserting COPYs before (for uses) or after (for defs).
137/// This requires the number of operands to match the instruction description.
138/// \returns whether operand regclass constraining succeeded.
139///
140// FIXME: Not all instructions have the same number of operands. We should
141// probably expose a constrain helper per operand and let the target selector
142// constrain individual registers, like fast-isel.
143bool constrainSelectedInstRegOperands(MachineInstr &I,
144 const TargetInstrInfo &TII,
145 const TargetRegisterInfo &TRI,
146 const RegisterBankInfo &RBI);
147
148/// Check if DstReg can be replaced with SrcReg depending on the register
149/// constraints.
150bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
151
152/// Check whether an instruction \p MI is dead: it only defines dead virtual
153/// registers, and doesn't have other side effects.
154bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
155
156/// Report an ISel error as a missed optimization remark to the LLVMContext's
157/// diagnostic stream. Set the FailedISel MachineFunction property.
158void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
159 MachineOptimizationRemarkEmitter &MORE,
160 MachineOptimizationRemarkMissed &R);
161
162void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
163 MachineOptimizationRemarkEmitter &MORE,
164 const char *PassName, StringRef Msg,
165 const MachineInstr &MI);
166
167/// Report an ISel warning as a missed optimization remark to the LLVMContext's
168/// diagnostic stream.
169void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
170 MachineOptimizationRemarkEmitter &MORE,
171 MachineOptimizationRemarkMissed &R);
172
173/// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
174std::optional<APInt> getIConstantVRegVal(Register VReg,
175 const MachineRegisterInfo &MRI);
176
177/// If \p VReg is defined by a G_CONSTANT fits in int64_t returns it.
178std::optional<int64_t> getIConstantVRegSExtVal(Register VReg,
179 const MachineRegisterInfo &MRI);
180
181/// Simple struct used to hold a constant integer value and a virtual
182/// register.
186};
187
188/// If \p VReg is defined by a statically evaluable chain of instructions rooted
189/// on a G_CONSTANT returns its APInt value and def register.
190std::optional<ValueAndVReg>
193 bool LookThroughInstrs = true);
194
195/// If \p VReg is defined by a statically evaluable chain of instructions rooted
196/// on a G_CONSTANT or G_FCONSTANT returns its value as APInt and def register.
197std::optional<ValueAndVReg> getAnyConstantVRegValWithLookThrough(
198 Register VReg, const MachineRegisterInfo &MRI,
199 bool LookThroughInstrs = true, bool LookThroughAnyExt = false);
200
204};
205
206/// If \p VReg is defined by a statically evaluable chain of instructions rooted
207/// on a G_FCONSTANT returns its APFloat value and def register.
208std::optional<FPValueAndVReg>
211 bool LookThroughInstrs = true);
212
214 const MachineRegisterInfo &MRI);
215
216/// See if Reg is defined by an single def instruction that is
217/// Opcode. Also try to do trivial folding if it's a COPY with
218/// same types. Returns null otherwise.
219MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
220 const MachineRegisterInfo &MRI);
221
222/// Simple struct used to hold a Register value and the instruction which
223/// defines it.
227};
228
229/// Find the def instruction for \p Reg, and underlying value Register folding
230/// away any copies.
231///
232/// Also walks through hints such as G_ASSERT_ZEXT.
233std::optional<DefinitionAndSourceRegister>
235
236/// Find the def instruction for \p Reg, folding away any trivial copies. May
237/// return nullptr if \p Reg is not a generic virtual register.
238///
239/// Also walks through hints such as G_ASSERT_ZEXT.
241 const MachineRegisterInfo &MRI);
242
243/// Find the source register for \p Reg, folding away any trivial copies. It
244/// will be an output register of the instruction that getDefIgnoringCopies
245/// returns. May return an invalid register if \p Reg is not a generic virtual
246/// register.
247///
248/// Also walks through hints such as G_ASSERT_ZEXT.
250
251/// Helper function to split a wide generic register into bitwise blocks with
252/// the given Type (which implies the number of blocks needed). The generic
253/// registers created are appended to Ops, starting at bit 0 of Reg.
254void extractParts(Register Reg, LLT Ty, int NumParts,
257
258/// Version which handles irregular splits.
259bool extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
261 SmallVectorImpl<Register> &LeftoverVRegs,
263
264/// Version which handles irregular sub-vector splits.
265void extractVectorParts(Register Reg, unsigned NumElts,
268
269// Templated variant of getOpcodeDef returning a MachineInstr derived T.
270/// See if Reg is defined by an single def instruction of type T
271/// Also try to do trivial folding if it's a COPY with
272/// same types. Returns null otherwise.
273template <class T>
276 return dyn_cast_or_null<T>(DefMI);
277}
278
279/// Returns an APFloat from Val converted to the appropriate size.
280APFloat getAPFloatFromSize(double Val, unsigned Size);
281
282/// Modify analysis usage so it preserves passes required for the SelectionDAG
283/// fallback.
284void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
285
286std::optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
287 const Register Op2,
288 const MachineRegisterInfo &MRI);
289std::optional<APFloat> ConstantFoldFPBinOp(unsigned Opcode, const Register Op1,
290 const Register Op2,
291 const MachineRegisterInfo &MRI);
292
293/// Tries to constant fold a vector binop with sources \p Op1 and \p Op2.
294/// Returns an empty vector on failure.
295SmallVector<APInt> ConstantFoldVectorBinop(unsigned Opcode, const Register Op1,
296 const Register Op2,
297 const MachineRegisterInfo &MRI);
298
299std::optional<APInt> ConstantFoldCastOp(unsigned Opcode, LLT DstTy,
300 const Register Op0,
301 const MachineRegisterInfo &MRI);
302
303std::optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
304 uint64_t Imm,
305 const MachineRegisterInfo &MRI);
306
307std::optional<APFloat> ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy,
308 Register Src,
309 const MachineRegisterInfo &MRI);
310
311/// Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on \p
312/// Src. If \p Src is a vector then it tries to do an element-wise constant
313/// fold.
314std::optional<SmallVector<unsigned>>
315ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI,
316 std::function<unsigned(APInt)> CB);
317
318std::optional<SmallVector<APInt>>
319ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2,
320 const MachineRegisterInfo &MRI);
321
322/// Test if the given value is known to have exactly one bit set. This differs
323/// from computeKnownBits in that it doesn't necessarily determine which bit is
324/// set.
325bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
326 GISelKnownBits *KnownBits = nullptr);
327
328/// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
329/// this returns if \p Val can be assumed to never be a signaling NaN.
330bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
331 bool SNaN = false);
332
333/// Returns true if \p Val can be assumed to never be a signaling NaN.
335 return isKnownNeverNaN(Val, MRI, true);
336}
337
338Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
339
340/// Return a virtual register corresponding to the incoming argument register \p
341/// PhysReg. This register is expected to have class \p RC, and optional type \p
342/// RegTy. This assumes all references to the register will use the same type.
343///
344/// If there is an existing live-in argument register, it will be returned.
345/// This will also ensure there is a valid copy
346Register getFunctionLiveInPhysReg(MachineFunction &MF,
347 const TargetInstrInfo &TII,
348 MCRegister PhysReg,
349 const TargetRegisterClass &RC,
350 const DebugLoc &DL, LLT RegTy = LLT());
351
352/// Return the least common multiple type of \p OrigTy and \p TargetTy, by
353/// changing the number of vector elements or scalar bitwidth. The intent is a
354/// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
355/// \p OrigTy elements, and unmerged into \p TargetTy. It is an error to call
356/// this function where one argument is a fixed vector and the other is a
357/// scalable vector, since it is illegal to build a G_{MERGE|UNMERGE}_VALUES
358/// between fixed and scalable vectors.
360LLT getLCMType(LLT OrigTy, LLT TargetTy);
361
363/// Return smallest type that covers both \p OrigTy and \p TargetTy and is
364/// multiple of TargetTy.
365LLT getCoverTy(LLT OrigTy, LLT TargetTy);
366
367/// Return a type where the total size is the greatest common divisor of \p
368/// OrigTy and \p TargetTy. This will try to either change the number of vector
369/// elements, or bitwidth of scalars. The intent is the result type can be used
370/// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
371/// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
372/// with intermediate casts) can re-form \p TargetTy.
373///
374/// If these are vectors with different element types, this will try to produce
375/// a vector with a compatible total size, but the element type of \p OrigTy. If
376/// this can't be satisfied, this will produce a scalar smaller than the
377/// original vector elements. It is an error to call this function where
378/// one argument is a fixed vector and the other is a scalable vector, since it
379/// is illegal to build a G_{MERGE|UNMERGE}_VALUES between fixed and scalable
380/// vectors.
381///
382/// In the worst case, this returns LLT::scalar(1)
384LLT getGCDType(LLT OrigTy, LLT TargetTy);
385
386/// Represents a value which can be a Register or a constant.
387///
388/// This is useful in situations where an instruction may have an interesting
389/// register operand or interesting constant operand. For a concrete example,
390/// \see getVectorSplat.
392 int64_t Cst;
393 Register Reg;
394 bool IsReg;
395
396public:
397 explicit RegOrConstant(Register Reg) : Reg(Reg), IsReg(true) {}
398 explicit RegOrConstant(int64_t Cst) : Cst(Cst), IsReg(false) {}
399 bool isReg() const { return IsReg; }
400 bool isCst() const { return !IsReg; }
401 Register getReg() const {
402 assert(isReg() && "Expected a register!");
403 return Reg;
404 }
405 int64_t getCst() const {
406 assert(isCst() && "Expected a constant!");
407 return Cst;
408 }
409};
410
411/// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
412/// If \p MI is not a splat, returns std::nullopt.
413std::optional<int> getSplatIndex(MachineInstr &MI);
414
415/// \returns the scalar integral splat value of \p Reg if possible.
416std::optional<APInt> getIConstantSplatVal(const Register Reg,
417 const MachineRegisterInfo &MRI);
418
419/// \returns the scalar integral splat value defined by \p MI if possible.
420std::optional<APInt> getIConstantSplatVal(const MachineInstr &MI,
421 const MachineRegisterInfo &MRI);
422
423/// \returns the scalar sign extended integral splat value of \p Reg if
424/// possible.
425std::optional<int64_t> getIConstantSplatSExtVal(const Register Reg,
426 const MachineRegisterInfo &MRI);
427
428/// \returns the scalar sign extended integral splat value defined by \p MI if
429/// possible.
430std::optional<int64_t> getIConstantSplatSExtVal(const MachineInstr &MI,
431 const MachineRegisterInfo &MRI);
432
433/// Returns a floating point scalar constant of a build vector splat if it
434/// exists. When \p AllowUndef == true some elements can be undef but not all.
435std::optional<FPValueAndVReg> getFConstantSplat(Register VReg,
436 const MachineRegisterInfo &MRI,
437 bool AllowUndef = true);
438
439/// Return true if the specified register is defined by G_BUILD_VECTOR or
440/// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
441bool isBuildVectorConstantSplat(const Register Reg,
442 const MachineRegisterInfo &MRI,
443 int64_t SplatValue, bool AllowUndef);
444
445/// Return true if the specified instruction is a G_BUILD_VECTOR or
446/// G_BUILD_VECTOR_TRUNC where all of the elements are \p SplatValue or undef.
447bool isBuildVectorConstantSplat(const MachineInstr &MI,
448 const MachineRegisterInfo &MRI,
449 int64_t SplatValue, bool AllowUndef);
450
451/// Return true if the specified instruction is a G_BUILD_VECTOR or
452/// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
453bool isBuildVectorAllZeros(const MachineInstr &MI,
454 const MachineRegisterInfo &MRI,
455 bool AllowUndef = false);
456
457/// Return true if the specified instruction is a G_BUILD_VECTOR or
458/// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
459bool isBuildVectorAllOnes(const MachineInstr &MI,
460 const MachineRegisterInfo &MRI,
461 bool AllowUndef = false);
462
463/// Return true if the specified instruction is known to be a constant, or a
464/// vector of constants.
465///
466/// If \p AllowFP is true, this will consider G_FCONSTANT in addition to
467/// G_CONSTANT. If \p AllowOpaqueConstants is true, constant-like instructions
468/// such as G_GLOBAL_VALUE will also be considered.
469bool isConstantOrConstantVector(const MachineInstr &MI,
470 const MachineRegisterInfo &MRI,
471 bool AllowFP = true,
472 bool AllowOpaqueConstants = true);
473
474/// Return true if the value is a constant 0 integer or a splatted vector of a
475/// constant 0 integer (with no undefs if \p AllowUndefs is false). This will
476/// handle G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC as truncation is not an issue
477/// for null values.
478bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI,
479 bool AllowUndefs = false);
480
481/// Return true if the value is a constant -1 integer or a splatted vector of a
482/// constant -1 integer (with no undefs if \p AllowUndefs is false).
483bool isAllOnesOrAllOnesSplat(const MachineInstr &MI,
484 const MachineRegisterInfo &MRI,
485 bool AllowUndefs = false);
486
487/// \returns a value when \p MI is a vector splat. The splat can be either a
488/// Register or a constant.
489///
490/// Examples:
491///
492/// \code
493/// %reg = COPY $physreg
494/// %reg_splat = G_BUILD_VECTOR %reg, %reg, ..., %reg
495/// \endcode
496///
497/// If called on the G_BUILD_VECTOR above, this will return a RegOrConstant
498/// containing %reg.
499///
500/// \code
501/// %cst = G_CONSTANT iN 4
502/// %constant_splat = G_BUILD_VECTOR %cst, %cst, ..., %cst
503/// \endcode
504///
505/// In the above case, this will return a RegOrConstant containing 4.
506std::optional<RegOrConstant> getVectorSplat(const MachineInstr &MI,
507 const MachineRegisterInfo &MRI);
508
509/// Determines if \p MI defines a constant integer or a build vector of
510/// constant integers. Treats undef values as constants.
511bool isConstantOrConstantVector(MachineInstr &MI,
512 const MachineRegisterInfo &MRI);
513
514/// Determines if \p MI defines a constant integer or a splat vector of
515/// constant integers.
516/// \returns the scalar constant or std::nullopt.
517std::optional<APInt>
519 const MachineRegisterInfo &MRI);
520
521/// Attempt to match a unary predicate against a scalar/splat constant or every
522/// element of a constant G_BUILD_VECTOR. If \p ConstVal is null, the source
523/// value was undef.
524bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg,
525 std::function<bool(const Constant *ConstVal)> Match,
526 bool AllowUndefs = false);
527
528/// Returns true if given the TargetLowering's boolean contents information,
529/// the value \p Val contains a true value.
530bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
531 bool IsFP);
532/// \returns true if given the TargetLowering's boolean contents information,
533/// the value \p Val contains a false value.
534bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
535 bool IsFP);
536
537/// Returns an integer representing true, as defined by the
538/// TargetBooleanContents.
539int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
540
541/// Returns true if the given block should be optimized for size.
542bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
543 BlockFrequencyInfo *BFI);
544
547 LostDebugLocObserver *LocObserver,
548 SmallInstListTy &DeadInstChain);
550 LostDebugLocObserver *LocObserver = nullptr);
552 LostDebugLocObserver *LocObserver = nullptr);
553
554/// Assuming the instruction \p MI is going to be deleted, attempt to salvage
555/// debug users of \p MI by writing the effect of \p MI in a DIExpression.
557
558} // End namespace llvm.
559#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file declares a class to represent arbitrary precision floating point values and provide a varie...
basic Basic Alias true
#define LLVM_READNONE
Definition: Compiler.h:220
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
Implement a low-level type suitable for MachineInstr level instruction selection.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Promote Memory to Register
Definition: Mem2Reg.cpp:110
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const char PassName[]
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:268
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a value which can be a Register or a constant.
Definition: Utils.h:391
RegOrConstant(Register Reg)
Definition: Utils.h:397
Register getReg() const
Definition: Utils.h:401
bool isCst() const
Definition: Utils.h:400
int64_t getCst() const
Definition: Utils.h:405
RegOrConstant(int64_t Cst)
Definition: Utils.h:398
bool isReg() const
Definition: Utils.h:399
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
@ ConstantFP
Definition: ISDOpcodes.h:77
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII, MCRegister PhysReg, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy=LLT())
Return a virtual register corresponding to the incoming argument register PhysReg.
Definition: Utils.cpp:882
bool isBuildVectorAllZeros(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1412
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:54
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:625
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:438
std::optional< APInt > getIConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT, return the corresponding value.
Definition: Utils.cpp:293
std::optional< APFloat > ConstantFoldIntToFloat(unsigned Opcode, LLT DstTy, Register Src, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:956
std::optional< APInt > getIConstantSplatVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1372
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
Definition: Utils.cpp:1525
std::optional< APFloat > ConstantFoldFPBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:713
void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI)
Assuming the instruction MI is going to be deleted, attempt to salvage debug users of MI by writing t...
Definition: Utils.cpp:1650
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:153
std::optional< SmallVector< unsigned > > ConstantFoldCountZeros(Register Src, const MachineRegisterInfo &MRI, std::function< unsigned(APInt)> CB)
Tries to constant fold a counting-zero operation (G_CTLZ or G_CTTZ) on Src.
Definition: Utils.cpp:969
std::optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:915
std::optional< RegOrConstant > getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1425
bool isKnownToBeAPowerOfTwo(const Value *V, const DataLayout &DL, bool OrZero=false, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return true if the given value is known to have exactly one bit set when defined.
std::optional< APInt > isConstantOrConstantSplatVector(MachineInstr &MI, const MachineRegisterInfo &MRI)
Determines if MI defines a constant integer or a splat vector of constant integers.
Definition: Utils.cpp:1495
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
Definition: Utils.cpp:1507
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:465
bool matchUnaryPredicate(const MachineRegisterInfo &MRI, Register Reg, std::function< bool(const Constant *ConstVal)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant G_B...
Definition: Utils.cpp:1540
bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Returns true if given the TargetLowering's boolean contents information, the value Val contains a tru...
Definition: Utils.cpp:1572
LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy)
Return the least common multiple type of OrigTy and TargetTy, by changing the number of vector elemen...
Definition: Utils.cpp:1144
std::optional< int64_t > getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:305
std::optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:644
bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
Returns true if the given block should be optimized for size.
Definition: Utils.cpp:1609
bool isConstantOrConstantVector(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowFP=true, bool AllowOpaqueConstants=true)
Return true if the specified instruction is known to be a constant, or a vector of constants.
Definition: Utils.cpp:1475
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:199
void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain)
Definition: Utils.cpp:1616
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:273
std::optional< SmallVector< APInt > > ConstantFoldICmp(unsigned Pred, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1001
std::optional< ValueAndVReg > getAnyConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool LookThroughAnyExt=false)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT or G_FCONST...
Definition: Utils.cpp:419
bool isBuildVectorAllOnes(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndef=false)
Return true if the specified instruction is a G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all of the...
Definition: Utils.cpp:1418
SmallVector< APInt > ConstantFoldVectorBinop(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Tries to constant fold a vector binop with sources Op1 and Op2.
Definition: Utils.cpp:767
std::optional< FPValueAndVReg > getFConstantSplat(Register VReg, const MachineRegisterInfo &MRI, bool AllowUndef=true)
Returns a floating point scalar constant of a build vector splat if it exists.
Definition: Utils.cpp:1405
std::optional< APInt > ConstantFoldCastOp(unsigned Opcode, LLT DstTy, const Register Op0, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:932
void extractParts(Register Reg, LLT Ty, int NumParts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Helper function to split a wide generic register into bitwise blocks with the given Type (which impli...
Definition: Utils.cpp:479
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:1140
LLVM_READNONE LLT getCoverTy(LLT OrigTy, LLT TargetTy)
Return smallest type that covers both OrigTy and TargetTy and is multiple of TargetTy.
Definition: Utils.cpp:1211
std::optional< FPValueAndVReg > getFConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_FCONSTANT returns it...
Definition: Utils.cpp:427
bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, bool IsFP)
Definition: Utils.cpp:1585
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:631
bool isBuildVectorConstantSplat(const Register Reg, const MachineRegisterInfo &MRI, int64_t SplatValue, bool AllowUndef)
Return true if the specified register is defined by G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC where all ...
Definition: Utils.cpp:1356
void eraseInstr(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1645
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:44
int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP)
Returns an integer representing true, as defined by the TargetBooleanContents.
Definition: Utils.cpp:1597
std::optional< ValueAndVReg > getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_CONSTANT returns its...
Definition: Utils.cpp:413
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:334
std::optional< DefinitionAndSourceRegister > getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, and underlying value Register folding away any copies.
Definition: Utils.cpp:446
void eraseInstrs(ArrayRef< MachineInstr * > DeadInstrs, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver=nullptr)
Definition: Utils.cpp:1630
bool isKnownNeverNaN(const Value *V, unsigned Depth, const SimplifyQuery &SQ)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:472
LLVM_READNONE LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type where the total size is the greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:1232
std::optional< int64_t > getIConstantSplatSExtVal(const Register Reg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:1390
void extractVectorParts(Register Reg, unsigned NumElts, SmallVectorImpl< Register > &VRegs, MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Version which handles irregular sub-vector splits.
Definition: Utils.cpp:583
int getSplatIndex(ArrayRef< int > Mask)
If all non-negative Mask elements are the same value, return that value.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn't have oth...
Definition: Utils.cpp:220
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:865
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext's diagnostic stream.
Definition: Utils.cpp:267
#define MORE()
Definition: regcomp.c:252
Simple struct used to hold a Register value and the instruction which defines it.
Definition: Utils.h:224
Register VReg
Definition: Utils.h:203
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:183
Register VReg
Definition: Utils.h:185