LLVM  11.0.0git
Utils.h
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1 //==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file declares the API of helper functions used throughout the
10 /// GlobalISel pipeline.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
15 #define LLVM_CODEGEN_GLOBALISEL_UTILS_H
16 
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/Support/Alignment.h"
22 
23 namespace llvm {
24 
25 class AnalysisUsage;
26 class MachineFunction;
27 class MachineInstr;
28 class MachineOperand;
29 class MachineOptimizationRemarkEmitter;
30 class MachineOptimizationRemarkMissed;
31 struct MachinePointerInfo;
32 class MachineRegisterInfo;
33 class MCInstrDesc;
34 class RegisterBankInfo;
35 class TargetInstrInfo;
36 class TargetPassConfig;
37 class TargetRegisterInfo;
38 class TargetRegisterClass;
39 class Twine;
40 class ConstantFP;
41 class APFloat;
42 
43 /// Try to constrain Reg to the specified register class. If this fails,
44 /// create a new virtual register in the correct class.
45 ///
46 /// \return The virtual register constrained to the right register class.
47 Register constrainRegToClass(MachineRegisterInfo &MRI,
48  const TargetInstrInfo &TII,
49  const RegisterBankInfo &RBI, Register Reg,
50  const TargetRegisterClass &RegClass);
51 
52 /// Constrain the Register operand OpIdx, so that it is now constrained to the
53 /// TargetRegisterClass passed as an argument (RegClass).
54 /// If this fails, create a new virtual register in the correct class and
55 /// insert a COPY before \p InsertPt if it is a use or after if it is a
56 /// definition. The debug location of \p InsertPt is used for the new copy.
57 ///
58 /// \return The virtual register constrained to the right register class.
59 Register constrainOperandRegClass(const MachineFunction &MF,
60  const TargetRegisterInfo &TRI,
61  MachineRegisterInfo &MRI,
62  const TargetInstrInfo &TII,
63  const RegisterBankInfo &RBI,
64  MachineInstr &InsertPt,
65  const TargetRegisterClass &RegClass,
66  const MachineOperand &RegMO);
67 
68 /// Try to constrain Reg so that it is usable by argument OpIdx of the
69 /// provided MCInstrDesc \p II. If this fails, create a new virtual
70 /// register in the correct class and insert a COPY before \p InsertPt
71 /// if it is a use or after if it is a definition.
72 /// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
73 /// with RegClass obtained from the MCInstrDesc. The debug location of \p
74 /// InsertPt is used for the new copy.
75 ///
76 /// \return The virtual register constrained to the right register class.
77 Register constrainOperandRegClass(const MachineFunction &MF,
78  const TargetRegisterInfo &TRI,
79  MachineRegisterInfo &MRI,
80  const TargetInstrInfo &TII,
81  const RegisterBankInfo &RBI,
82  MachineInstr &InsertPt, const MCInstrDesc &II,
83  const MachineOperand &RegMO, unsigned OpIdx);
84 
85 /// Mutate the newly-selected instruction \p I to constrain its (possibly
86 /// generic) virtual register operands to the instruction's register class.
87 /// This could involve inserting COPYs before (for uses) or after (for defs).
88 /// This requires the number of operands to match the instruction description.
89 /// \returns whether operand regclass constraining succeeded.
90 ///
91 // FIXME: Not all instructions have the same number of operands. We should
92 // probably expose a constrain helper per operand and let the target selector
93 // constrain individual registers, like fast-isel.
94 bool constrainSelectedInstRegOperands(MachineInstr &I,
95  const TargetInstrInfo &TII,
96  const TargetRegisterInfo &TRI,
97  const RegisterBankInfo &RBI);
98 
99 /// Check if DstReg can be replaced with SrcReg depending on the register
100 /// constraints.
101 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
102 
103 /// Check whether an instruction \p MI is dead: it only defines dead virtual
104 /// registers, and doesn't have other side effects.
105 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
106 
107 /// Report an ISel error as a missed optimization remark to the LLVMContext's
108 /// diagnostic stream. Set the FailedISel MachineFunction property.
109 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
110  MachineOptimizationRemarkEmitter &MORE,
111  MachineOptimizationRemarkMissed &R);
112 
113 void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
114  MachineOptimizationRemarkEmitter &MORE,
115  const char *PassName, StringRef Msg,
116  const MachineInstr &MI);
117 
118 /// Report an ISel warning as a missed optimization remark to the LLVMContext's
119 /// diagnostic stream.
120 void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
121  MachineOptimizationRemarkEmitter &MORE,
122  MachineOptimizationRemarkMissed &R);
123 
124 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
125 /// returns it.
126 Optional<int64_t> getConstantVRegVal(Register VReg,
127  const MachineRegisterInfo &MRI);
128 /// Simple struct used to hold a constant integer value and a virtual
129 /// register.
130 struct ValueAndVReg {
131  int64_t Value;
133 };
134 /// If \p VReg is defined by a statically evaluable chain of
135 /// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
136 /// and that constant fits in int64_t, returns its value as well as the
137 /// virtual register defined by this G_F/CONSTANT.
138 /// When \p LookThroughInstrs == false this function behaves like
139 /// getConstantVRegVal.
140 /// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
143  bool LookThroughInstrs = true,
144  bool HandleFConstants = true);
146  const MachineRegisterInfo &MRI);
147 
148 /// See if Reg is defined by an single def instruction that is
149 /// Opcode. Also try to do trivial folding if it's a COPY with
150 /// same types. Returns null otherwise.
151 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
152  const MachineRegisterInfo &MRI);
153 
154 /// Find the def instruction for \p Reg, folding away any trivial copies. Note
155 /// it may still return a COPY, if it changes the type. May return nullptr if \p
156 /// Reg is not a generic virtual register.
158  const MachineRegisterInfo &MRI);
159 
160 /// Find the source register for \p Reg, folding away any trivial copies. It
161 /// will be an output register of the instruction that getDefIgnoringCopies
162 /// returns. May return an invalid register if \p Reg is not a generic virtual
163 /// register.
165  const MachineRegisterInfo &MRI);
166 
167 /// Returns an APFloat from Val converted to the appropriate size.
168 APFloat getAPFloatFromSize(double Val, unsigned Size);
169 
170 /// Modify analysis usage so it preserves passes required for the SelectionDAG
171 /// fallback.
173 
174 Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
175  const Register Op2,
176  const MachineRegisterInfo &MRI);
177 
178 Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
179  uint64_t Imm, const MachineRegisterInfo &MRI);
180 
181 /// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
182 /// this returns if \p Val can be assumed to never be a signaling NaN.
184  bool SNaN = false);
185 
186 /// Returns true if \p Val can be assumed to never be a signaling NaN.
188  return isKnownNeverNaN(Val, MRI, true);
189 }
190 
192 
193 /// Return the least common multiple type of \p Ty0 and \p Ty1, by changing
194 /// the number of vector elements or scalar bitwidth. The intent is a
195 /// G_MERGE_VALUES can be constructed from \p Ty0 elements, and unmerged into
196 /// \p Ty1.
197 LLT getLCMType(LLT Ty0, LLT Ty1);
198 
199 /// Return a type that is greatest common divisor of \p OrigTy and \p
200 /// TargetTy. This will either change the number of vector elements, or
201 /// bitwidth of scalars. The intent is the result type can be used as the
202 /// result of a G_UNMERGE_VALUES from \p OrigTy.
203 LLT getGCDType(LLT OrigTy, LLT TargetTy);
204 
205 } // End namespace llvm.
206 #endif
Simple struct used to hold a constant integer value and a virtual register.
Definition: Utils.h:130
Optional< ValueAndVReg > getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs=true, bool HandleFConstants=true)
If VReg is defined by a statically evaluable chain of instructions rooted on a G_F/CONSTANT (LookThro...
Definition: Utils.cpp:256
This class represents lattice values for constants.
Definition: AllocatorList.h:23
void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)
Modify analysis usage so it preserves passes required for the SelectionDAG fallback.
Definition: Utils.cpp:509
unsigned Reg
unsigned const TargetRegisterInfo * TRI
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:41
MachineInstr * getDefIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the def instruction for Reg, folding away any trivial copies.
Definition: Utils.cpp:366
bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI)
Returns true if Val can be assumed to never be a signaling NaN.
Definition: Utils.h:187
int64_t Value
Definition: Utils.h:131
Optional< APInt > ConstantFoldBinOp(unsigned Opcode, const Register Op1, const Register Op2, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:399
const HexagonInstrInfo * TII
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:480
APFloat getAPFloatFromSize(double Val, unsigned Size)
Returns an APFloat from Val converted to the appropriate size.
Definition: Utils.cpp:386
Register constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass)
Try to constrain Reg to the specified register class.
Definition: Utils.cpp:31
Optional< int64_t > getConstantVRegVal(Register VReg, const MachineRegisterInfo &MRI)
If VReg is defined by a G_CONSTANT fits in int64_t returns it.
Definition: Utils.cpp:245
unsigned const MachineRegisterInfo * MRI
ConstantFP - Floating Point Values [float, double].
Definition: Constants.h:261
Represent the analysis usage information of a pass.
LLT getLCMType(LLT Ty0, LLT Ty1)
Return the least common multiple type of Ty0 and Ty1, by changing the number of vector elements or sc...
Definition: Utils.cpp:513
const ConstantFP * getConstantFPVRegVal(Register VReg, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:334
MachineInstr * getOpcodeDef(unsigned Opcode, Register Reg, const MachineRegisterInfo &MRI)
See if Reg is defined by an single def instruction that is Opcode.
Definition: Utils.cpp:380
This class contains a discriminated union of information about pointers in memory operands...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI)
Check if DstReg can be replaced with SrcReg depending on the register constraints.
Definition: Utils.cpp:167
Promote Memory to Register
Definition: Mem2Reg.cpp:110
#define MORE()
Definition: regcomp.c:252
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
Definition: Utils.cpp:120
RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks)
Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI)
Check whether an instruction MI is dead: it only defines dead virtual registers, and doesn&#39;t have oth...
Definition: Utils.cpp:181
Representation of each machine instruction.
Definition: MachineInstr.h:62
#define I(x, y, z)
Definition: MD5.cpp:59
uint32_t Size
Definition: Profile.cpp:46
Register VReg
Definition: Utils.h:132
bool isKnownNeverNaN(const Value *V, const TargetLibraryInfo *TLI, unsigned Depth=0)
Return true if the floating-point scalar value is not a NaN or if the floating-point vector value has...
void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel warning as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:219
IRTranslator LLVM IR MI
Optional< APInt > ConstantFoldExtOp(unsigned Opcode, const Register Op1, uint64_t Imm, const MachineRegisterInfo &MRI)
Definition: Utils.cpp:492
LLT getGCDType(LLT OrigTy, LLT TargetTy)
Return a type that is greatest common divisor of OrigTy and TargetTy.
Definition: Utils.cpp:544
void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, MachineOptimizationRemarkEmitter &MORE, MachineOptimizationRemarkMissed &R)
Report an ISel error as a missed optimization remark to the LLVMContext&#39;s diagnostic stream...
Definition: Utils.cpp:225
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI)
Find the source register for Reg, folding away any trivial copies.
Definition: Utils.cpp:373