LLVM  10.0.0svn
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AMDGPUISelDAGToDAG.cpp File Reference

Defines an instruction selector for the AMDGPU target. More...

#include "AMDGPU.h"
#include "AMDGPUArgumentUsageInfo.h"
#include "AMDGPUISelLowering.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUPerfHintAnalysis.h"
#include "AMDGPURegisterInfo.h"
#include "AMDGPUSubtarget.h"
#include "AMDGPUTargetMachine.h"
#include "SIDefines.h"
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "SIRegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Instruction.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
#include <cstdint>
#include <new>
#include <vector>
#include "AMDGPUGenDAGISel.inc"
#include "R600GenDAGISel.inc"
Include dependency graph for AMDGPUISelDAGToDAG.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 

Macros

#define DEBUG_TYPE   "isel"
 

Functions

 INITIALIZE_PASS_BEGIN (AMDGPUDAGToDAGISel, "amdgpu-isel", "AMDGPU DAG->DAG Pattern Instruction Selection", false, false) INITIALIZE_PASS_END(AMDGPUDAGToDAGISel
 
static unsigned selectSGPRVectorRegClassID (unsigned NumVectorElts)
 
static bool isStackPtrRelative (const MachinePointerInfo &PtrInfo)
 
static MemSDNodefindMemSDNode (SDNode *N)
 
static unsigned gwsIntrinToOpcode (unsigned IntrID)
 

Variables

amdgpu isel
 
amdgpu AMDGPU DAG DAG Pattern Instruction Selection
 
amdgpu AMDGPU DAG DAG Pattern Instruction false
 

Detailed Description

Defines an instruction selector for the AMDGPU target.

Definition in file AMDGPUISelDAGToDAG.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "isel"

Definition at line 57 of file AMDGPUISelDAGToDAG.cpp.

Function Documentation

◆ findMemSDNode()

static MemSDNode* findMemSDNode ( SDNode N)
static

◆ gwsIntrinToOpcode()

static unsigned gwsIntrinToOpcode ( unsigned  IntrID)
static

◆ INITIALIZE_PASS_BEGIN()

INITIALIZE_PASS_BEGIN ( AMDGPUDAGToDAGISel  ,
"amdgpu-isel ,
"AMDGPU DAG->DAG Pattern Instruction Selection ,
false  ,
false   
)

◆ isStackPtrRelative()

static bool isStackPtrRelative ( const MachinePointerInfo PtrInfo)
static

◆ selectSGPRVectorRegClassID()

static unsigned selectSGPRVectorRegClassID ( unsigned  NumVectorElts)
static

Definition at line 636 of file AMDGPUISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::ADDC, llvm::ISD::ADDCARRY, llvm::ISD::ADDE, llvm::ISD::AND, llvm::AMDGPU::HSAMD::Kernel::Key::Args, assert(), llvm::AMDGPUISD::ATOMIC_CMP_SWAP, llvm::AMDGPUISD::ATOMIC_DEC, llvm::AMDGPUISD::ATOMIC_INC, llvm::ISD::ATOMIC_LOAD, llvm::ISD::ATOMIC_LOAD_FADD, llvm::AMDGPUISD::ATOMIC_LOAD_FMAX, llvm::AMDGPUISD::ATOMIC_LOAD_FMIN, llvm::ISD::ATOMIC_STORE, llvm::AMDGPUISD::BFE_I32, llvm::AMDGPUISD::BFE_U32, llvm::EVT::bitsEq(), llvm::ISD::BRCOND, llvm::ISD::BUILD_PAIR, llvm::ISD::BUILD_VECTOR, C, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::ISD::CopyToReg, llvm::AMDGPUISD::CVT_PK_I16_I32, llvm::AMDGPUISD::CVT_PK_U16_U32, llvm::AMDGPUISD::CVT_PKNORM_I16_F32, llvm::AMDGPUISD::CVT_PKNORM_U16_F32, llvm::AMDGPUISD::CVT_PKRTZ_F16_F32, llvm::AMDGPUISD::DIV_FMAS, llvm::AMDGPUISD::DIV_SCALE, llvm::AMDGPUISD::DWORDADDR, llvm::dyn_cast(), llvm::MVT::f32, llvm::MVT::f64, llvm::ISD::FMA, llvm::AMDGPUISD::FMA_W_CHAIN, llvm::ISD::FMAD, llvm::AMDGPUISD::FMUL_W_CHAIN, llvm::Instruction::getMetadata(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::GCNSubtarget::getRegisterInfo(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), llvm::BasicBlock::getTerminator(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::SIRegisterInfo::getVCC(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDNode::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::MVT::i1, llvm::MVT::i128, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::SDNode::isDivergent(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SDNode::isMachineOpcode(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::isUInt< 8 >(), llvm::SITargetLowering::legalizeTargetIndependentNode(), llvm_unreachable, llvm::ISD::LOAD, Lowering, llvm::AMDGPUISD::MAD_I64_I32, llvm::AMDGPUISD::MAD_U64_U32, N, llvm::ISD::OR, llvm::SmallVectorTemplateBase< T >::push_back(), llvm::MCID::RegSequence, llvm::ISD::SCALAR_TO_VECTOR, llvm::MCID::Select, llvm::SDNode::setNodeId(), llvm::ISD::SIGN_EXTEND_INREG, Signed, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::STORE, llvm::ISD::SUB, llvm::ISD::SUBC, llvm::ISD::SUBCARRY, llvm::ISD::SUBE, TRI, llvm::ISD::UADDO, llvm::ISD::USUBO, llvm::MVT::v2f16, llvm::MVT::v2i16, llvm::MVT::v2i32, and llvm::SITargetLowering::wrapAddr64Rsrc().

Variable Documentation

◆ false

amdgpu AMDGPU DAG DAG Pattern Instruction false

Definition at line 366 of file AMDGPUISelDAGToDAG.cpp.

◆ isel

amdgpu isel

Definition at line 366 of file AMDGPUISelDAGToDAG.cpp.

◆ Selection

amdgpu AMDGPU DAG DAG Pattern Instruction Selection