14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELDAGTODAG_H
36 Out =
C->getAPIntValue().getSExtValue();
41 Out =
C->getValueAPF().bitcastToAPInt().getSExtValue();
52 if (getConstantValue(
N->getOperand(0), LHSVal) &&
53 getConstantValue(
N->getOperand(1), RHSVal)) {
55 uint32_t K = (LHSVal & 0xffff) | (RHSVal << 16);
75 bool EnableLateStructurizeCFG;
79 bool fp16SrcZerosHighBits(
unsigned Opc)
const;
96 std::pair<SDValue, SDValue> foldFrameIndex(
SDValue N)
const;
98 bool isInlineImmediate(
const SDNode *
N)
const;
100 bool isInlineImmediate(
const APInt &Imm)
const {
104 bool isInlineImmediate(
const APFloat &Imm)
const {
108 bool isVGPRImm(
const SDNode *
N)
const;
109 bool isUniformLoad(
const SDNode *
N)
const;
110 bool isUniformBr(
const SDNode *
N)
const;
114 bool isUnneededShiftMask(
const SDNode *
N,
unsigned ShAmtBits)
const;
129 bool isDSOffset2Legal(
SDValue Base,
unsigned Offset0,
unsigned Offset1,
130 unsigned Size)
const;
134 bool isFlatScratchBaseLegalSVImm(
SDValue Addr)
const;
135 bool isSOffsetLegalWithImmOffset(
SDValue *SOffset,
bool Imm32Only,
136 bool IsBuffer, int64_t ImmOffset = 0)
const;
179 bool IsBuffer =
false,
bool HasSOffset =
false,
180 int64_t ImmOffset = 0)
const;
184 bool IsBuffer =
false,
bool HasSOffset =
false,
185 int64_t ImmOffset = 0)
const;
201 bool SelectVOP3ModsImpl(
SDValue In,
SDValue &Src,
unsigned &SrcMods,
202 bool IsCanonicalizing =
true,
203 bool AllowAbs =
true)
const;
225 bool IsDOT =
false)
const;
245 unsigned &Mods)
const;
252 SDValue getMaterializedScalarImm32(int64_t Val,
const SDLoc &
DL)
const;
254 void SelectADD_SUB_I64(
SDNode *
N);
255 void SelectAddcSubb(
SDNode *
N);
256 void SelectUADDO_USUBO(
SDNode *
N);
257 void SelectDIV_SCALE(
SDNode *
N);
258 void SelectMAD_64_32(
SDNode *
N);
259 void SelectMUL_LOHI(
SDNode *
N);
260 void SelectFMA_W_CHAIN(
SDNode *
N);
261 void SelectFMUL_W_CHAIN(
SDNode *
N);
264 void SelectS_BFEFromShifts(
SDNode *
N);
266 bool isCBranchSCC(
const SDNode *
N)
const;
268 void SelectFMAD_FMA(
SDNode *
N);
269 void SelectFP_EXTEND(
SDNode *
N);
270 void SelectDSAppendConsume(
SDNode *
N,
unsigned IntrID);
271 void SelectDSBvhStackIntrinsic(
SDNode *
N);
272 void SelectDS_GWS(
SDNode *
N,
unsigned IntrID);
273 void SelectInterpP1F16(
SDNode *
N);
274 void SelectINTRINSIC_W_CHAIN(
SDNode *
N);
275 void SelectINTRINSIC_WO_CHAIN(
SDNode *
N);
276 void SelectINTRINSIC_VOID(
SDNode *
N);
277 void SelectWAVE_ADDRESS(
SDNode *
N);
278 void SelectSTACKRESTORE(
SDNode *
N);
282#include "AMDGPUGenDAGISel.inc"
amdgpu AMDGPU Register Bank Select
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMD GCN specific subclass of TargetSubtarget.
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.
void SelectBuildVector(SDNode *N, unsigned RegClassID)
bool runOnMachineFunction(MachineFunction &MF) override
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
AMDGPUDAGToDAGISel()=delete
bool matchLoadD16FromBuildVector(SDNode *N) const
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Class for arbitrary precision integers.
A container for analyses that lazily runs them and caches their results.
Represent the analysis usage information of a pass.
const SIInstrInfo * getInstrInfo() const override
An SDNode that represents everything that will be needed to construct a MachineInstr.
A set of analyses that are preserved following a run of a transformation pass.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool isInlineConstant(const APInt &Imm) const
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
StringRef - Represent a constant reference to a string, i.e.
Primary interface to the complete machine description for the target machine.
@ C
The default llvm calling convention, compatible with C.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
This is an optimization pass for GlobalISel generic memory operations.
CodeGenOptLevel
Code generation optimization level.