22#include "llvm/IR/IntrinsicsHexagon.h"
27#define DEBUG_TYPE "hexagon-isel"
28#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection"
33 cl::desc(
"Rebalance address calculation trees to improve "
34 "instruction selection"));
41 cl::desc(
"Rebalance address tree only if this allows optimizations"));
46 cl::init(
false),
cl::desc(
"Rebalance address tree only if it is imbalanced"));
55#define GET_DAGISEL_BODY HexagonDAGToDAGISel
56#include "HexagonGenDAGISel.inc"
75 int32_t Inc = cast<ConstantSDNode>(
Offset.getNode())->getSExtValue();
76 EVT LoadedVT = LD->getMemoryVT();
83 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc);
89 Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
91 Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
95 Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
97 Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
103 Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
110 Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
120 if (isAlignedMemNode(LD)) {
121 if (LD->isNonTemporal())
122 Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
124 Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
126 Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
140 return CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
MVT::i64,
144 return CurDAG->getMachineNode(Hexagon::A2_sxtw, dl,
MVT::i64,
153 EVT ValueVT = LD->getValueType(0);
162 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT,
165 CurDAG->setNodeMemRefs(L, {
MemOp});
169 if (LD->getValueType(0) ==
MVT::i64)
176 CurDAG->setNodeMemRefs(L, {
MemOp});
182 if (LD->getValueType(0) ==
MVT::i64)
186 ReplaceUses(
From, To, 3);
187 CurDAG->RemoveDeadNode(LD);
195 unsigned IntNo = cast<ConstantSDNode>(IntN->
getOperand(1))->getZExtValue();
197 static std::map<unsigned,unsigned> LoadPciMap = {
198 { Intrinsic::hexagon_circ_ldb, Hexagon::L2_loadrb_pci },
199 { Intrinsic::hexagon_circ_ldub, Hexagon::L2_loadrub_pci },
200 { Intrinsic::hexagon_circ_ldh, Hexagon::L2_loadrh_pci },
201 { Intrinsic::hexagon_circ_lduh, Hexagon::L2_loadruh_pci },
202 { Intrinsic::hexagon_circ_ldw, Hexagon::L2_loadri_pci },
203 { Intrinsic::hexagon_circ_ldd, Hexagon::L2_loadrd_pci },
205 auto FLC = LoadPciMap.find(IntNo);
206 if (FLC != LoadPciMap.end()) {
210 auto Inc = cast<ConstantSDNode>(IntN->
getOperand(5));
213 { IntN->getOperand(2), I, IntN->getOperand(4),
214 IntN->getOperand(0) });
229 unsigned Size = 1U << (SizeBits-1);
287 switch (cast<ConstantSDNode>(
C->getOperand(1))->getZExtValue()) {
288 case Intrinsic::hexagon_circ_ldub:
289 case Intrinsic::hexagon_circ_lduh:
292 case Intrinsic::hexagon_circ_ldw:
293 case Intrinsic::hexagon_circ_ldd:
300 if (
N->getExtensionType() != IntExt)
305 if (
C->getNumOperands() < 4 || Loc.
getNode() !=
C->getOperand(3).getNode())
327 const SDLoc &dl(IntN);
328 unsigned IntNo = cast<ConstantSDNode>(IntN->
getOperand(1))->getZExtValue();
330 static const std::map<unsigned, unsigned> LoadBrevMap = {
331 { Intrinsic::hexagon_L2_loadrb_pbr, Hexagon::L2_loadrb_pbr },
332 { Intrinsic::hexagon_L2_loadrub_pbr, Hexagon::L2_loadrub_pbr },
333 { Intrinsic::hexagon_L2_loadrh_pbr, Hexagon::L2_loadrh_pbr },
334 { Intrinsic::hexagon_L2_loadruh_pbr, Hexagon::L2_loadruh_pbr },
335 { Intrinsic::hexagon_L2_loadri_pbr, Hexagon::L2_loadri_pbr },
336 { Intrinsic::hexagon_L2_loadrd_pbr, Hexagon::L2_loadrd_pbr }
338 auto FLI = LoadBrevMap.find(IntNo);
339 if (FLI != LoadBrevMap.end()) {
347 FLI->second, dl, RTys,
369 unsigned IntNo = cast<ConstantSDNode>(IntN->
getOperand(1))->getZExtValue();
372 static std::map<unsigned,unsigned> LoadNPcMap = {
373 { Intrinsic::hexagon_L2_loadrub_pci, Hexagon::PS_loadrub_pci },
374 { Intrinsic::hexagon_L2_loadrb_pci, Hexagon::PS_loadrb_pci },
375 { Intrinsic::hexagon_L2_loadruh_pci, Hexagon::PS_loadruh_pci },
376 { Intrinsic::hexagon_L2_loadrh_pci, Hexagon::PS_loadrh_pci },
377 { Intrinsic::hexagon_L2_loadri_pci, Hexagon::PS_loadri_pci },
378 { Intrinsic::hexagon_L2_loadrd_pci, Hexagon::PS_loadrd_pci },
379 { Intrinsic::hexagon_L2_loadrub_pcr, Hexagon::PS_loadrub_pcr },
380 { Intrinsic::hexagon_L2_loadrb_pcr, Hexagon::PS_loadrb_pcr },
381 { Intrinsic::hexagon_L2_loadruh_pcr, Hexagon::PS_loadruh_pcr },
382 { Intrinsic::hexagon_L2_loadrh_pcr, Hexagon::PS_loadrh_pcr },
383 { Intrinsic::hexagon_L2_loadri_pcr, Hexagon::PS_loadri_pcr },
384 { Intrinsic::hexagon_L2_loadrd_pcr, Hexagon::PS_loadrd_pcr }
386 auto FLI = LoadNPcMap.find (IntNo);
387 if (FLI != LoadNPcMap.end()) {
389 if (IntNo == Intrinsic::hexagon_L2_loadrd_pci ||
390 IntNo == Intrinsic::hexagon_L2_loadrd_pcr)
395 auto Inc = cast<ConstantSDNode>(IntN->
getOperand(3));
413 static std::map<unsigned,unsigned> StoreNPcMap = {
414 { Intrinsic::hexagon_S2_storerb_pci, Hexagon::PS_storerb_pci },
415 { Intrinsic::hexagon_S2_storerh_pci, Hexagon::PS_storerh_pci },
416 { Intrinsic::hexagon_S2_storerf_pci, Hexagon::PS_storerf_pci },
417 { Intrinsic::hexagon_S2_storeri_pci, Hexagon::PS_storeri_pci },
418 { Intrinsic::hexagon_S2_storerd_pci, Hexagon::PS_storerd_pci },
419 { Intrinsic::hexagon_S2_storerb_pcr, Hexagon::PS_storerb_pcr },
420 { Intrinsic::hexagon_S2_storerh_pcr, Hexagon::PS_storerh_pcr },
421 { Intrinsic::hexagon_S2_storerf_pcr, Hexagon::PS_storerf_pcr },
422 { Intrinsic::hexagon_S2_storeri_pcr, Hexagon::PS_storeri_pcr },
423 { Intrinsic::hexagon_S2_storerd_pcr, Hexagon::PS_storerd_pcr }
425 auto FSI = StoreNPcMap.find (IntNo);
426 if (FSI != StoreNPcMap.end()) {
430 auto Inc = cast<ConstantSDNode>(IntN->
getOperand(3));
469 SDValue Chain = ST->getChain();
474 int32_t Inc = cast<ConstantSDNode>(
Offset.getNode())->getSExtValue();
475 EVT StoredVT = ST->getMemoryVT();
484 Opcode = IsValidInc ? Hexagon::S2_storerb_pi : Hexagon::S2_storerb_io;
487 Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
493 Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
500 Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
510 if (isAlignedMemNode(ST)) {
511 if (ST->isNonTemporal())
512 Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai;
514 Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
516 Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
523 if (ST->isTruncatingStore() && ValueVT.
getSizeInBits() == 64) {
578 auto Default = [
this,
N] () ->
void { SelectCode(
N); };
584 int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue();
591 int32_t ValConst =
C->getSExtValue() << ShlConst;
592 if (isInt<9>(ValConst)) {
612 int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
613 if (isInt<9>(-ValConst)) {
644 unsigned IntNo = cast<ConstantSDNode>(
N->getOperand(1))->getZExtValue();
645 if (IntNo == Intrinsic::hexagon_V6_vgathermw ||
646 IntNo == Intrinsic::hexagon_V6_vgathermw_128B ||
647 IntNo == Intrinsic::hexagon_V6_vgathermh ||
648 IntNo == Intrinsic::hexagon_V6_vgathermh_128B ||
649 IntNo == Intrinsic::hexagon_V6_vgathermhw ||
650 IntNo == Intrinsic::hexagon_V6_vgathermhw_128B) {
654 if (IntNo == Intrinsic::hexagon_V6_vgathermwq ||
655 IntNo == Intrinsic::hexagon_V6_vgathermwq_128B ||
656 IntNo == Intrinsic::hexagon_V6_vgathermhq ||
657 IntNo == Intrinsic::hexagon_V6_vgathermhq_128B ||
658 IntNo == Intrinsic::hexagon_V6_vgathermhwq ||
659 IntNo == Intrinsic::hexagon_V6_vgathermhwq_128B) {
668 unsigned IID = cast<ConstantSDNode>(
N->getOperand(0))->getZExtValue();
671 case Intrinsic::hexagon_S2_vsplatrb:
674 case Intrinsic::hexagon_S2_vsplatrh:
677 case Intrinsic::hexagon_V6_vaddcarry:
678 case Intrinsic::hexagon_V6_vaddcarry_128B:
679 case Intrinsic::hexagon_V6_vsubcarry:
680 case Intrinsic::hexagon_V6_vsubcarry_128B:
691 if (keepsLowBits(V, Bits, U)) {
693 N->getOperand(0), U);
695 SelectCode(R.getNode());
703 MVT ResTy =
N->getValueType(0).getSimpleVT();
704 auto IdxN = cast<ConstantSDNode>(
N->getOperand(1));
705 unsigned Idx = IdxN->getZExtValue();
714 unsigned SubReg =
Idx == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
725 auto *CN = cast<ConstantFPSDNode>(
N);
726 APInt A = CN->getValueAPF().bitcastToAPInt();
745 if (
N->getValueType(0) ==
MVT::i1) {
746 assert(!(cast<ConstantSDNode>(
N)->getZExtValue() >> 1));
747 unsigned Opc = (cast<ConstantSDNode>(
N)->getSExtValue() != 0)
760 int FX = cast<FrameIndexSDNode>(
N)->getIndex();
777 Register AR = HMFI.getStackAlignBaseReg();
788 : Hexagon::A4_subp_c;
790 { N->getOperand(0), N->getOperand(1),
796 MVT ResTy =
N->getValueType(0).getSimpleVT();
798 return SelectHvxVAlign(
N);
819 M0,
N->getOperand(2),
M1);
822 N->getOperand(2),
M1);
836 N->getOperand(0),
N->getOperand(1),
845 int Mask = -cast<ConstantSDNode>(
A.getNode())->getSExtValue();
850 N->getOperand(0), M);
859 MVT OpTy = Op.getValueType().getSimpleVT();
866 MVT ResTy =
N->getValueType(0).getSimpleVT();
874 MVT ResTy =
N->getValueType(0).getSimpleVT();
877 N->getOperand(0), Zero);
883 MVT ResTy =
N->getValueType(0).getSimpleVT();
885 MVT OpTy =
N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy;
897 MVT ResTy =
N->getValueType(0).getSimpleVT();
909 if (
N->isMachineOpcode())
910 return N->setNodeId(-1);
912 auto isHvxOp = [
this](
SDNode *
N) {
913 for (
unsigned i = 0, e =
N->getNumValues(); i != e; ++i) {
925 switch (
N->getOpcode()) {
933 switch (
N->getOpcode()) {
960 std::vector<SDValue> &OutOps) {
963 switch (ConstraintID) {
970 OutOps.push_back(Res);
972 OutOps.push_back(Inp);
988 unsigned Opc = U->getOpcode();
1000 SDValue S1 = U->getOperand(1);
1003 SDNode *UUse = *U->use_begin();
1011 SDNode *SYNode = SY.getNode();
1013 SDValue LDBasePtr = cast<MemSDNode>(SYNode)->getBasePtr();
1014 SDValue STBasePtr = cast<MemSDNode>(UUse)->getBasePtr();
1015 if (LDBasePtr == STBasePtr)
1024void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
1027 for (
auto *
I : Nodes) {
1031 auto IsZero = [] (
const SDValue &
V) ->
bool {
1033 return SC->isZero();
1036 auto IsSelect0 = [IsZero] (
const SDValue &
Op) ->
bool {
1039 return IsZero(
Op.getOperand(1)) || IsZero(
Op.getOperand(2));
1042 SDValue N0 =
I->getOperand(0), N1 =
I->getOperand(1);
1043 EVT VT =
I->getValueType(0);
1044 bool SelN0 = IsSelect0(N0);
1045 SDValue SOp = SelN0 ? N0 : N1;
1046 SDValue VOp = SelN0 ? N1 : N0;
1057 }
else if (IsZero(SX)) {
1072void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) {
1075 for (
auto *
I : Nodes) {
1107 if (EV % (1 << CV) != 0)
1109 unsigned DV = EV / (1 << CV);
1136void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) {
1140 unsigned Opc =
N->getOpcode();
1177 if (TZ +
M1 + LZ != 32)
1201void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
1205 unsigned Opc =
N->getOpcode();
1212 for (
auto I =
N->use_begin(),
E =
N->use_end();
I !=
E; ++
I) {
1214 if (
U->getNumValues() != 1)
1216 EVT UVT =
U->getValueType(0);
1226 unsigned I1N =
I.getOperandNo();
1228 for (
unsigned i = 0, n =
U->getNumOperands(); i != n; ++i)
1229 Ops[i] =
U->getOperand(i);
1230 EVT BVT = Ops[I1N].getValueType();
1237 if (isa<MachineSDNode>(U)) {
1238 unsigned UseOpc =
U->getMachineOpcode();
1244 unsigned UseOpc =
U->getOpcode();
1246 If0 = DAG.
getNode(UseOpc, dl, UVT, Ops);
1248 If1 = DAG.
getNode(UseOpc, dl, UVT, Ops);
1266 auto getNodes = [
this]() -> std::vector<SDNode *> {
1267 std::vector<SDNode *>
T;
1275 PreprocessHvxISelDAG();
1279 ppSimplifyOrSelect0(getNodes());
1287 ppAddrReorderAddShl(getNodes());
1302 ppAddrRewriteAndSrl(getNodes());
1306 ppHoistZextI1(getNodes());
1309 dbgs() <<
"Preprocessed (Hexagon) selection DAG:";
1314 rebalanceAddressTrees();
1317 dbgs() <<
"Address tree balanced selection DAG:";
1326 if (!HFI.needsAligna(*
MF))
1343 assert(AP.
isValid() &&
"Couldn't reserve stack align register");
1349void HexagonDAGToDAGISel::updateAligna() {
1351 if (!HFI.needsAligna(*
MF))
1353 auto *AlignaI =
const_cast<MachineInstr*
>(HFI.getAlignaInstr(*
MF));
1354 assert(AlignaI !=
nullptr);
1356 if (AlignaI->getOperand(1).getImm() < MaxA)
1357 AlignaI->getOperand(1).setImm(MaxA);
1366 int FX = cast<FrameIndexSDNode>(
N)->getIndex();
1399 EVT T =
N.getValueType();
1400 if (!
T.isInteger() ||
T.getSizeInBits() != 32 || !isa<ConstantSDNode>(
N))
1402 int32_t V = cast<const ConstantSDNode>(
N)->getZExtValue();
1409 switch (
N.getOpcode()) {
1413 int32_t V = cast<const ConstantSDNode>(
N)->getZExtValue();
1422 if (Alignment >
Align(8))
1424 R =
N.getOperand(0);
1428 if (Alignment >
Align(1))
1434 if (Alignment >
Align(4) ||
1449 bool UseGP,
Align Alignment) {
1450 switch (
N.getOpcode()) {
1460 if (!
isAligned(Alignment, Const->getZExtValue()))
1467 N.getValueType(), NewOff);
1480 R =
N.getOperand(0);
1484 R =
N.getOperand(0);
1514 unsigned Opc =
N.getOpcode();
1520 ?
N.getOperand(0).getValueType()
1521 : cast<VTSDNode>(
N.getOperand(1))->getVT();
1522 unsigned SW =
T.getSizeInBits();
1524 R =
N.getOperand(0);
1537 if (L->getMemoryVT().getSizeInBits() > 32)
1543 auto *S = dyn_cast<ConstantSDNode>(
N.getOperand(1));
1544 if (!S || S->getZExtValue() != 32)
1552 EVT RT = R.getValueType();
1570bool HexagonDAGToDAGISel::keepsLowBits(
const SDValue &Val,
unsigned NumBits,
1579 if (
T.isInteger() &&
T.getSizeInBits() == NumBits) {
1590 if (
T->getVT().getSizeInBits() == NumBits) {
1600 if (
C->getZExtValue() ==
Mask) {
1606 if (
C->getZExtValue() ==
Mask) {
1618 if ((
C->getZExtValue() &
Mask) == 0) {
1624 if ((
C->getZExtValue() &
Mask) == 0) {
1637bool HexagonDAGToDAGISel::isAlignedMemNode(
const MemSDNode *
N)
const {
1638 return N->getAlign().value() >=
N->getMemoryVT().getStoreSize();
1641bool HexagonDAGToDAGISel::isSmallStackStore(
const StoreSDNode *
N)
const {
1643 switch (
N->getMemoryVT().getStoreSize()) {
1645 return StackSize <= 56;
1647 return StackSize <= 120;
1649 return StackSize <= 248;
1656bool HexagonDAGToDAGISel::isPositiveHalfWord(
const SDNode *
N)
const {
1659 return V > 0 && isInt<16>(V);
1662 const VTSDNode *VN = dyn_cast<const VTSDNode>(
N->getOperand(1));
1668bool HexagonDAGToDAGISel::hasOneUse(
const SDNode *
N)
const {
1676 switch (
N->getOpcode()) {
1683 return isa<ConstantSDNode>(
N->getOperand(1).getNode());
1690int HexagonDAGToDAGISel::getWeight(
SDNode *
N) {
1693 assert(RootWeights.count(
N) &&
"Cannot get weight of unseen root!");
1694 assert(RootWeights[
N] != -1 &&
"Cannot get weight of unvisited root!");
1695 assert(RootWeights[
N] != -2 &&
"Cannot get weight of RAWU'd root!");
1696 return RootWeights[
N];
1699int HexagonDAGToDAGISel::getHeight(
SDNode *
N) {
1702 assert(RootWeights.count(
N) && RootWeights[
N] >= 0 &&
1703 "Cannot query height of unvisited/RAUW'd node!");
1704 return RootHeights[
N];
1708struct WeightedLeaf {
1715 WeightedLeaf(
SDValue Value,
int Weight,
int InsertionOrder) :
1716 Value(
Value), Weight(Weight), InsertionOrder(InsertionOrder) {
1717 assert(Weight >= 0 &&
"Weight must be >= 0");
1720 static bool Compare(
const WeightedLeaf &
A,
const WeightedLeaf &
B) {
1721 assert(
A.Value.getNode() &&
B.Value.getNode());
1722 return A.Weight ==
B.Weight ?
1723 (
A.InsertionOrder >
B.InsertionOrder) :
1724 (
A.Weight >
B.Weight);
1731class LeafPrioQueue {
1734 WeightedLeaf ConstElt;
1739 return (!HaveConst && Q.
empty());
1743 return Q.
size() + HaveConst;
1750 const WeightedLeaf &top() {
1756 WeightedLeaf pop() {
1761 std::pop_heap(Q.
begin(), Q.
end(), WeightedLeaf::Compare);
1765 void push(WeightedLeaf L,
bool SeparateConst=
true) {
1766 if (!HaveConst && SeparateConst && isa<ConstantSDNode>(
L.Value)) {
1768 cast<ConstantSDNode>(
L.Value)->getSExtValue() == 1)
1771 cast<ConstantSDNode>(
L.Value)->getSExtValue() == 0)
1778 std::push_heap(Q.
begin(), Q.
end(), WeightedLeaf::Compare);
1784 void pushToBottom(WeightedLeaf L) {
1791 WeightedLeaf findSHL(
uint64_t MaxAmount);
1793 WeightedLeaf findMULbyConst();
1795 LeafPrioQueue(
unsigned Opcode) :
1796 HaveConst(
false), Opcode(Opcode) { }
1800WeightedLeaf LeafPrioQueue::findSHL(
uint64_t MaxAmount) {
1804 for (
int Pos = 0, End = Q.
size(); Pos != End; ++Pos) {
1805 const WeightedLeaf &
L = Q[Pos];
1812 (
Result.Weight ==
L.Weight &&
Result.InsertionOrder >
L.InsertionOrder))
1819 if (
Result.Value.getNode()) {
1820 Q.
erase(&Q[ResultPos]);
1821 std::make_heap(Q.
begin(), Q.
end(), WeightedLeaf::Compare);
1827WeightedLeaf LeafPrioQueue::findMULbyConst() {
1831 for (
int Pos = 0, End = Q.
size(); Pos != End; ++Pos) {
1832 const WeightedLeaf &
L = Q[Pos];
1839 (
Result.Weight ==
L.Weight &&
Result.InsertionOrder >
L.InsertionOrder))
1846 if (
Result.Value.getNode()) {
1847 Q.
erase(&Q[ResultPos]);
1848 std::make_heap(Q.
begin(), Q.
end(), WeightedLeaf::Compare);
1855 uint64_t MulFactor = 1ull <<
N->getConstantOperandVal(1);
1857 N->getOperand(1).getValueType());
1863 unsigned MaxFactor = 0;
1864 for (
int i = 0; i < 2; ++i) {
1868 const APInt &CInt =
C->getAPIntValue();
1886 SDValue Ops[] = { V.getOperand(0), V.getOperand(1) };
1887 for (
int i = 0; i < 2; ++i)
1888 if (isa<ConstantSDNode>(Ops[i].getNode()) &&
1889 V.getConstantOperandVal(i) % (1ULL << Amount) == 0) {
1890 uint64_t NewConst = V.getConstantOperandVal(i) >> Amount;
1891 return (NewConst == 1);
1893 }
else if (V.getOpcode() ==
ISD::SHL) {
1894 return (Amount == V.getConstantOperandVal(1));
1900SDValue HexagonDAGToDAGISel::factorOutPowerOf2(
SDValue V,
unsigned Power) {
1901 SDValue Ops[] = {
V.getOperand(0),
V.getOperand(1) };
1903 for (
int i=0; i < 2; ++i) {
1904 if (isa<ConstantSDNode>(Ops[i].getNode()) &&
1905 V.getConstantOperandVal(i) % ((
uint64_t)1 << Power) == 0) {
1906 uint64_t NewConst =
V.getConstantOperandVal(i) >> Power;
1910 SDLoc(V),
V.getValueType());
1915 uint64_t ShiftAmount =
V.getConstantOperandVal(1);
1916 if (ShiftAmount == Power)
1919 SDLoc(V),
V.getValueType());
1930unsigned HexagonDAGToDAGISel::getUsesInFunction(
const Value *V) {
1931 if (GAUsesInFunction.count(V))
1932 return GAUsesInFunction[
V];
1936 for (
const User *U :
V->users()) {
1937 if (isa<Instruction>(U) &&
1952SDValue HexagonDAGToDAGISel::balanceSubTree(
SDNode *
N,
bool TopLevel) {
1953 assert(RootWeights.count(
N) &&
"Cannot balance non-root node.");
1954 assert(RootWeights[
N] != -2 &&
"This node was RAUW'd!");
1958 if (RootWeights[
N] != -1)
1972 Weight = getWeight(balanceSubTree(Op0N).getNode());
1975 Weight = getWeight(Op0N);
1977 SDNode *Op1N =
N->getOperand(1).getNode();
1979 Weight += getWeight(balanceSubTree(Op1N).getNode());
1982 Weight += getWeight(Op1N);
1984 RootWeights[
N] = Weight;
1985 RootHeights[
N] = std::max(getHeight(
N->getOperand(0).getNode()),
1986 getHeight(
N->getOperand(1).getNode())) + 1;
1988 LLVM_DEBUG(
dbgs() <<
"--> No need to balance root (Weight=" << Weight
1989 <<
" Height=" << RootHeights[
N] <<
"): ");
1998 unsigned NOpcode =
N->getOpcode();
2000 LeafPrioQueue Leaves(NOpcode);
2008 bool CanFactorize =
false;
2009 WeightedLeaf Mul1, Mul2;
2010 unsigned MaxPowerOf2 = 0;
2015 bool HaveTopLevelShift =
false;
2021 HaveTopLevelShift =
true;
2025 int InsertionOrder = 0;
2027 bool Imbalanced =
false;
2028 int CurrentWeight = 0;
2029 while (!Worklist.
empty()) {
2035 int Weight = RootWeights[Child.
getNode()];
2037 Child = balanceSubTree(Child.
getNode());
2039 Weight = getWeight(Child.
getNode());
2040 }
else if (Weight == -2) {
2045 return balanceSubTree(
N, TopLevel);
2048 NodeHeights[Child] = 1;
2049 CurrentWeight += Weight;
2052 if (TopLevel && !CanFactorize && !HaveTopLevelShift &&
2058 if (!Mul1.Value.getNode()) {
2059 Mul1 = WeightedLeaf(Child, Weight, InsertionOrder++);
2060 MaxPowerOf2 = PowerOf2;
2062 Mul2 = WeightedLeaf(Child, Weight, InsertionOrder++);
2063 MaxPowerOf2 = std::min(MaxPowerOf2, PowerOf2);
2066 if (MaxPowerOf2 > 3)
2069 CanFactorize =
true;
2072 Leaves.push(WeightedLeaf(Child, Weight, InsertionOrder++));
2075 int Weight = getWeight(Child.
getNode());
2077 NodeHeights[Child] = getHeight(Child.
getNode());
2078 CurrentWeight += Weight;
2081 GA = WeightedLeaf(Child, Weight, InsertionOrder++);
2083 Leaves.push(WeightedLeaf(Child, Weight, InsertionOrder++));
2087 unsigned ChildOpcode = Child.
getOpcode();
2088 assert(ChildOpcode == NOpcode ||
2094 Op1 = getMultiplierForSHL(Child.
getNode());
2099 assert(!NodeHeights.
count(Child) &&
"Parent visited before children?");
2106 if (std::abs(NodeHeights[Op1] - NodeHeights[Child->
getOperand(0)]) > 1)
2109 NodeHeights[Child] = std::max(NodeHeights[Op1],
2116 <<
" weight=" << CurrentWeight
2117 <<
" imbalanced=" << Imbalanced <<
"\n");
2123 LLVM_DEBUG(
dbgs() <<
"--> Found common factor for two MUL children!\n");
2124 int Weight = Mul1.Weight + Mul2.Weight;
2125 int Height = std::max(NodeHeights[Mul1.Value], NodeHeights[Mul2.Value]) + 1;
2126 SDValue Mul1Factored = factorOutPowerOf2(Mul1.Value, MaxPowerOf2);
2127 SDValue Mul2Factored = factorOutPowerOf2(Mul2.Value, MaxPowerOf2);
2129 Mul1Factored, Mul2Factored);
2131 Mul1.Value.getValueType());
2134 NodeHeights[
New] = Height;
2135 Leaves.push(WeightedLeaf(New, Weight, Mul1.InsertionOrder));
2136 }
else if (Mul1.Value.getNode()) {
2140 if (Mul2.Value.getNode())
2142 CanFactorize =
false;
2148 bool CombinedGA =
false;
2149 if (NOpcode ==
ISD::ADD && GA.Value.getNode() && Leaves.hasConst() &&
2150 GA.Value.hasOneUse() &&
N->use_size() < 3) {
2152 cast<GlobalAddressSDNode>(GA.Value.getOperand(0));
2155 if (getUsesInFunction(GANode->
getGlobal()) == 1 &&
Offset->hasOneUse() &&
2158 <<
Offset->getSExtValue() <<
"): ");
2166 GA.Value.getValueType(), NewTGA);
2167 GA.Weight += Leaves.top().Weight;
2169 NodeHeights[GA.Value] = getHeight(GA.Value.getNode());
2178 RootWeights[
N] = CurrentWeight;
2179 RootHeights[
N] = NodeHeights[
SDValue(
N, 0)];
2185 if (NOpcode ==
ISD::ADD && GA.Value.getNode()) {
2186 WeightedLeaf
SHL = Leaves.findSHL(31);
2187 if (
SHL.Value.getNode()) {
2188 int Height = std::max(NodeHeights[GA.Value], NodeHeights[
SHL.Value]) + 1;
2190 GA.Value.getValueType(),
2191 GA.Value,
SHL.Value);
2192 GA.Weight =
SHL.Weight;
2193 NodeHeights[GA.Value] = Height;
2197 if (GA.Value.getNode())
2202 if (TopLevel && !CanFactorize && Leaves.hasConst()) {
2204 Leaves.pushToBottom(Leaves.pop());
2211 while (Leaves.size() > 1) {
2212 WeightedLeaf L0 = Leaves.pop();
2216 WeightedLeaf L1 = Leaves.findMULbyConst();
2217 if (!L1.Value.getNode())
2220 assert(L0.Weight <= L1.Weight &&
"Priority queue is broken!");
2223 int V0Weight = L0.Weight;
2225 int V1Weight = L1.Weight;
2228 if ((RootWeights.count(V0.
getNode()) && RootWeights[V0.
getNode()] == -2) ||
2229 (RootWeights.count(V1.
getNode()) && RootWeights[V1.
getNode()] == -2)) {
2231 return balanceSubTree(
N, TopLevel);
2236 EVT VT =
N->getValueType(0);
2246 "Children must have been visited before re-combining them!");
2247 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1;
2259 NodeHeights[NewNode] = Height;
2261 int Weight = V0Weight + V1Weight;
2262 Leaves.push(WeightedLeaf(NewNode, Weight, L0.InsertionOrder));
2265 <<
",Height=" << Height <<
"):\n");
2269 assert(Leaves.size() == 1);
2270 SDValue NewRoot = Leaves.top().Value;
2273 int Height = NodeHeights[NewRoot];
2296 RootWeights[
N] = -2;
2301 RootWeights[NewRoot.
getNode()] = Leaves.top().Weight;
2302 RootHeights[NewRoot.
getNode()] = Height;
2307void HexagonDAGToDAGISel::rebalanceAddressTrees() {
2318 if (RootWeights.count(
BasePtr.getNode()))
2321 LLVM_DEBUG(
dbgs() <<
"** Rebalancing address calculation in node: ");
2330 while (!Worklist.
empty()) {
2332 unsigned Opcode =
N->getOpcode();
2337 Worklist.
push_back(
N->getOperand(0).getNode());
2338 Worklist.
push_back(
N->getOperand(1).getNode());
2341 if (
N->hasOneUse() && Opcode ==
N->use_begin()->getOpcode())
2345 if (RootWeights.count(
N))
2348 RootWeights[
N] = -1;
2352 RootWeights[
BasePtr.getNode()] = -1;
2357 NewBasePtr,
N->getOperand(2));
2360 NewBasePtr,
N->getOperand(3));
2367 GAUsesInFunction.clear();
2368 RootHeights.clear();
2369 RootWeights.clear();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static const Function * getParent(const Value *V)
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
static bool willShiftRightEliminate(SDValue V, unsigned Amount)
static cl::opt< bool > RebalanceOnlyImbalancedTrees("rebalance-only-imbal", cl::Hidden, cl::init(false), cl::desc("Rebalance address tree only if it is imbalanced"))
static unsigned getPowerOf2Factor(SDValue Val)
static cl::opt< bool > CheckSingleUse("hexagon-isel-su", cl::Hidden, cl::init(true), cl::desc("Enable checking of SDNode's single-use status"))
static cl::opt< bool > EnableAddressRebalancing("isel-rebalance-addr", cl::Hidden, cl::init(true), cl::desc("Rebalance address calculation trees to improve " "instruction selection"))
static bool isMemOPCandidate(SDNode *I, SDNode *U)
static bool isTargetConstant(const SDValue &V)
static bool isOpcodeHandled(const SDNode *N)
static cl::opt< bool > RebalanceOnlyForOptimizations("rebalance-only-opt", cl::Hidden, cl::init(false), cl::desc("Rebalance address tree only if this allows optimizations"))
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned logBase2() const
bool getBoolValue() const
Convert APInt to a boolean value.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
int64_t getSExtValue() const
A parsed version of the target data layout string in and methods for querying it.
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
FunctionPass class - This class is used to implement most global optimizations.
int64_t getOffset() const
const GlobalValue * getGlobal() const
This class is used to form a handle around another node that is persistent and is updated across invo...
const SDValue & getValue() const
void SelectAddSubCarry(SDNode *N)
void SelectConstant(SDNode *N)
void SelectIntrinsicWOChain(SDNode *N)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
void SelectExtractSubvector(SDNode *N)
void SelectVAlign(SDNode *N)
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
bool SelectAnyImm2(SDValue &N, SDValue &R)
bool SelectAnyImm(SDValue &N, SDValue &R)
void SelectV65GatherPred(SDNode *N)
bool SelectAnyImm0(SDValue &N, SDValue &R)
void SelectSHL(SDNode *N)
void SelectIntrinsicWChain(SDNode *N)
void SelectV2Q(SDNode *N)
bool SelectAnyImm1(SDValue &N, SDValue &R)
void SelectConstantFP(SDNode *N)
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectBrevLdIntrinsic(SDNode *IntN)
void emitFunctionEntryCode() override
bool SelectAddrFI(SDValue &N, SDValue &R)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
bool SelectAddrGP(SDValue &N, SDValue &R)
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
void SelectFrameIndex(SDNode *N)
bool SelectAnyImm3(SDValue &N, SDValue &R)
void SelectStore(SDNode *N)
void SelectLoad(SDNode *N)
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectAddrGA(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
void SelectTypecast(SDNode *N)
void SelectD2P(SDNode *N)
void SelectVAlignAddr(SDNode *N)
void SelectP2D(SDNode *N)
void SelectV65Gather(SDNode *N)
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
void SelectHVXDualOutput(SDNode *N)
void SelectQ2V(SDNode *N)
bool isValidAutoIncImm(const EVT VT, const int Offset) const
Hexagon target-specific information for each MachineFunction.
BitVector getReservedRegs(const MachineFunction &MF) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
const HexagonFrameLowering * getFrameLowering() const override
const HexagonRegisterInfo * getRegisterInfo() const override
bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const
unsigned getVectorLength() const
This class is used to represent ISD::LOAD nodes.
unsigned getVectorNumElements() const
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
MVT getVectorElementType() const
static MVT getIntegerVT(unsigned BitWidth)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Representation of each machine instruction.
A description of a memory reference used in the backend.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
void dump() const
Dump this node, for debugging.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool hasOneUse() const
Return true if there is exactly one use of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
const TargetLowering * TLI
void ReplaceUses(SDValue F, SDValue T)
ReplaceUses - replace all uses of the old node F with the use of the new node T.
void ReplaceNode(SDNode *F, SDNode *T)
Replace all uses of F with T, then remove F from the DAG.
const TargetLowering * getTargetLowering() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
const DataLayout & getDataLayout() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
iterator_range< allnodes_iterator > allnodes()
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
ilist< SDNode >::size_type allnodes_size() const
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
iterator erase(const_iterator CI)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This class is used to represent EVT's, which are used to parameterize some operations.
LLVM Value Representation.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
Level
Code generation optimization level.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ SIGN_EXTEND
Conversion operators.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
unsigned M1(unsigned Val)
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned M0(unsigned Val)
@ Default
The result values are uniform if and only if all operands are uniform.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
bool isVector() const
Return true if this is a vector value type.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isInteger() const
Return true if this is an integer or a vector integer type.
This class contains a discriminated union of information about pointers in memory operands,...