Go to the documentation of this file.
29 #include "llvm/Config/llvm-config.h"
56 cl::desc(
"Display more information when dumping selection "
63 return "<<Unknown DAG Node>>";
69 return "<<Unknown Machine Node #" + utostr(
getOpcode()) +
">>";
75 return "<<Unknown Target Node #" + utostr(
getOpcode()) +
">>";
77 return "<<Unknown Node #" + utostr(
getOpcode()) +
">>";
116 if (cast<ConstantSDNode>(
this)->isOpaque())
117 return "OpaqueConstant";
146 unsigned IID = cast<ConstantSDNode>(
getOperand(OpNo))->getZExtValue();
147 if (IID < Intrinsic::num_intrinsics)
150 return "Unknown intrinsic";
152 return TII->getName(IID);
158 if (cast<ConstantSDNode>(
this)->isOpaque())
159 return "OpaqueTargetConstant";
160 return "TargetConstant";
408 return "pseudoprobe";
438 switch (cast<CondCodeSDNode>(
this)->
get()) {
485 #define BEGIN_REGISTER_VP_SDNODE(SDID, LEGALARG, NAME, ...) \
488 #include "llvm/IR/VPIntrinsics.def"
505 OS <<
't' << Node.PersistentId;
507 OS << (
const void*)&Node;
521 MMO.
print(OS, MST, SSNs, Ctx, MFI,
TII);
530 G->getSubtarget().getInstrInfo(), *
G->getContext());
535 nullptr,
nullptr, Ctx);
538 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
576 if (
getFlags().hasAllowReciprocal())
582 if (
getFlags().hasApproximateFuncs())
585 if (
getFlags().hasAllowReassociation())
591 if (
const MachineSDNode *MN = dyn_cast<MachineSDNode>(
this)) {
592 if (!MN->memoperands_empty()) {
596 e = MN->memoperands_end();
i !=
e; ++
i) {
598 if (std::next(
i) !=
e)
604 dyn_cast<ShuffleVectorSDNode>(
this)) {
606 for (
unsigned i = 0,
e = ValueList[0].getVectorNumElements();
i !=
e; ++
i) {
607 int Idx = SVN->getMaskElt(
i);
615 }
else if (
const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(
this)) {
616 OS <<
'<' << CSDN->getAPIntValue() <<
'>';
617 }
else if (
const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(
this)) {
619 OS <<
'<' << CSDN->getValueAPF().convertToFloat() <<
'>';
621 OS <<
'<' << CSDN->getValueAPF().convertToDouble() <<
'>';
624 CSDN->getValueAPF().bitcastToAPInt().print(OS,
false);
628 dyn_cast<GlobalAddressSDNode>(
this)) {
629 int64_t offset = GADN->getOffset();
631 GADN->getGlobal()->printAsOperand(OS);
634 OS << " + " << offset;
637 if (unsigned int TF = GADN->getTargetFlags())
638 OS << " [TF=" << TF << ']
';
639 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
640 OS << "<" << FIDN->getIndex() << ">";
641 } else if (const JumpTableSDNode *JTDN = dyn_cast<JumpTableSDNode>(this)) {
642 OS << "<" << JTDN->getIndex() << ">";
643 if (unsigned int TF = JTDN->getTargetFlags())
644 OS << " [TF=" << TF << ']
';
645 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
646 int offset = CP->getOffset();
647 if (CP->isMachineConstantPoolEntry())
648 OS << "<" << *CP->getMachineCPVal() << ">";
650 OS << "<" << *CP->getConstVal() << ">";
652 OS << " + " << offset;
655 if (unsigned int TF = CP->getTargetFlags())
656 OS << " [TF=" << TF << ']
';
657 } else if (const TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(this)) {
658 OS << "<" << TI->getIndex() << '+
' << TI->getOffset() << ">";
659 if (unsigned TF = TI->getTargetFlags())
660 OS << " [TF=" << TF << ']
';
661 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
663 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
665 OS << LBB->getName() << " ";
666 OS << (const void*)BBDN->getBasicBlock() << ">";
667 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
668 OS << ' ' << printReg(R->getReg(),
669 G ? G->getSubtarget().getRegisterInfo() : nullptr);
670 } else if (const ExternalSymbolSDNode *ES =
671 dyn_cast<ExternalSymbolSDNode>(this)) {
672 OS << "'" << ES->getSymbol() << "'";
673 if (unsigned int TF = ES->getTargetFlags())
674 OS << " [TF=" << TF << ']
';
675 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
677 OS << "<" << M->getValue() << ">";
680 } else if (const MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(this)) {
682 OS << "<" << MD->getMD() << ">";
685 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
686 OS << ":" << N->getVT().getEVTString();
688 else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
691 printMemOperand(OS, *LD->getMemOperand(), G);
694 switch (LD->getExtensionType()) {
695 default: doExt = false; break;
696 case ISD::EXTLOAD: OS << ", anyext"; break;
697 case ISD::SEXTLOAD: OS << ", sext"; break;
698 case ISD::ZEXTLOAD: OS << ", zext"; break;
701 OS << " from " << LD->getMemoryVT().getEVTString();
703 const char *AM = getIndexedModeName(LD->getAddressingMode());
708 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(this)) {
710 printMemOperand(OS, *ST->getMemOperand(), G);
712 if (ST->isTruncatingStore())
713 OS << ", trunc to " << ST->getMemoryVT().getEVTString();
715 const char *AM = getIndexedModeName(ST->getAddressingMode());
720 } else if (const MaskedLoadSDNode *MLd = dyn_cast<MaskedLoadSDNode>(this)) {
723 printMemOperand(OS, *MLd->getMemOperand(), G);
726 switch (MLd->getExtensionType()) {
727 default: doExt = false; break;
728 case ISD::EXTLOAD: OS << ", anyext"; break;
729 case ISD::SEXTLOAD: OS << ", sext"; break;
730 case ISD::ZEXTLOAD: OS << ", zext"; break;
733 OS << " from " << MLd->getMemoryVT().getEVTString();
735 const char *AM = getIndexedModeName(MLd->getAddressingMode());
739 if (MLd->isExpandingLoad())
743 } else if (const MaskedStoreSDNode *MSt = dyn_cast<MaskedStoreSDNode>(this)) {
745 printMemOperand(OS, *MSt->getMemOperand(), G);
747 if (MSt->isTruncatingStore())
748 OS << ", trunc to " << MSt->getMemoryVT().getEVTString();
750 const char *AM = getIndexedModeName(MSt->getAddressingMode());
754 if (MSt->isCompressingStore())
755 OS << ", compressing";
758 } else if (const auto *MGather = dyn_cast<MaskedGatherSDNode>(this)) {
760 printMemOperand(OS, *MGather->getMemOperand(), G);
763 switch (MGather->getExtensionType()) {
764 default: doExt = false; break;
765 case ISD::EXTLOAD: OS << ", anyext"; break;
766 case ISD::SEXTLOAD: OS << ", sext"; break;
767 case ISD::ZEXTLOAD: OS << ", zext"; break;
770 OS << " from " << MGather->getMemoryVT().getEVTString();
772 auto Signed = MGather->isIndexSigned() ? "signed" : "unsigned";
773 auto Scaled = MGather->isIndexScaled() ? "scaled" : "unscaled";
774 OS << ", " << Signed << " " << Scaled << " offset";
777 } else if (const auto *MScatter = dyn_cast<MaskedScatterSDNode>(this)) {
779 printMemOperand(OS, *MScatter->getMemOperand(), G);
781 if (MScatter->isTruncatingStore())
782 OS << ", trunc to " << MScatter->getMemoryVT().getEVTString();
784 auto Signed = MScatter->isIndexSigned() ? "signed" : "unsigned";
785 auto Scaled = MScatter->isIndexScaled() ? "scaled" : "unscaled";
786 OS << ", " << Signed << " " << Scaled << " offset";
789 } else if (const MemSDNode *M = dyn_cast<MemSDNode>(this)) {
791 printMemOperand(OS, *M->getMemOperand(), G);
793 } else if (const BlockAddressSDNode *BA =
794 dyn_cast<BlockAddressSDNode>(this)) {
795 int64_t offset = BA->getOffset();
797 BA->getBlockAddress()->getFunction()->printAsOperand(OS, false);
799 BA->getBlockAddress()->getBasicBlock()->printAsOperand(OS, false);
802 OS << " + " << offset;
805 if (unsigned int TF = BA->getTargetFlags())
806 OS << " [TF=" << TF << ']
';
807 } else if (const AddrSpaceCastSDNode *ASC =
808 dyn_cast<AddrSpaceCastSDNode>(this)) {
810 << ASC->getSrcAddressSpace()
812 << ASC->getDestAddressSpace()
814 } else if (const LifetimeSDNode *LN = dyn_cast<LifetimeSDNode>(this)) {
816 OS << "<" << LN->getOffset() << " to " << LN->getOffset() + LN->getSize() << ">";
819 if (VerboseDAGDumping) {
820 if (unsigned Order = getIROrder())
821 OS << " [ORD=" << Order << ']
';
823 if (getNodeId() != -1)
824 OS << " [ID=" << getNodeId() << ']
';
825 if (!(isa<ConstantSDNode>(this) || (isa<ConstantFPSDNode>(this))))
826 OS << " # D:" << isDivergent();
828 if (G && !G->GetDbgValues(this).empty()) {
829 OS << " [NoOfDbgValues=" << G->GetDbgValues(this).size() << ']
';
830 for (SDDbgValue *Dbg : G->GetDbgValues(this))
831 if (!Dbg->isInvalidated())
833 } else if (getHasDebugValue())
834 OS << " [NoOfDbgValues>0]";
838 LLVM_DUMP_METHOD void SDDbgValue::print(raw_ostream &OS) const {
839 OS << " DbgVal(Order=" << getOrder() << ')
';
841 OS << "(Invalidated)";
846 for (const SDDbgOperand &Op : getLocationOps()) {
849 switch (Op.getKind()) {
850 case SDDbgOperand::SDNODE:
852 OS << "SDNODE=" << PrintNodeId(*Op.getSDNode()) << ':
' << Op.getResNo();
856 case SDDbgOperand::CONST:
859 case SDDbgOperand::FRAMEIX:
860 OS << "FRAMEIX=" << Op.getFrameIx();
862 case SDDbgOperand::VREG:
863 OS << "VREG=" << Op.getVReg();
869 if (isIndirect()) OS << "(Indirect)";
872 OS << ":\"" << Var->getName() << '"';
874 if (Expr->getNumElements())
879 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
880 LLVM_DUMP_METHOD void SDDbgValue::dump() const {
890 static bool shouldPrintInline(const SDNode &Node, const SelectionDAG *G) {
891 // Avoid lots of cluttering when inline printing nodes with associated
892 // DbgValues in verbose mode.
893 if (VerboseDAGDumping && G && !G->GetDbgValues(&Node).empty())
895 if (Node.getOpcode() == ISD::EntryToken)
897 return Node.getNumOperands() == 0;
900 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
901 static void DumpNodes(const SDNode *N, unsigned indent, const SelectionDAG *G) {
902 for (const SDValue &Op : N->op_values()) {
903 if (shouldPrintInline(*Op.getNode(), G))
905 if (Op.getNode()->hasOneUse())
906 DumpNodes(Op.getNode(), indent+2, G);
909 dbgs().indent(indent);
913 LLVM_DUMP_METHOD void SelectionDAG::dump() const {
916 for (const SDNode &N : allnodes()) {
917 if (!N.hasOneUse() && &N != getRoot().getNode() &&
918 (!shouldPrintInline(N, this) || N.use_empty()))
919 DumpNodes(&N, 2, this);
922 if (getRoot().getNode()) DumpNodes(getRoot().getNode(), 2, this);
925 if (VerboseDAGDumping) {
926 if (DbgBegin() != DbgEnd())
927 dbgs() << "SDDbgValues:\
n";
928 for (auto *Dbg : make_range(DbgBegin(), DbgEnd()))
930 if (ByvalParmDbgBegin() != ByvalParmDbgEnd())
931 dbgs() << "Byval SDDbgValues:\
n";
932 for (auto *Dbg : make_range(ByvalParmDbgBegin(), ByvalParmDbgEnd()))
939 void SDNode::printr(raw_ostream &OS, const SelectionDAG *G) const {
940 OS << PrintNodeId(*this) << ":
";
942 OS << " =
" << getOperationName(G);
943 print_details(OS, G);
946 static bool printOperand(raw_ostream &OS, const SelectionDAG *G,
947 const SDValue Value) {
948 if (!Value.getNode()) {
953 if (shouldPrintInline(*Value.getNode(), G)) {
954 OS << Value->getOperationName(G) << ':';
955 Value->print_types(OS, G);
956 Value->print_details(OS, G);
960 OS << PrintNodeId(*Value.getNode());
961 if (unsigned RN = Value.getResNo())
966 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
967 using VisitedSDNodeSet = SmallPtrSet<const SDNode *, 32>;
969 static void DumpNodesr(raw_ostream &OS, const SDNode *N, unsigned indent,
970 const SelectionDAG *G, VisitedSDNodeSet &once) {
971 if (!once.insert(N).second) // If we've been here before, return now.
974 // Dump the current SDNode, but don't end the line yet.
978 // Having printed this SDNode, walk the children:
979 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
983 const SDValue Op = N->getOperand(i);
984 bool printedInline = printOperand(OS, G, Op);
986 once.insert(Op.getNode());
991 // Dump children that have grandchildren on their own line(s).
992 for (const SDValue &Op : N->op_values())
993 DumpNodesr(OS, Op.getNode(), indent+2, G, once);
996 LLVM_DUMP_METHOD void SDNode::dumpr() const {
997 VisitedSDNodeSet once;
998 DumpNodesr(dbgs(), this, 0, nullptr, once);
1001 LLVM_DUMP_METHOD void SDNode::dumpr(const SelectionDAG *G) const {
1002 VisitedSDNodeSet once;
1003 DumpNodesr(dbgs(), this, 0, G, once);
1007 static void printrWithDepthHelper(raw_ostream &OS, const SDNode *N,
1008 const SelectionDAG *G, unsigned depth,
1017 for (const SDValue &Op : N->op_values()) {
1018 // Don't follow chain operands.
1019 if (Op.getValueType() == MVT::Other)
1022 printrWithDepthHelper(OS, Op.getNode(), G, depth - 1, indent + 2);
1026 void SDNode::printrWithDepth(raw_ostream &OS, const SelectionDAG *G,
1027 unsigned depth) const {
1028 printrWithDepthHelper(OS, this, G, depth, 0);
1031 void SDNode::printrFull(raw_ostream &OS, const SelectionDAG *G) const {
1032 // Don't print impossibly deep things.
1033 printrWithDepth(OS, G, 10);
1036 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1038 void SDNode::dumprWithDepth(const SelectionDAG *G, unsigned depth) const {
1039 printrWithDepth(dbgs(), G, depth);
1042 LLVM_DUMP_METHOD void SDNode::dumprFull(const SelectionDAG *G) const {
1043 // Don't print impossibly deep things.
1044 dumprWithDepth(G, 10);
1048 void SDNode::print(raw_ostream &OS, const SelectionDAG *G) const {
1050 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1051 if (i) OS << ",
"; else OS << " ";
1052 printOperand(OS, G, getOperand(i));
1054 if (DebugLoc DL = getDebugLoc()) {
StringRef getBaseName(ID id)
Return the LLVM name for an intrinsic, without encoded types for overloading, such as "llvm....
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
This file implements support for optimizing divisions by a constant.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
@ FLT_ROUNDS_
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BR_JT
BR_JT - Jumptable branch.
static const fltSemantics & IEEEsingle() LLVM_READNONE
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ LIFETIME_START
This corresponds to the llvm.lifetime.
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
@ BSWAP
Byte Swap and Counting operators.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
An SDNode that represents everything that will be needed to construct a MachineInstr.
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Represents one node in the SelectionDAG.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
A description of a memory reference used in the backend.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
void incorporateFunction(const Function &F)
Incorporate the given function.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Manage lifetime of a slot tracker for printing IR.
@ ADDCARRY
Carry-using nodes for multiple precision addition and subtraction.
@ BRCOND
BRCOND - Conditional branch.
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
TargetIntrinsicInfo - Interface to description of machine instruction set.
@ BRIND
BRIND - Indirect branch.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ GC_TRANSITION_START
GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the beginning and end of GC transition s...
@ BR_CC
BR_CC - Conditional branch.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
TargetInstrInfo - Interface to description of machine instruction set.
static bool hasNoUnsignedWrap(BinaryOperator &I)
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
const HexagonInstrInfo * TII
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
This class implements an extremely fast bulk output stream that can only output to a stream.
This file declares a class to represent arbitrary precision floating point values and provide a varie...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ SMULO
Same for multiplication.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ FADD
Simple binary floating point operators.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Module * getParent()
Get the module that this global value is contained inside of...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
void print_details(raw_ostream &OS, const SelectionDAG *G) const
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ TRAP
TRAP - Trapping instruction.
This is an important class for using LLVM in a threaded context.
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
iterator_range< typename GraphTraits< GraphType >::nodes_iterator > nodes(const GraphType &G)
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
const SDValue & getOperand(unsigned Num) const
static Printable PrintNodeId(const SDNode &Node)
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
void dump() const
Dump this node, for debugging.
ArrayRef< MachineMemOperand * >::const_iterator mmo_iterator
static void printMemOperand(raw_ostream &OS, const MachineMemOperand &MMO, const MachineFunction *MF, const Module *M, const MachineFrameInfo *MFI, const TargetInstrInfo *TII, LLVMContext &Ctx)
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
void print(raw_ostream &OS, const SelectionDAG *G=nullptr) const
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ BasicBlock
Various leaf nodes.
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
A Module instance is used to store all the information related to an LLVM module.
virtual const char * getTargetNodeName(unsigned Opcode) const
This method returns the name of a target specific DAG node.
bool isMachineOpcode() const
Test if this node has a post-isel opcode, directly corresponding to a MachineInstr opcode.
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
void print_types(raw_ostream &OS, const SelectionDAG *G) const
static const fltSemantics & IEEEdouble() LLVM_READNONE
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static const char * getIndexedModeName(ISD::MemIndexedMode AM)
@ UNDEF
UNDEF - An undefined node.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ CARRY_FALSE
CARRY_FALSE - This node is used when folding other nodes, like ADDC/SUBC, which indicate the carry re...
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
std::string getOperationName(const SelectionDAG *G=nullptr) const
Return the opcode of this operation for printing.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
Function & getFunction()
Return the LLVM function that this machine code represents.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Should compile to something r4 addze r3 instead we get
@ BR
Control flow instructions. These all have token chains.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
@ FRAME_TO_ARGS_OFFSET
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
static bool hasNoSignedWrap(BinaryOperator &I)
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ ADD
Simple integer binary arithmetic operators.
@ SSUBO
Same for subtraction.
unsigned getMachineOpcode() const
This may only be called if isMachineOpcode returns true.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SHL
Shift and rotation operations.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Simple wrapper around std::function<void(raw_ostream&)>.
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
static bool hasNoInfs(const TargetOptions &Options, SDValue N)
@ SIGN_EXTEND
Conversion operators.
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
SDNodeFlags getFlags() const
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ SET_ROUNDING
Set rounding mode.
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
static cl::opt< bool > VerboseDAGDumping("dag-dump-verbose", cl::Hidden, cl::desc("Display more information when dumping selection " "DAG nodes."))
