LLVM 19.0.0git
Go to the documentation of this file.
1//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8// Hexagon specific code to select Hexagon machine instructions for
9// SelectionDAG operations.
15#include "HexagonSubtarget.h"
21#include <vector>
23namespace llvm {
24class MachineFunction;
25class HexagonInstrInfo;
26class HexagonRegisterInfo;
29 const HexagonSubtarget *HST;
30 const HexagonInstrInfo *HII;
31 const HexagonRegisterInfo *HRI;
38 : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
39 HRI(nullptr) {}
42 // Reset the subtarget each time through.
44 HII = HST->getInstrInfo();
45 HRI = HST->getRegisterInfo();
47 updateAligna();
48 return true;
49 }
51 bool ComplexPatternFuncMutatesDAG() const override {
52 return true;
53 }
54 void PreprocessISelDAG() override;
55 void emitFunctionEntryCode() override;
57 void Select(SDNode *N) override;
59 // Complex Pattern Selectors.
60 inline bool SelectAddrGA(SDValue &N, SDValue &R);
61 inline bool SelectAddrGP(SDValue &N, SDValue &R);
62 inline bool SelectAnyImm(SDValue &N, SDValue &R);
63 inline bool SelectAnyInt(SDValue &N, SDValue &R);
64 bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment);
65 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment);
66 bool SelectAddrFI(SDValue &N, SDValue &R);
67 bool DetectUseSxtw(SDValue &N, SDValue &R);
69 inline bool SelectAnyImm0(SDValue &N, SDValue &R);
70 inline bool SelectAnyImm1(SDValue &N, SDValue &R);
71 inline bool SelectAnyImm2(SDValue &N, SDValue &R);
72 inline bool SelectAnyImm3(SDValue &N, SDValue &R);
74 // Generate a machine instruction node corresponding to the circ/brev
75 // load intrinsic.
77 // Given the circ/brev load intrinsic and the already generated machine
78 // instruction, generate the appropriate store (that is a part of the
79 // intrinsic's functionality).
83 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
84 /// inline asm expressions.
86 InlineAsm::ConstraintCode ConstraintID,
87 std::vector<SDValue> &OutOps) override;
89 bool SelectBrevLdIntrinsic(SDNode *IntN);
91 void SelectLoad(SDNode *N);
92 void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
93 void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
94 void SelectStore(SDNode *N);
95 void SelectSHL(SDNode *N);
99 void SelectConstant(SDNode *N);
101 void SelectV65Gather(SDNode *N);
105 void SelectVAlign(SDNode *N);
107 void SelectTypecast(SDNode *N);
108 void SelectP2D(SDNode *N);
109 void SelectD2P(SDNode *N);
110 void SelectQ2V(SDNode *N);
111 void SelectV2Q(SDNode *N);
112 void SelectFDiv(SDNode *N);
113 void FDiv(SDNode *N);
114 void FastFDiv(SDNode *N);
116 // Include the declarations autogenerated from the selection patterns.
117 #define GET_DAGISEL_DECL
118 #include "HexagonGenDAGISel.inc"
121 // This is really only to get access to ReplaceNode (which is a protected
122 // member). Any other members used by HvxSelector can be moved around to
123 // make them accessible).
124 friend struct HvxSelector;
126 SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
127 SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
128 return SDValue(U, 0);
129 }
131 bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
132 bool isAlignedMemNode(const MemSDNode *N) const;
133 bool isSmallStackStore(const StoreSDNode *N) const;
134 bool isPositiveHalfWord(const SDNode *N) const;
135 bool hasOneUse(const SDNode *N) const;
137 // DAG preprocessing functions.
138 void PreprocessHvxISelDAG();
139 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
140 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
141 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
142 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
143 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
145 void SelectHvxExtractSubvector(SDNode *N);
146 void SelectHvxShuffle(SDNode *N);
147 void SelectHvxRor(SDNode *N);
148 void SelectHvxVAlign(SDNode *N);
150 // Function postprocessing.
151 void updateAligna();
153 SmallDenseMap<SDNode *,int> RootWeights;
154 SmallDenseMap<SDNode *,int> RootHeights;
155 SmallDenseMap<const Value *,int> GAUsesInFunction;
156 int getWeight(SDNode *N);
157 int getHeight(SDNode *N);
158 SDValue getMultiplierForSHL(SDNode *N);
159 SDValue factorOutPowerOf2(SDValue V, unsigned Power);
160 unsigned getUsesInFunction(const Value *V);
161 SDValue balanceSubTree(SDNode *N, bool Factorize = false);
162 void rebalanceAddressTrees();
163}; // end HexagonDAGToDAGISel
167 static char ID;
169 CodeGenOptLevel OptLevel);
amdgpu AMDGPU Register Bank Select
This class represents an Operation in the Expression.
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
bool SelectAnyImm2(SDValue &N, SDValue &R)
bool SelectAnyImm(SDValue &N, SDValue &R)
bool SelectAnyImm0(SDValue &N, SDValue &R)
bool runOnMachineFunction(MachineFunction &MF) override
bool SelectAnyImm1(SDValue &N, SDValue &R)
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectBrevLdIntrinsic(SDNode *IntN)
bool SelectAddrFI(SDValue &N, SDValue &R)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
bool SelectAddrGP(SDValue &N, SDValue &R)
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
bool SelectAnyImm3(SDValue &N, SDValue &R)
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectAddrGA(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel)
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
const HexagonInstrInfo * getInstrInfo() const override
const HexagonRegisterInfo * getRegisterInfo() const override
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
CodeGenOptLevel OptLevel
virtual bool runOnMachineFunction(MachineFunction &mf)
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
This class is used to represent ISD::STORE nodes.
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Code generation optimization level.
Definition: CodeGen.h:54
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39