12#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
13#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
26class HexagonInstrInfo;
27class HexagonRegisterInfo;
88 unsigned ConstraintID,
89 std::vector<SDValue> &OutOps)
override;
116 #define GET_DAGISEL_DECL
117 #include "HexagonGenDAGISel.inc"
130 bool keepsLowBits(
const SDValue &Val,
unsigned NumBits,
SDValue &Src);
131 bool isAlignedMemNode(
const MemSDNode *
N)
const;
133 bool isPositiveHalfWord(
const SDNode *
N)
const;
134 bool hasOneUse(
const SDNode *
N)
const;
137 void PreprocessHvxISelDAG();
138 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
139 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
140 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
141 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
142 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
144 void SelectHvxExtractSubvector(
SDNode *
N);
145 void SelectHvxShuffle(
SDNode *
N);
147 void SelectHvxVAlign(
SDNode *
N);
159 unsigned getUsesInFunction(
const Value *V);
161 void rebalanceAddressTrees();
amdgpu AMDGPU Register Bank Select
void SelectAddSubCarry(SDNode *N)
void SelectConstant(SDNode *N)
void SelectIntrinsicWOChain(SDNode *N)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
void SelectExtractSubvector(SDNode *N)
void SelectVAlign(SDNode *N)
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
bool SelectAnyImm2(SDValue &N, SDValue &R)
bool SelectAnyImm(SDValue &N, SDValue &R)
void SelectV65GatherPred(SDNode *N)
bool SelectAnyImm0(SDValue &N, SDValue &R)
void SelectSHL(SDNode *N)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void SelectIntrinsicWChain(SDNode *N)
void SelectV2Q(SDNode *N)
bool SelectAnyImm1(SDValue &N, SDValue &R)
void SelectConstantFP(SDNode *N)
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectBrevLdIntrinsic(SDNode *IntN)
void emitFunctionEntryCode() override
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOpt::Level OptLevel)
bool SelectAddrFI(SDValue &N, SDValue &R)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
bool SelectAddrGP(SDValue &N, SDValue &R)
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
void SelectFrameIndex(SDNode *N)
bool SelectAnyImm3(SDValue &N, SDValue &R)
void SelectStore(SDNode *N)
void SelectLoad(SDNode *N)
HexagonDAGToDAGISel()=delete
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectAddrGA(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
void SelectTypecast(SDNode *N)
void SelectD2P(SDNode *N)
void SelectVAlignAddr(SDNode *N)
void SelectP2D(SDNode *N)
void SelectV65Gather(SDNode *N)
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
void SelectHVXDualOutput(SDNode *N)
void SelectQ2V(SDNode *N)
const HexagonInstrInfo * getInstrInfo() const override
const HexagonRegisterInfo * getRegisterInfo() const override
This class is used to represent ISD::LOAD nodes.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
CodeGenOpt::Level OptLevel
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
This class is used to represent ISD::STORE nodes.
LLVM Value Representation.
Level
Code generation optimization level.
This is an optimization pass for GlobalISel generic memory operations.
This struct is a compact representation of a valid (non-zero power of two) alignment.