LLVM 18.0.0git
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1//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8// Hexagon specific code to select Hexagon machine instructions for
9// SelectionDAG operations.
15#include "HexagonSubtarget.h"
17#include "llvm/ADT/StringRef.h"
22#include <vector>
24namespace llvm {
25class MachineFunction;
26class HexagonInstrInfo;
27class HexagonRegisterInfo;
30 const HexagonSubtarget *HST;
31 const HexagonInstrInfo *HII;
32 const HexagonRegisterInfo *HRI;
34 static char ID;
40 : SelectionDAGISel(ID, tm, OptLevel), HST(nullptr), HII(nullptr),
41 HRI(nullptr) {}
44 // Reset the subtarget each time through.
46 HII = HST->getInstrInfo();
47 HRI = HST->getRegisterInfo();
49 updateAligna();
50 return true;
51 }
53 bool ComplexPatternFuncMutatesDAG() const override {
54 return true;
55 }
56 void PreprocessISelDAG() override;
57 void emitFunctionEntryCode() override;
59 void Select(SDNode *N) override;
61 // Complex Pattern Selectors.
62 inline bool SelectAddrGA(SDValue &N, SDValue &R);
63 inline bool SelectAddrGP(SDValue &N, SDValue &R);
64 inline bool SelectAnyImm(SDValue &N, SDValue &R);
65 inline bool SelectAnyInt(SDValue &N, SDValue &R);
66 bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment);
67 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment);
68 bool SelectAddrFI(SDValue &N, SDValue &R);
69 bool DetectUseSxtw(SDValue &N, SDValue &R);
71 inline bool SelectAnyImm0(SDValue &N, SDValue &R);
72 inline bool SelectAnyImm1(SDValue &N, SDValue &R);
73 inline bool SelectAnyImm2(SDValue &N, SDValue &R);
74 inline bool SelectAnyImm3(SDValue &N, SDValue &R);
76 // Generate a machine instruction node corresponding to the circ/brev
77 // load intrinsic.
79 // Given the circ/brev load intrinsic and the already generated machine
80 // instruction, generate the appropriate store (that is a part of the
81 // intrinsic's functionality).
85 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
86 /// inline asm expressions.
88 InlineAsm::ConstraintCode ConstraintID,
89 std::vector<SDValue> &OutOps) override;
91 bool SelectBrevLdIntrinsic(SDNode *IntN);
93 void SelectLoad(SDNode *N);
94 void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
95 void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
96 void SelectStore(SDNode *N);
97 void SelectSHL(SDNode *N);
101 void SelectConstant(SDNode *N);
103 void SelectV65Gather(SDNode *N);
107 void SelectVAlign(SDNode *N);
109 void SelectTypecast(SDNode *N);
110 void SelectP2D(SDNode *N);
111 void SelectD2P(SDNode *N);
112 void SelectQ2V(SDNode *N);
113 void SelectV2Q(SDNode *N);
115 // Include the declarations autogenerated from the selection patterns.
116 #define GET_DAGISEL_DECL
117 #include "HexagonGenDAGISel.inc"
120 // This is really only to get access to ReplaceNode (which is a protected
121 // member). Any other members used by HvxSelector can be moved around to
122 // make them accessible).
123 friend struct HvxSelector;
125 SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
126 SDNode *U = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy);
127 return SDValue(U, 0);
128 }
130 bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
131 bool isAlignedMemNode(const MemSDNode *N) const;
132 bool isSmallStackStore(const StoreSDNode *N) const;
133 bool isPositiveHalfWord(const SDNode *N) const;
134 bool hasOneUse(const SDNode *N) const;
136 // DAG preprocessing functions.
137 void PreprocessHvxISelDAG();
138 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
139 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
140 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
141 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
142 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
144 void SelectHvxExtractSubvector(SDNode *N);
145 void SelectHvxShuffle(SDNode *N);
146 void SelectHvxRor(SDNode *N);
147 void SelectHvxVAlign(SDNode *N);
149 // Function postprocessing.
150 void updateAligna();
152 SmallDenseMap<SDNode *,int> RootWeights;
153 SmallDenseMap<SDNode *,int> RootHeights;
154 SmallDenseMap<const Value *,int> GAUsesInFunction;
155 int getWeight(SDNode *N);
156 int getHeight(SDNode *N);
157 SDValue getMultiplierForSHL(SDNode *N);
158 SDValue factorOutPowerOf2(SDValue V, unsigned Power);
159 unsigned getUsesInFunction(const Value *V);
160 SDValue balanceSubTree(SDNode *N, bool Factorize = false);
161 void rebalanceAddressTrees();
162}; // end HexagonDAGToDAGISel
amdgpu AMDGPU Register Bank Select
This class represents an Operation in the Expression.
bool SelectNewCircIntrinsic(SDNode *IntN)
Generate a machine instruction node for the new circular buffer intrinsics.
bool tryLoadOfLoadIntrinsic(LoadSDNode *N)
void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl)
MachineSDNode * LoadInstrForLoadIntrinsic(SDNode *IntN)
bool SelectAnyImm2(SDValue &N, SDValue &R)
bool SelectAnyImm(SDValue &N, SDValue &R)
bool SelectAnyImm0(SDValue &N, SDValue &R)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool SelectAnyImm1(SDValue &N, SDValue &R)
bool DetectUseSxtw(SDValue &N, SDValue &R)
bool SelectBrevLdIntrinsic(SDNode *IntN)
bool SelectAddrFI(SDValue &N, SDValue &R)
SDNode * StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN)
bool SelectAddrGP(SDValue &N, SDValue &R)
bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment)
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment)
bool SelectAnyImm3(SDValue &N, SDValue &R)
bool SelectAnyInt(SDValue &N, SDValue &R)
bool SelectAddrGA(SDValue &N, SDValue &R)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Implement addressing mode selection for inline asm expressions.
HexagonDAGToDAGISel(HexagonTargetMachine &tm, CodeGenOptLevel OptLevel)
bool ComplexPatternFuncMutatesDAG() const override
Return true if complex patterns for this target can mutate the DAG.
void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl)
const HexagonInstrInfo * getInstrInfo() const override
const HexagonRegisterInfo * getRegisterInfo() const override
This class is used to represent ISD::LOAD nodes.
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
An SDNode that represents everything that will be needed to construct a MachineInstr.
This is an abstract virtual class for memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
MachineFunction * MF
CodeGenOptLevel OptLevel
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
This class is used to represent ISD::STORE nodes.
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Code generation optimization level.
Definition: CodeGen.h:54
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39