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15 #ifndef LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
16 #define LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
113 class M68kMachineFunctionInfo;
131 EVT VT)
const override;
161 std::pair<unsigned, const TargetRegisterClass *>
167 std::vector<SDValue> &Ops,
175 bool IsVarArg)
const;
181 unsigned GetAlignedArgumentStackSize(
unsigned StackSize,
189 SDValue Chain,
bool IsTailCall,
int FPDiff,
196 EVT PtrVT,
unsigned SlotSize,
int FPDiff,
203 unsigned ArgIdx)
const;
273 bool IsEligibleForTailCallOptimization(
275 bool IsCalleeStructRet,
bool IsCallerStructRet,
Type *RetTy,
284 #endif // LLVM_LIB_TARGET_M68K_M68KISELLOWERING_H
CCAssignFn * getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
@ Wrapper
A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
This is an optimization pass for GlobalISel generic memory operations.
@ BRCOND
M68k conditional branches.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
A parsed version of the target data layout string in and methods for querying it.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Context object for machine code objects.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned const TargetRegisterInfo * TRI
bool isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO)
Determines whether the callee is required to pop its own arguments.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
@ And
Bitwise or logical AND of integers.
CCValAssign - Represent assignment of one arg/retval to a location.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
(vector float) vec_cmpeq(*A, *B) C
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
@ FIRST_NUMBER
Start the numbering from where ISD NodeType finishes.
static const M68kTargetLowering * create(const M68kTargetMachine &TM, const M68kSubtarget &STI)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
Provide custom lowering hooks for some operations.
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ CMOV
M68k conditional moves.
Representation of each machine instruction.
This is an important class for using LLVM in a threaded context.
@ BTST
M68k bit-test instructions.
This structure contains all information that is necessary for lowering calls.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
EVT is not used in-tree, but is used by out-of-tree target.
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Helper struct shared between Function Specialization and SCCP Solver.
an instruction that atomically reads a memory location, combines it with another value,...
@ WrapperPC
Special wrapper used under M68k PIC mode for PC relative displacements.
amdgpu Simplify well known AMD library false FunctionCallee Callee
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ CMP
M68k compare and logical compare instructions.
M68kTargetLowering(const M68kTargetMachine &TM, const M68kSubtarget &STI)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the value type to use for ISD::SETCC.
ConstraintType getConstraintType(StringRef ConstraintStr) const override
Given a constraint, return the type of constraint it is for this target.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const char LLVMTargetMachineRef TM
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
NodeType
M68k Specific DAG nodes.
Base class for the full range of assembler expressions which are needed for parsing.