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X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
21 #include <vector>
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27 class MachineInstrBuilder;
28 class X86RegisterInfo;
29 class X86Subtarget;
30 
31 namespace X86 {
32 
34  // For instr that was compressed from EVEX to VEX.
36 };
37 
38 /// Return a pair of condition code for the given predicate and whether
39 /// the instruction operands should be swaped to match the condition code.
40 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
41 
42 /// Return a setcc opcode based on whether it has a memory operand.
43 unsigned getSETOpc(bool HasMemoryOperand = false);
44 
45 /// Return a cmov opcode for the given register size in bytes, and operand type.
46 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
47 
48 // Turn jCC instruction into condition code.
50 
51 // Turn setCC instruction into condition code.
53 
54 // Turn CMov instruction into condition code.
56 
57 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
58 /// e.g. turning COND_E to COND_NE.
60 
61 /// Get the VPCMP immediate for the given condition.
63 
64 /// Get the VPCMP immediate if the opcodes are swapped.
65 unsigned getSwappedVPCMPImm(unsigned Imm);
66 
67 /// Get the VPCOM immediate if the opcodes are swapped.
68 unsigned getSwappedVPCOMImm(unsigned Imm);
69 
70 } // namespace X86
71 
72 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
73 /// a reference to a stub for a global, not the global itself.
74 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
75  switch (TargetFlag) {
76  case X86II::MO_DLLIMPORT: // dllimport stub.
77  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
78  case X86II::MO_GOT: // normal GOT reference.
79  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
80  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
81  case X86II::MO_COFFSTUB: // COFF .refptr stub.
82  return true;
83  default:
84  return false;
85  }
86 }
87 
88 /// isGlobalRelativeToPICBase - Return true if the specified global value
89 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
90 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
91 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
92  switch (TargetFlag) {
93  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
94  case X86II::MO_GOT: // isPICStyleGOT: other global.
95  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
96  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
97  case X86II::MO_TLVP: // ??? Pretty sure..
98  return true;
99  default:
100  return false;
101  }
102 }
103 
104 inline static bool isScale(const MachineOperand &MO) {
105  return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
106  MO.getImm() == 4 || MO.getImm() == 8);
107 }
108 
109 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
110  if (MI.getOperand(Op).isFI())
111  return true;
112  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
113  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
115  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
116  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
117  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
118  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
119  MI.getOperand(Op + X86::AddrDisp).isJTI());
120 }
121 
122 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
123  if (MI.getOperand(Op).isFI())
124  return true;
125  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
126  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
127 }
128 
129 class X86InstrInfo final : public X86GenInstrInfo {
130  X86Subtarget &Subtarget;
131  const X86RegisterInfo RI;
132 
133  virtual void anchor();
134 
135  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
136  MachineBasicBlock *&FBB,
138  SmallVectorImpl<MachineInstr *> &CondBranches,
139  bool AllowModify) const;
140 
141 public:
142  explicit X86InstrInfo(X86Subtarget &STI);
143 
144  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
145  /// such, whenever a client has an instance of instruction info, it should
146  /// always be able to get register info as well (through this method).
147  ///
148  const X86RegisterInfo &getRegisterInfo() const { return RI; }
149 
150  /// Returns the stack pointer adjustment that happens inside the frame
151  /// setup..destroy sequence (e.g. by pushes, or inside the callee).
152  int64_t getFrameAdjustment(const MachineInstr &I) const {
153  assert(isFrameInstr(I));
154  if (isFrameSetup(I))
155  return I.getOperand(2).getImm();
156  return I.getOperand(1).getImm();
157  }
158 
159  /// Sets the stack pointer adjustment made inside the frame made up by this
160  /// instruction.
161  void setFrameAdjustment(MachineInstr &I, int64_t V) const {
162  assert(isFrameInstr(I));
163  if (isFrameSetup(I))
164  I.getOperand(2).setImm(V);
165  else
166  I.getOperand(1).setImm(V);
167  }
168 
169  /// getSPAdjust - This returns the stack pointer adjustment made by
170  /// this instruction. For x86, we need to handle more complex call
171  /// sequences involving PUSHes.
172  int getSPAdjust(const MachineInstr &MI) const override;
173 
174  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
175  /// extension instruction. That is, it's like a copy where it's legal for the
176  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
177  /// true, then it's expected the pre-extension value is available as a subreg
178  /// of the result register. This also returns the sub-register index in
179  /// SubIdx.
180  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
181  unsigned &DstReg, unsigned &SubIdx) const override;
182 
183  unsigned isLoadFromStackSlot(const MachineInstr &MI,
184  int &FrameIndex) const override;
185  unsigned isLoadFromStackSlot(const MachineInstr &MI,
186  int &FrameIndex,
187  unsigned &MemBytes) const override;
188  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
189  /// stack locations as well. This uses a heuristic so it isn't
190  /// reliable for correctness.
191  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
192  int &FrameIndex) const override;
193 
194  unsigned isStoreToStackSlot(const MachineInstr &MI,
195  int &FrameIndex) const override;
196  unsigned isStoreToStackSlot(const MachineInstr &MI,
197  int &FrameIndex,
198  unsigned &MemBytes) const override;
199  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
200  /// stack locations as well. This uses a heuristic so it isn't
201  /// reliable for correctness.
202  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
203  int &FrameIndex) const override;
204 
205  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
206  AliasAnalysis *AA) const override;
207  void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
208  unsigned DestReg, unsigned SubIdx,
209  const MachineInstr &Orig,
210  const TargetRegisterInfo &TRI) const override;
211 
212  /// Given an operand within a MachineInstr, insert preceding code to put it
213  /// into the right format for a particular kind of LEA instruction. This may
214  /// involve using an appropriate super-register instead (with an implicit use
215  /// of the original) or creating a new virtual register and inserting COPY
216  /// instructions to get the data into the right class.
217  ///
218  /// Reference parameters are set to indicate how caller should add this
219  /// operand to the LEA instruction.
220  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
221  unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
222  bool &isKill, MachineOperand &ImplicitOp,
223  LiveVariables *LV) const;
224 
225  /// convertToThreeAddress - This method must be implemented by targets that
226  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
227  /// may be able to convert a two-address instruction into a true
228  /// three-address instruction on demand. This allows the X86 target (for
229  /// example) to convert ADD and SHL instructions into LEA instructions if they
230  /// would require register copies due to two-addressness.
231  ///
232  /// This method returns a null pointer if the transformation cannot be
233  /// performed, otherwise it returns the new instruction.
234  ///
235  MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
236  MachineInstr &MI,
237  LiveVariables *LV) const override;
238 
239  /// Returns true iff the routine could find two commutable operands in the
240  /// given machine instruction.
241  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
242  /// input values can be re-defined in this method only if the input values
243  /// are not pre-defined, which is designated by the special value
244  /// 'CommuteAnyOperandIndex' assigned to it.
245  /// If both of indices are pre-defined and refer to some operands, then the
246  /// method simply returns true if the corresponding operands are commutable
247  /// and returns false otherwise.
248  ///
249  /// For example, calling this method this way:
250  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
251  /// findCommutedOpIndices(MI, Op1, Op2);
252  /// can be interpreted as a query asking to find an operand that would be
253  /// commutable with the operand#1.
254  bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
255  unsigned &SrcOpIdx2) const override;
256 
257  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
258  /// performs the same computations as the given \p MI but which has the
259  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
260  /// It may return 0 if it is unsafe to commute the operands.
261  /// Note that a machine instruction (instead of its opcode) is passed as the
262  /// first parameter to make it possible to analyze the instruction's uses and
263  /// commute the first operand of FMA even when it seems unsafe when you look
264  /// at the opcode. For example, it is Ok to commute the first operand of
265  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
266  ///
267  /// The returned FMA opcode may differ from the opcode in the given \p MI.
268  /// For example, commuting the operands #1 and #3 in the following FMA
269  /// FMA213 #1, #2, #3
270  /// results into instruction with adjusted opcode:
271  /// FMA231 #3, #2, #1
272  unsigned
273  getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
274  unsigned SrcOpIdx2,
275  const X86InstrFMA3Group &FMA3Group) const;
276 
277  // Branch analysis.
278  bool isUnpredicatedTerminator(const MachineInstr &MI) const override;
279  bool isUnconditionalTailCall(const MachineInstr &MI) const override;
280  bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
281  const MachineInstr &TailCall) const override;
282  void replaceBranchWithTailCall(MachineBasicBlock &MBB,
284  const MachineInstr &TailCall) const override;
285 
286  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
287  MachineBasicBlock *&FBB,
289  bool AllowModify) const override;
290 
291  bool getMemOperandWithOffset(const MachineInstr &LdSt,
292  const MachineOperand *&BaseOp,
293  int64_t &Offset,
294  const TargetRegisterInfo *TRI) const override;
295  bool analyzeBranchPredicate(MachineBasicBlock &MBB,
297  bool AllowModify = false) const override;
298 
299  unsigned removeBranch(MachineBasicBlock &MBB,
300  int *BytesRemoved = nullptr) const override;
301  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
303  const DebugLoc &DL,
304  int *BytesAdded = nullptr) const override;
305  bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
306  unsigned, unsigned, int &, int &, int &) const override;
307  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
308  const DebugLoc &DL, unsigned DstReg,
309  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
310  unsigned FalseReg) const override;
311  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
312  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
313  bool KillSrc) const override;
314  void storeRegToStackSlot(MachineBasicBlock &MBB,
315  MachineBasicBlock::iterator MI, unsigned SrcReg,
316  bool isKill, int FrameIndex,
317  const TargetRegisterClass *RC,
318  const TargetRegisterInfo *TRI) const override;
319 
320  void loadRegFromStackSlot(MachineBasicBlock &MBB,
321  MachineBasicBlock::iterator MI, unsigned DestReg,
322  int FrameIndex, const TargetRegisterClass *RC,
323  const TargetRegisterInfo *TRI) const override;
324 
325  bool expandPostRAPseudo(MachineInstr &MI) const override;
326 
327  /// Check whether the target can fold a load that feeds a subreg operand
328  /// (or a subreg operand that feeds a store).
329  bool isSubregFoldable() const override { return true; }
330 
331  /// foldMemoryOperand - If this target supports it, fold a load or store of
332  /// the specified stack slot into the specified machine instruction for the
333  /// specified operand(s). If this is possible, the target should perform the
334  /// folding and return true, otherwise it should return false. If it folds
335  /// the instruction, it is likely that the MachineInstruction the iterator
336  /// references has been changed.
337  MachineInstr *
338  foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
339  ArrayRef<unsigned> Ops,
340  MachineBasicBlock::iterator InsertPt, int FrameIndex,
341  LiveIntervals *LIS = nullptr,
342  VirtRegMap *VRM = nullptr) const override;
343 
344  /// foldMemoryOperand - Same as the previous version except it allows folding
345  /// of any load and store from / to any address, not just from a specific
346  /// stack slot.
347  MachineInstr *foldMemoryOperandImpl(
349  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
350  LiveIntervals *LIS = nullptr) const override;
351 
352  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
353  /// a store or a load and a store into two or more instruction. If this is
354  /// possible, returns true as well as the new instructions by reference.
355  bool
356  unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
357  bool UnfoldLoad, bool UnfoldStore,
358  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
359 
360  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
361  SmallVectorImpl<SDNode *> &NewNodes) const override;
362 
363  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
364  /// instruction after load / store are unfolded from an instruction of the
365  /// specified opcode. It returns zero if the specified unfolding is not
366  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
367  /// index of the operand which will hold the register holding the loaded
368  /// value.
369  unsigned
370  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
371  unsigned *LoadRegIndex = nullptr) const override;
372 
373  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
374  /// to determine if two loads are loading from the same base address. It
375  /// should only return true if the base pointers are the same and the
376  /// only differences between the two addresses are the offset. It also returns
377  /// the offsets by reference.
378  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
379  int64_t &Offset2) const override;
380 
381  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
382  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
383  /// should be scheduled togther. On some targets if two loads are loading from
384  /// addresses in the same cache line, it's better if they are scheduled
385  /// together. This function takes two integers that represent the load offsets
386  /// from the common base address. It returns true if it decides it's desirable
387  /// to schedule the two loads together. "NumLoads" is the number of loads that
388  /// have already been scheduled after Load1.
389  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
390  int64_t Offset2,
391  unsigned NumLoads) const override;
392 
393  void getNoop(MCInst &NopInst) const override;
394 
395  bool
396  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
397 
398  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
399  /// instruction that defines the specified register class.
400  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
401 
402  /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
403  /// would clobber the EFLAGS condition register. Note the result may be
404  /// conservative. If it cannot definitely determine the safety after visiting
405  /// a few instructions in each direction it assumes it's not safe.
408  return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) ==
410  }
411 
412  /// True if MI has a condition code def, e.g. EFLAGS, that is
413  /// not marked dead.
414  bool hasLiveCondCodeDef(MachineInstr &MI) const;
415 
416  /// getGlobalBaseReg - Return a virtual register initialized with the
417  /// the global base register value. Output instructions required to
418  /// initialize the register in the function entry block, if necessary.
419  ///
420  unsigned getGlobalBaseReg(MachineFunction *MF) const;
421 
422  std::pair<uint16_t, uint16_t>
423  getExecutionDomain(const MachineInstr &MI) const override;
424 
425  uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
426 
427  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
428 
429  bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
430 
431  unsigned
432  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
433  const TargetRegisterInfo *TRI) const override;
434  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
435  const TargetRegisterInfo *TRI) const override;
436  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
437  const TargetRegisterInfo *TRI) const override;
438 
439  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
440  unsigned OpNum,
443  unsigned Size, unsigned Alignment,
444  bool AllowCommute) const;
445 
446  bool isHighLatencyDef(int opc) const override;
447 
448  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
449  const MachineRegisterInfo *MRI,
450  const MachineInstr &DefMI, unsigned DefIdx,
451  const MachineInstr &UseMI,
452  unsigned UseIdx) const override;
453 
454  bool useMachineCombiner() const override { return true; }
455 
456  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
457 
458  bool hasReassociableOperands(const MachineInstr &Inst,
459  const MachineBasicBlock *MBB) const override;
460 
461  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
462  MachineInstr &NewMI1,
463  MachineInstr &NewMI2) const override;
464 
465  /// analyzeCompare - For a comparison instruction, return the source registers
466  /// in SrcReg and SrcReg2 if having two register operands, and the value it
467  /// compares against in CmpValue. Return true if the comparison instruction
468  /// can be analyzed.
469  bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
470  unsigned &SrcReg2, int &CmpMask,
471  int &CmpValue) const override;
472 
473  /// optimizeCompareInstr - Check if there exists an earlier instruction that
474  /// operates on the same source operands and sets flags in the same way as
475  /// Compare; remove Compare if possible.
476  bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
477  unsigned SrcReg2, int CmpMask, int CmpValue,
478  const MachineRegisterInfo *MRI) const override;
479 
480  /// optimizeLoadInstr - Try to remove the load by folding it to a register
481  /// operand at the use. We fold the load instructions if and only if the
482  /// def and use are in the same BB. We only look at one load and see
483  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
484  /// defined by the load we are trying to fold. DefMI returns the machine
485  /// instruction that defines FoldAsLoadDefReg, and the function returns
486  /// the machine instruction generated due to folding.
487  MachineInstr *optimizeLoadInstr(MachineInstr &MI,
488  const MachineRegisterInfo *MRI,
489  unsigned &FoldAsLoadDefReg,
490  MachineInstr *&DefMI) const override;
491 
492  std::pair<unsigned, unsigned>
493  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
494 
496  getSerializableDirectMachineOperandTargetFlags() const override;
497 
498  virtual outliner::OutlinedFunction getOutliningCandidateInfo(
499  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
500 
501  bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
502  bool OutlineFromLinkOnceODRs) const override;
503 
505  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
506 
507  void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
508  const outliner::OutlinedFunction &OF) const override;
509 
511  insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
513  const outliner::Candidate &C) const override;
514 
515 #define GET_INSTRINFO_HELPER_DECLS
516 #include "X86GenInstrInfo.inc"
517 
518  static bool hasLockPrefix(const MachineInstr &MI) {
519  return MI.getDesc().TSFlags & X86II::LOCK;
520  }
521 
523  describeLoadedValue(const MachineInstr &MI) const override;
524 
525 protected:
526  /// Commutes the operands in the given instruction by changing the operands
527  /// order and/or changing the instruction's opcode and/or the immediate value
528  /// operand.
529  ///
530  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
531  /// to be commuted.
532  ///
533  /// Do not call this method for a non-commutable instruction or
534  /// non-commutable operands.
535  /// Even though the instruction is commutable, the method may still
536  /// fail to commute the operands, null pointer is returned in such cases.
537  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
538  unsigned CommuteOpIdx1,
539  unsigned CommuteOpIdx2) const override;
540 
541  /// If the specific machine instruction is a instruction that moves/copies
542  /// value from one register to another register return true along with
543  /// @Source machine operand and @Destination machine operand.
544  bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
545  const MachineOperand *&Destination) const override;
546 
547 private:
548  /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
549  /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
550  /// super-register and then truncating back down to a 8/16-bit sub-register.
551  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
553  MachineInstr &MI,
554  LiveVariables *LV,
555  bool Is8BitOp) const;
556 
557  /// Handles memory folding for special case instructions, for instance those
558  /// requiring custom manipulation of the address.
559  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
560  unsigned OpNum,
563  unsigned Size, unsigned Align) const;
564 
565  /// isFrameOperand - Return true and the FrameIndex if the specified
566  /// operand and follow operands form a reference to the stack frame.
567  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
568  int &FrameIndex) const;
569 
570  /// Returns true iff the routine could find two commutable operands in the
571  /// given machine instruction with 3 vector inputs.
572  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
573  /// input values can be re-defined in this method only if the input values
574  /// are not pre-defined, which is designated by the special value
575  /// 'CommuteAnyOperandIndex' assigned to it.
576  /// If both of indices are pre-defined and refer to some operands, then the
577  /// method simply returns true if the corresponding operands are commutable
578  /// and returns false otherwise.
579  ///
580  /// For example, calling this method this way:
581  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
582  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
583  /// can be interpreted as a query asking to find an operand that would be
584  /// commutable with the operand#1.
585  ///
586  /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
587  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
588  unsigned &SrcOpIdx1,
589  unsigned &SrcOpIdx2,
590  bool IsIntrinsic = false) const;
591 };
592 
593 } // namespace llvm
594 
595 #endif
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:161
uint64_t CallInst * C
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:104
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:275
This class represents lattice values for constants.
Definition: AllocatorList.h:23
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, unsigned Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before...
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
This class is used to group {132, 213, 231} forms of FMA opcodes together.
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
CondCode getCondFromCMov(const MachineInstr &MI)
Return condition code of a CMov opcode.
unsigned Reg
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isCPI() const
isCPI - Tests if this is a MO_ConstantPoolIndex operand.
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:147
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
An individual sequence of instructions to be replaced with a call to an outlined function.
Represents a predicate at the MachineFunction level.
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:247
Provide an instruction scheduling machine model to CodeGen passes.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:414
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:74
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:122
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:91
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:132
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:109
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:242
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given register size in bytes, and operand type.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
unsigned const MachineRegisterInfo * MRI
InstrType
Represents how an instruction should be mapped by the outliner.
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:253
MachineInstrBuilder & UseMI
The information necessary to create an outlined function for some class of candidate.
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:518
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
Register is known to be fully dead.
CondCode getCondFromSETCC(const MachineInstr &MI)
Return condition code of a SETCC opcode.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:732
void setImm(int64_t immVal)
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:454
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:40
CondCode getCondFromBranch(const MachineInstr &MI)
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e...
Definition: X86InstrInfo.h:152
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:148
Represents one node in the SelectionDAG.
int64_t getImm() const
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:329
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:64
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:139
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
uint32_t Size
Definition: Profile.cpp:46
unsigned getSETOpc(bool HasMemoryOperand=false)
Return a setcc opcode based on whether it has a memory operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const
isSafeToClobberEFLAGS - Return true if it&#39;s safe insert an instruction tha would clobber the EFLAGS c...
Definition: X86InstrInfo.h:406
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:125
IRTranslator LLVM IR MI
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:237