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LLVM 22.0.0git
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#include "Target/X86/X86InstrInfo.h"
Static Public Member Functions | |
| static bool | isDataInvariant (MachineInstr &MI) |
| Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands. | |
| static bool | isDataInvariantLoad (MachineInstr &MI) |
| Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands. | |
| static bool | hasLockPrefix (const MachineInstr &MI) |
Protected Member Functions | |
| MachineInstr * | commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override |
| std::optional< DestSourcePair > | isCopyInstrImpl (const MachineInstr &MI) const override |
| bool | getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override |
| void | genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override |
| When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence. | |
| bool | accumulateInstrSeqToRootLatency (MachineInstr &Root) const override |
| When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency. | |
| void | getFrameIndexOperands (SmallVectorImpl< MachineOperand > &Ops, int FI) const override |
Definition at line 224 of file X86InstrInfo.h.
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Definition at line 86 of file X86InstrInfo.cpp.
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When calculate the latency of the root instruction, accumulate the latency of the sequence to the root latency.
| Root | - Instruction that could be combined with one of its operands For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd is not in the critical path, so the root latency only include vpmaddwd. |
Definition at line 693 of file X86InstrInfo.h.
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Definition at line 3938 of file X86InstrInfo.cpp.
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Definition at line 4006 of file X86InstrInfo.cpp.
References assert(), Cond, llvm::X86::COND_E, llvm::X86::COND_NE, llvm::MachineOperand::CreateImm(), llvm::drop_begin(), llvm::ilist_node_with_parent< NodeTy, ParentTy, Options >::getNextNode(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getRegisterInfo(), llvm::MachineOperand::isIdenticalTo(), MBB, MI, llvm::reverse(), llvm::MachineBasicBlock::successors(), and TRI.
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Definition at line 4829 of file X86InstrInfo.cpp.
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Definition at line 8777 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::X86::AddrSegmentReg, llvm::SDNode::getMachineOpcode(), llvm::SDNode::getOperand(), I, and llvm::SDNode::isMachineOpcode().
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Definition at line 7138 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::get(), llvm::getX86SubSuperRegister(), llvm::X86Subtarget::hasAVX(), llvm::X86II::hasNewDataDest(), llvm::RegState::ImplicitDefine, MI, Opc, TRI, and llvm::RegState::Undef.
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Definition at line 10744 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), DL, llvm::get(), llvm::MachineBasicBlock::getParent(), getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::getX86SubSuperRegister(), MBB, TRI, and llvm::RegState::Undef.
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Definition at line 10714 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, and MBB.
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Definition at line 4156 of file X86InstrInfo.cpp.
References llvm::X86Subtarget::canUseCMOV(), Cond, llvm::getImm(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::X86::LAST_VALID_COND, MBB, and MRI.
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Definition at line 3702 of file X86InstrInfo.cpp.
References assert(), llvm::TargetMachine::getCodeModel(), llvm::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getTCReturnAddrDelta(), llvm::MachineFunction::hasWinCFI(), llvm::X86Subtarget::isTargetWin64(), llvm::CodeModel::Kernel, llvm::X86::LAST_VALID_COND, and llvm::SmallVectorBase< Size_T >::size().
Referenced by replaceBranchWithTailCall().
| bool X86InstrInfo::classifyLEAReg | ( | MachineInstr & | MI, |
| const MachineOperand & | Src, | ||
| unsigned | LEAOpcode, | ||
| bool | AllowSP, | ||
| Register & | NewSrc, | ||
| unsigned & | NewSrcSubReg, | ||
| bool & | isKill, | ||
| MachineOperand & | ImplicitOp, | ||
| LiveVariables * | LV, | ||
| LiveIntervals * | LIS | ||
| ) | const |
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction.
This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class.
Reference parameters are set to indicate how caller should add this operand to the LEA instruction.
Definition at line 1145 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::LiveRange::Segment::end, llvm::get(), llvm::SlotIndex::getBaseIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineFunction::getRegInfo(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), llvm::getX86SubSuperRegister(), Idx, llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::Register::isPhysical(), llvm::Register::isValid(), llvm::Register::isVirtual(), MI, Opc, llvm::LiveVariables::replaceKillInstruction(), llvm::MachineOperand::setImplicit(), SubReg, and llvm::RegState::Undef.
Referenced by convertToThreeAddress().
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Definition at line 2291 of file X86InstrInfo.cpp.
References llvm::MachineInstr::addOperand(), assert(), CASE_ND, llvm::TargetInstrInfo::commuteInstructionImpl(), commuteVPTERNLOG(), llvm::countr_zero(), llvm::MachineOperand::CreateImm(), FROM_TO_SIZE, llvm::get(), getCommutedVPERMV3Opcode(), llvm::getFMA3Group(), getFMA3OpcodeToCommuteOperands(), llvm::MachineInstr::getOperand(), llvm::X86::GetOppositeBranchCondition(), llvm::X86::getSwappedVCMPImm(), llvm::X86::getSwappedVPCMPImm(), llvm::X86::getSwappedVPCOMImm(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), isCommutableVPERMV3Instruction(), llvm_unreachable, MI, Opc, llvm::popcount(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setImm(), and Size.
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convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.
FIXME: Support these similar to ADD8ri/ADD16ri*.
Definition at line 1406 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addReg(), llvm::addRegReg(), assert(), llvm::BuildMI(), CASE_NF, classifyLEAReg(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineOperand::CreateReg(), llvm::get(), llvm::LiveIntervals::getInterval(), llvm::getKillRegState(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), getTruncatedShiftCount(), llvm::LiveVariables::getVarInfo(), hasLiveCondCodeDef(), I, llvm::MachineBasicBlock::insert(), isTruncatedShiftCountForLEA(), llvm::LiveVariables::VarInfo::Kills, llvm_unreachable, MBB, MI, Opc, llvm::LiveVariables::replaceKillInstruction(), and llvm::LiveIntervals::ReplaceMachineInstrInMaps().
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Definition at line 4297 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), CopyToFromAsymmetricReg(), llvm::dbgs(), DL, llvm::get(), llvm::getKillRegState(), getRegisterInfo(), llvm::X86Subtarget::hasAVX(), isHReg(), LLVM_DEBUG, MBB, MI, Opc, llvm::report_fatal_error(), and TRI.
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Definition at line 10314 of file X86InstrInfo.cpp.
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Definition at line 10135 of file X86InstrInfo.cpp.
References llvm::DIExpression::appendExt(), llvm::DIExpression::appendOffset(), assert(), contains(), llvm::MachineOperand::CreateImm(), llvm::TargetInstrInfo::describeLoadedValue(), describeMOVrrLoadedValue(), llvm::MDNode::get(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::MachineOperand::isFI(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), MI, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.
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Definition at line 6162 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Expand2AddrKreg(), Expand2AddrUndef(), expandLoadStackGuard(), expandMOV32r1(), ExpandMOVImmSExti8(), expandMOVSHP(), expandNOVLXLoad(), expandNOVLXStore(), expandSHXDROT(), expandXorFP(), llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), getRegisterInfo(), llvm::getRegState(), llvm::X86Subtarget::hasAVX(), llvm::RegState::ImplicitDefine, MBB, MI, Opc, llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsUndef(), llvm::MachineOperand::setReg(), TRI, and llvm::RegState::Undef.
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Returns true iff the routine could find two commutable operands in the given machine instruction.
The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise.
For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Definition at line 2801 of file X86InstrInfo.cpp.
References llvm::X86II::EncodingMask, llvm::X86II::EVEX, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::getFMA3Group(), llvm::X86Subtarget::hasSSE2(), llvm::X86Subtarget::hasSSE41(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm::X86II::isKMasked(), llvm::X86II::isKMergeMasked(), MI, and llvm::MCOI::TIED_TO.
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foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction.
Definition at line 5925 of file X86InstrInfo.cpp.
References DefMI, getConstValDefinedInReg(), MRI, and UseMI.
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Fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s).
If folding happens, it is likely that the referenced instruction has been changed.
Definition at line 7589 of file X86InstrInfo.cpp.
References llvm::MachineOperand::CreateFI(), foldMemoryOperandImpl(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::X86::getNonNDVariant(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineOperand::getSubReg(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), llvm::MachineOperand::isDef(), MI, NoFusing, Opc, shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), Size, and SubReg.
Referenced by foldMemoryOperandImpl().
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Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 8104 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::SmallVectorImpl< T >::append(), llvm::CallingConv::C, llvm::MachineOperand::CreateCPI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), FOLD_BROADCAST, foldMemoryOperandImpl(), llvm::get(), llvm::FixedVectorType::get(), llvm::getAlign(), llvm::Constant::getAllOnesValue(), llvm::TargetMachine::getCodeModel(), llvm::MachineFunction::getConstantPool(), llvm::MachineConstantPool::getConstantPoolIndex(), llvm::Function::getContext(), llvm::MachineInstr::getDesc(), llvm::Type::getDoubleTy(), llvm::Type::getFloatTy(), llvm::Type::getFP128Ty(), llvm::MachineFunction::getFunction(), llvm::Type::getHalfTy(), llvm::Type::getInt32Ty(), llvm::Constant::getNullValue(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getTarget(), llvm::X86II::hasNewDataDest(), llvm::MachineInstr::hasOneMemOperand(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), isLoadFromStackSlot(), llvm::isMemInstrWithGOTPCREL(), isNonFoldablePartialRegisterLoad(), llvm::TargetMachine::isPositionIndependent(), llvm::CodeModel::Large, llvm::MachineInstr::memoperands_begin(), MI, NoFusing, llvm::MachineInstr::operands_begin(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), and X86EnableAPXForRelocation.
| MachineInstr * X86InstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr & | MI, | ||
| unsigned | OpNum, | ||
| ArrayRef< MachineOperand > | MOs, | ||
| MachineBasicBlock::iterator | InsertPt, | ||
| unsigned | Size, | ||
| Align | Alignment, | ||
| bool | AllowCommute | ||
| ) | const |
Definition at line 7459 of file X86InstrInfo.cpp.
References llvm::X86::AddrDisp, llvm::X86::AddrNumOperands, foldMemoryOperandImpl(), fuseInst(), fuseTwoAddrInst(), llvm::MachineFunction::getFunction(), llvm::X86::getNonNDVariant(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::Function::hasMinSize(), llvm::Function::hasOptSize(), hasPartialRegUpdate(), I, llvm::Register::isPhysical(), llvm::lookupFoldTable(), llvm::lookupTwoAddrFoldTable(), MI, llvm::X86II::MO_GOT_ABSOLUTE_ADDRESS, llvm::X86II::MO_GOTTPOFF, Opc, printFailMsgforFold(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), shouldPreventUndefRegUpdateMemFold(), llvm::ArrayRef< T >::size(), Size, llvm::TB_ALIGN_MASK, llvm::TB_ALIGN_SHIFT, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and TRI.
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When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions that could replace the original code sequence.
Definition at line 10931 of file X86InstrInfo.cpp.
References llvm::DPWSSD, llvm::TargetInstrInfo::genAlternativeCodeSequence(), and genAlternativeDpCodeSequence().
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Definition at line 4549 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Displacement, llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::MachineInstr::getOperand(), llvm::X86II::getOperandBias(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::ExtAddrMode::Scale, and llvm::ExtAddrMode::ScaledReg.
Referenced by verifyInstruction().
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Definition at line 4604 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), MI, and MRI.
Referenced by foldImmediate().
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Definition at line 9326 of file X86InstrInfo.cpp.
References getExecutionDomainCustom(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX512(), MI, and llvm::X86II::SSEDomainShift.
| uint16_t X86InstrInfo::getExecutionDomainCustom | ( | const MachineInstr & | MI | ) | const |
Definition at line 9060 of file X86InstrInfo.cpp.
References AdjustBlendMask(), llvm::X86Subtarget::hasAVX2(), and MI.
Referenced by getExecutionDomain().
| unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands | ( | const MachineInstr & | MI, |
| unsigned | SrcOpIdx1, | ||
| unsigned | SrcOpIdx2, | ||
| const X86InstrFMA3Group & | FMA3Group | ||
| ) | const |
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given MI but which has the operands SrcOpIdx1 and SrcOpIdx2 commuted.
It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
The returned FMA opcode may differ from the opcode in the given MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1
Definition at line 2082 of file X86InstrInfo.cpp.
References assert(), llvm::X86InstrFMA3Group::get132Opcode(), llvm::X86InstrFMA3Group::get213Opcode(), llvm::X86InstrFMA3Group::get231Opcode(), getThreeSrcCommuteCase(), llvm::X86InstrFMA3Group::isIntrinsic(), llvm_unreachable, MI, and Opc.
Referenced by commuteInstructionImpl().
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Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g.
by pushes, or inside the callee).
Definition at line 262 of file X86InstrInfo.h.
Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), getSPAdjust(), and llvm::X86FrameLowering::spillFPBP().
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Definition at line 10950 of file X86InstrInfo.cpp.
References llvm::X86AddressMode::FrameIndexBase.
| Register X86InstrInfo::getGlobalBaseReg | ( | MachineFunction * | MF | ) | const |
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Return a virtual register initialized with the the global base register value.
Output instructions required to initialize the register in the function entry block, if necessary.
Output instructions required to initialize the register in the function entry block, if necessary.
TODO: Eliminate this and move the code to X86MachineFunctionInfo.
Definition at line 8993 of file X86InstrInfo.cpp.
References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::X86MachineFunctionInfo::getGlobalBaseReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), and llvm::X86MachineFunctionInfo::setGlobalBaseReg().
Referenced by X86SelectAddress().
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Definition at line 3973 of file X86InstrInfo.cpp.
References llvm::Add, getJumpTableIndexFromAddr(), getJumpTableIndexFromReg(), llvm::MachineFunction::getRegInfo(), MI, and MRI.
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Definition at line 10809 of file X86InstrInfo.cpp.
References llvm::DPWSSD, llvm::TargetInstrInfo::getMachineCombinerPatterns(), llvm::MachineInstr::getOpcode(), Opc, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 4674 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineOperand::getImm(), llvm::X86II::getMemoryOperandNo(), llvm::X86II::getOperandBias(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::Offset, llvm::LocationSize::precise(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Return the noop instruction to use for a noop.
Definition at line 9423 of file X86InstrInfo.cpp.
References llvm::MCInst::setOpcode().
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Definition at line 8760 of file X86InstrInfo.cpp.
References I, llvm::lookupUnfoldTable(), Opc, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, and llvm::TB_INDEX_MASK.
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Definition at line 10596 of file X86InstrInfo.cpp.
References llvm::CallingConv::C, I, MachineOutlinerDefault, MachineOutlinerTailCall, and MI.
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Definition at line 10676 of file X86InstrInfo.cpp.
References llvm::outliner::Illegal, llvm::outliner::Legal, and MI.
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Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register update.
Definition at line 6741 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getReg(), llvm::X86II::hasNewDataDest(), hasPartialRegUpdate(), MI, PartialRegUpdateClearance, llvm::MachineOperand::readsReg(), and TRI.
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Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL.
Returned register class may be different from the definition in the TD file, e.g. GR*RegClass (definition in TD file) -> GR*_NOREX2RegClass (Returned register class)
Definition at line 95 of file X86InstrInfo.cpp.
References llvm::X86II::canUseApxExtendedReg(), llvm::X86RegisterInfo::constrainRegClassToNonRex2(), llvm::TargetInstrInfo::getRegClass(), llvm::X86Subtarget::getRegisterInfo(), and TRI.
Referenced by foldMemoryOperandImpl(), and unfoldMemoryOperand().
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getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).
Definition at line 258 of file X86InstrInfo.h.
Referenced by analyzeBranchPredicate(), buildClearRegister(), copyPhysReg(), describeLoadedValue(), expandPostRAPseudo(), llvm::X86Subtarget::getRegisterInfo(), optimizeCompareInstr(), and replaceBranchWithTailCall().
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Definition at line 10319 of file X86InstrInfo.cpp.
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getSPAdjust - This returns the stack pointer adjustment made by this instruction.
For x86, we need to handle more complex call sequences involving PUSHes.
Definition at line 411 of file X86InstrInfo.cpp.
References llvm::alignTo(), llvm::MachineBasicBlock::end(), getFrameAdjustment(), llvm::TargetSubtargetInfo::getFrameLowering(), llvm::TargetFrameLowering::getStackAlign(), llvm::MachineFunction::getSubtarget(), I, MBB, and MI.
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Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register reads.
This catches the VCVTSI2SD family of instructions:
vcvtsi2sdq rax, undef xmm0, xmm14
We should to be careful not to catch VXOR idioms which are presumably handled specially in the pipeline:
vxorps undef xmm1, undef xmm1, xmm1
Like getPartialRegUpdateClearance, this makes a strong assumption that the high bits that are passed-through are not live.
Definition at line 7129 of file X86InstrInfo.cpp.
References llvm::MachineOperand::getReg(), hasUndefRegUpdate(), llvm::Register::isPhysical(), MI, and UndefRegClearance.
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Returns true if we have preference on the operands order in MI, the commute decision is returned in Commute.
Definition at line 3126 of file X86InstrInfo.cpp.
References isConvertibleLEA(), MI, and MRI.
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Definition at line 9740 of file X86InstrInfo.cpp.
References DefMI, and isHighLatencyDef().
| bool X86InstrInfo::hasLiveCondCodeDef | ( | MachineInstr & | MI | ) | const |
True if MI has a condition code def, e.g.
True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
EFLAGS, that is not marked dead.
Definition at line 996 of file X86InstrInfo.cpp.
References MI.
Referenced by convertToThreeAddress().
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Definition at line 660 of file X86InstrInfo.h.
References llvm::X86II::LOCK, and MI.
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Definition at line 9749 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineInstr::getNumDefs(), llvm::MachineInstr::getNumExplicitDefs(), llvm::MachineInstr::getNumExplicitOperands(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::MachineOperand::isDead(), and MBB.
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Definition at line 4098 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, llvm::X86::COND_E_AND_NP, llvm::X86::COND_NE, llvm::X86::COND_NE_OR_P, llvm::X86::COND_NP, llvm::X86::COND_P, DL, llvm::get(), getFallThroughMBB(), llvm::getImm(), MBB, and TBB.
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Definition at line 9416 of file X86InstrInfo.cpp.
References llvm::BuildMI(), DL, llvm::get(), MBB, and MI.
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Definition at line 10727 of file X86InstrInfo.cpp.
References llvm::BuildMI(), llvm::CallingConv::C, llvm::get(), llvm::MachineFunction::getName(), llvm::MachineBasicBlock::insert(), MachineOutlinerTailCall, and MBB.
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Definition at line 4193 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::X86::getCMovOpcode(), llvm::getImm(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, MRI, Opc, and TRI.
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Definition at line 9773 of file X86InstrInfo.cpp.
References CASE_ND, llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), and llvm::MachineInstr::getOpcode().
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isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 111 of file X86InstrInfo.cpp.
References llvm_unreachable, and MI.
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Definition at line 4385 of file X86InstrInfo.cpp.
References MI.
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Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands.
Instructions are considered data invariant even if they set EFLAGS.
A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.
FIXME: This should become part of our instruction tables.
Definition at line 161 of file X86InstrInfo.cpp.
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Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands.
For example, if the latency of the instruction is dependent on the particular bits set in any of the registers or any of the bits loaded from memory.
Instructions are considered data invariant even if they set EFLAGS.
A classical example of something that is inherently not data invariant is an indirect jump – the destination is loaded into icache based on the bits set in the jump destination register.
FIXME: This should become part of our instruction tables.
Definition at line 228 of file X86InstrInfo.cpp.
References MI.
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Definition at line 10653 of file X86InstrInfo.cpp.
References F, llvm::X86Subtarget::getFrameLowering(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::X86MachineFunctionInfo::getUsesRedZone(), and llvm::X86FrameLowering::has128ByteRedZone().
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Definition at line 9429 of file X86InstrInfo.cpp.
Referenced by hasHighOperandLatency().
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Definition at line 676 of file X86InstrInfo.cpp.
References llvm::TypeSize::getZero(), isLoadFromStackSlot(), and MI.
Referenced by foldMemoryOperandImpl(), isLoadFromStackSlot(), and isLoadFromStackSlotPostFE().
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Definition at line 682 of file X86InstrInfo.cpp.
References isFrameLoadOpcode(), and MI.
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isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 691 of file X86InstrInfo.cpp.
References Accesses, llvm::TypeSize::getZero(), isFrameLoadOpcode(), isLoadFromStackSlot(), and MI.
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Definition at line 758 of file X86InstrInfo.cpp.
References llvm::X86::AddrBaseReg, llvm::X86::AddrDisp, llvm::X86::AddrIndexReg, llvm::X86::AddrScaleAmt, llvm::MachineFunction::getRegInfo(), llvm::TargetInstrInfo::isReallyTriviallyReMaterializable(), llvm_unreachable, MI, MRI, regIsPICBase(), and ReMatPICStubLoad.
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Definition at line 8978 of file X86InstrInfo.cpp.
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Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled.
Definition at line 8952 of file X86InstrInfo.cpp.
References llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, llvm::TargetInstrInfo::isSchedulingBoundary(), MBB, and MI.
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Definition at line 709 of file X86InstrInfo.cpp.
References llvm::TypeSize::getZero(), isStoreToStackSlot(), and MI.
Referenced by llvm::X86FrameLowering::emitPrologue(), isStoreToStackSlot(), and isStoreToStackSlotPostFE().
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Definition at line 715 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, isFrameStoreOpcode(), and MI.
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isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
This uses a heuristic so it isn't reliable for correctness.
Definition at line 725 of file X86InstrInfo.cpp.
References Accesses, llvm::X86::AddrNumOperands, llvm::TypeSize::getZero(), isFrameStoreOpcode(), isStoreToStackSlot(), and MI.
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Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).
Definition at line 491 of file X86InstrInfo.h.
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Definition at line 3687 of file X86InstrInfo.cpp.
References MI.
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Definition at line 4808 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), assert(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), getLoadRegOpcode(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlign(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, Opc, llvm::MachineInstrBuilder::setMIFlag(), and TRI.
Referenced by llvm::X86FrameLowering::restoreCalleeSavedRegisters().
| void X86InstrInfo::loadStoreTileReg | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | Opc, | ||
| Register | Reg, | ||
| int | FrameIdx, | ||
| bool | isKill = false |
||
| ) | const |
Definition at line 4745 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrIndexReg, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::get(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm_unreachable, MBB, MI, Opc, llvm::MachineOperand::setIsKill(), and llvm::MachineOperand::setReg().
Referenced by loadRegFromStackSlot(), and storeRegToStackSlot().
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Check if there exists an earlier instruction that operates on the same source operands and sets eflags in the same way as CMP and remove CMP if possible.
Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.
Definition at line 5282 of file X86InstrInfo.cpp.
References llvm::MachineBasicBlock::addLiveIn(), assert(), llvm::BitWidth, CASE_ND, llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_S, llvm::MachineInstr::dropDebugNumber(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), findRedundantFlagInstr(), From, FROM_TO, llvm::get(), llvm::X86::getCondFromMI(), llvm::APInt::getMaxValue(), llvm::X86::getNFVariant(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), GetOppositeBranchCondition(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegisterInfo(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignedMinValue(), getSwappedCondition(), llvm::isAddMemInstrWithRelocation(), isDefConvertible(), llvm::MachineBasicBlock::isLiveIn(), llvm::Register::isPhysical(), isUseDefConvertible(), llvm_unreachable, llvm::make_range(), MBB, MI, MRI, llvm::MachineBasicBlock::pred_begin(), llvm::MachineBasicBlock::pred_size(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineBasicBlock::rbegin(), llvm::MachineBasicBlock::remove(), llvm::MachineInstr::removeOperand(), llvm::MachineBasicBlock::rend(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsDead(), llvm::Sub, llvm::Successor, llvm::MachineBasicBlock::successors(), TRI, and X86EnableAPXForRelocation.
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Definition at line 4646 of file X86InstrInfo.cpp.
References llvm::all_of(), assert(), llvm_unreachable, MI, and TRI.
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Definition at line 957 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineFunction::CloneMachineInstr(), llvm::MachineBasicBlock::computeRegisterLiveness(), DL, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), I, llvm::MachineBasicBlock::insert(), llvm_unreachable, llvm::MachineBasicBlock::LQR_Dead, MBB, MI, llvm::MachineInstr::modifiesRegister(), llvm::MachineInstr::substituteRegister(), and TRI.
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Definition at line 4075 of file X86InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), llvm::X86::COND_INVALID, llvm::MachineBasicBlock::end(), llvm::X86::getCondFromBranch(), I, and MBB.
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Definition at line 3746 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::CallingConv::C, canMakeTailCallConditional(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::X86::getCondFromBranch(), llvm::getImm(), getRegisterInfo(), I, llvm::RegState::Implicit, MBB, Opc, and llvm::SmallVectorBase< Size_T >::size().
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Definition at line 8970 of file X86InstrInfo.cpp.
References assert(), Cond, and GetOppositeBranchCondition().
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Definition at line 9366 of file X86InstrInfo.cpp.
References assert(), llvm::get(), llvm::X86Subtarget::hasAVX2(), llvm::X86Subtarget::hasAVX512(), lookup(), lookupAVX512(), MI, setExecutionDomainCustom(), and llvm::X86II::SSEDomainShift.
| bool X86InstrInfo::setExecutionDomainCustom | ( | MachineInstr & | MI, |
| unsigned | Domain | ||
| ) | const |
Definition at line 9175 of file X86InstrInfo.cpp.
References AdjustBlendMask(), assert(), llvm::get(), llvm::X86Subtarget::hasAVX2(), lookup(), lookupAVX512(), MI, and llvm::X86II::SSEDomainShift.
Referenced by setExecutionDomain().
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Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition at line 271 of file X86InstrInfo.h.
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This is an architecture-specific helper function of reassociateOps.
Set special operand attributes for new instructions after reassociation.
Definition at line 10278 of file X86InstrInfo.cpp.
References assert(), llvm::MachineInstr::findRegisterDefOperand(), llvm::MachineOperand::isDead(), and llvm::MachineOperand::setIsDead().
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This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther.
On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 8903 of file X86InstrInfo.cpp.
References assert(), llvm::SDNode::getMachineOpcode(), llvm::EVT::getSimpleVT(), llvm::SDNode::getValueType(), and llvm::MVT::SimpleTy.
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Definition at line 4784 of file X86InstrInfo.cpp.
References llvm::addFrameReference(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::X86RegisterInfo::canRealignStack(), llvm::get(), llvm::MachineFunction::getFrameInfo(), llvm::X86Subtarget::getFrameLowering(), llvm::getKillRegState(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::TargetFrameLowering::getStackAlign(), getStoreRegOpcode(), llvm::isAligned(), isAMXOpcode(), llvm::MachineFrameInfo::isFixedObjectIndex(), loadStoreTileReg(), MBB, MI, Opc, llvm::MachineInstrBuilder::setMIFlag(), and TRI.
Referenced by llvm::X86FrameLowering::spillCalleeSavedRegisters().
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Definition at line 8478 of file X86InstrInfo.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), llvm::X86::AddrNumOperands, llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineFunction::CreateMachineInstr(), llvm::RegState::Define, DL, extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), llvm::getDeadRegState(), llvm::getDefRegState(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), getLoadRegOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), llvm::getUndefRegState(), I, llvm::RegState::Implicit, llvm::isAligned(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::RegState::Kill, llvm_unreachable, llvm::lookupUnfoldTable(), MI, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineInstrBuilder::setMemRefs(), llvm::TB_BCAST_MASK, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.
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Definition at line 8625 of file X86InstrInfo.cpp.
References llvm::X86::AddrNumOperands, llvm::append_range(), extractLoadMMOs(), extractStoreMMOs(), llvm::get(), getBroadcastOpcode(), getLoadRegOpcode(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::MCInstrDesc::getNumDefs(), getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), getStoreRegOpcode(), llvm::MachineFunction::getSubtarget(), I, llvm::isAligned(), llvm::isNullConstant(), llvm_unreachable, llvm::lookupUnfoldTable(), N, llvm::MCInstrDesc::NumDefs, Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::setNodeMemRefs(), llvm::TB_BCAST_MASK, llvm::TB_FOLDED_LOAD, llvm::TB_FOLDED_STORE, llvm::TB_INDEX_MASK, and TRI.
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Definition at line 598 of file X86InstrInfo.h.
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Definition at line 4575 of file X86InstrInfo.cpp.
References assert(), llvm::ExtAddrMode::Basic, llvm::ExtAddrMode::Displacement, llvm::ExtAddrMode::Form, getAddrModeFromMemoryOp(), MI, llvm::ExtAddrMode::Scale, and llvm::ExtAddrMode::ScaledReg.
1.9.6