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LLVM 20.0.0git
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This is the complete list of members for llvm::X86InstrInfo, including all inherited members.
| accumulateInstrSeqToRootLatency(MachineInstr &Root) const override | llvm::X86InstrInfo | inlineprotected |
| analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override | llvm::X86InstrInfo | |
| analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override | llvm::X86InstrInfo | |
| analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override | llvm::X86InstrInfo | |
| areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override | llvm::X86InstrInfo | |
| breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override | llvm::X86InstrInfo | |
| buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override | llvm::X86InstrInfo | |
| canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override | llvm::X86InstrInfo | |
| canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override | llvm::X86InstrInfo | |
| classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const | llvm::X86InstrInfo | |
| commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override | llvm::X86InstrInfo | protected |
| convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override | llvm::X86InstrInfo | |
| copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override | llvm::X86InstrInfo | |
| decomposeMachineOperandsTargetFlags(unsigned TF) const override | llvm::X86InstrInfo | |
| describeLoadedValue(const MachineInstr &MI, Register Reg) const override | llvm::X86InstrInfo | |
| expandPostRAPseudo(MachineInstr &MI) const override | llvm::X86InstrInfo | |
| findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override | llvm::X86InstrInfo | |
| foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override | llvm::X86InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override | llvm::X86InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override | llvm::X86InstrInfo | |
| foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, unsigned OpNum, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, unsigned Size, Align Alignment, bool AllowCommute) const | llvm::X86InstrInfo | |
| genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override | llvm::X86InstrInfo | protected |
| getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override | llvm::X86InstrInfo | |
| getExecutionDomain(const MachineInstr &MI) const override | llvm::X86InstrInfo | |
| getExecutionDomainCustom(const MachineInstr &MI) const | llvm::X86InstrInfo | |
| getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const | llvm::X86InstrInfo | |
| getFrameAdjustment(const MachineInstr &I) const | llvm::X86InstrInfo | inline |
| getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override | llvm::X86InstrInfo | protected |
| getGlobalBaseReg(MachineFunction *MF) const | llvm::X86InstrInfo | |
| getJumpTableIndex(const MachineInstr &MI) const override | llvm::X86InstrInfo | |
| getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override | llvm::X86InstrInfo | protected |
| getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| getNop() const override | llvm::X86InstrInfo | |
| getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override | llvm::X86InstrInfo | |
| getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override | llvm::X86InstrInfo | |
| getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const override | llvm::X86InstrInfo | |
| getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override | llvm::X86InstrInfo | |
| getRegisterInfo() const | llvm::X86InstrInfo | inline |
| getSerializableDirectMachineOperandTargetFlags() const override | llvm::X86InstrInfo | |
| getSPAdjust(const MachineInstr &MI) const override | llvm::X86InstrInfo | |
| getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| hasCommutePreference(MachineInstr &MI, bool &Commute) const override | llvm::X86InstrInfo | |
| hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override | llvm::X86InstrInfo | |
| hasLiveCondCodeDef(MachineInstr &MI) const | llvm::X86InstrInfo | |
| hasLockPrefix(const MachineInstr &MI) | llvm::X86InstrInfo | inlinestatic |
| hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override | llvm::X86InstrInfo | |
| insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override | llvm::X86InstrInfo | |
| insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override | llvm::X86InstrInfo | |
| insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override | llvm::X86InstrInfo | |
| insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override | llvm::X86InstrInfo | |
| isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override | llvm::X86InstrInfo | |
| isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override | llvm::X86InstrInfo | |
| isCopyInstrImpl(const MachineInstr &MI) const override | llvm::X86InstrInfo | protected |
| isDataInvariant(MachineInstr &MI) | llvm::X86InstrInfo | static |
| isDataInvariantLoad(MachineInstr &MI) | llvm::X86InstrInfo | static |
| isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override | llvm::X86InstrInfo | |
| isHighLatencyDef(int opc) const override | llvm::X86InstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::X86InstrInfo | |
| isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override | llvm::X86InstrInfo | |
| isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override | llvm::X86InstrInfo | |
| isReallyTriviallyReMaterializable(const MachineInstr &MI) const override | llvm::X86InstrInfo | |
| isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override | llvm::X86InstrInfo | |
| isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override | llvm::X86InstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override | llvm::X86InstrInfo | |
| isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override | llvm::X86InstrInfo | |
| isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override | llvm::X86InstrInfo | |
| isSubregFoldable() const override | llvm::X86InstrInfo | inline |
| isUnconditionalTailCall(const MachineInstr &MI) const override | llvm::X86InstrInfo | |
| loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::X86InstrInfo | |
| loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const | llvm::X86InstrInfo | |
| optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override | llvm::X86InstrInfo | |
| optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override | llvm::X86InstrInfo | |
| preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override | llvm::X86InstrInfo | |
| reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override | llvm::X86InstrInfo | |
| removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override | llvm::X86InstrInfo | |
| replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override | llvm::X86InstrInfo | |
| reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override | llvm::X86InstrInfo | |
| setExecutionDomain(MachineInstr &MI, unsigned Domain) const override | llvm::X86InstrInfo | |
| setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const | llvm::X86InstrInfo | |
| setFrameAdjustment(MachineInstr &I, int64_t V) const | llvm::X86InstrInfo | inline |
| setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override | llvm::X86InstrInfo | |
| shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override | llvm::X86InstrInfo | |
| storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override | llvm::X86InstrInfo | |
| unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override | llvm::X86InstrInfo | |
| unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override | llvm::X86InstrInfo | |
| useMachineCombiner() const override | llvm::X86InstrInfo | inline |
| verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override | llvm::X86InstrInfo | |
| X86InstrInfo(X86Subtarget &STI) | llvm::X86InstrInfo | explicit |
1.9.6