LLVM  9.0.0svn
X86FixupLEAs.cpp
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1 //===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass that finds instructions that can be
10 // re-written as LEA instructions in order to reduce pipeline delays.
11 // It replaces LEAs with ADD/INC/DEC when that is better for size/speed.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "X86.h"
16 #include "X86InstrInfo.h"
17 #include "X86Subtarget.h"
18 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/Support/Debug.h"
25 using namespace llvm;
26 
27 #define FIXUPLEA_DESC "X86 LEA Fixup"
28 #define FIXUPLEA_NAME "x86-fixup-LEAs"
29 
30 #define DEBUG_TYPE FIXUPLEA_NAME
31 
32 STATISTIC(NumLEAs, "Number of LEA instructions created");
33 
34 namespace {
35 class FixupLEAPass : public MachineFunctionPass {
36  enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
37 
38  /// Given a machine register, look for the instruction
39  /// which writes it in the current basic block. If found,
40  /// try to replace it with an equivalent LEA instruction.
41  /// If replacement succeeds, then also process the newly created
42  /// instruction.
43  void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
44  MachineBasicBlock &MBB);
45 
46  /// Given a memory access or LEA instruction
47  /// whose address mode uses a base and/or index register, look for
48  /// an opportunity to replace the instruction which sets the base or index
49  /// register with an equivalent LEA instruction.
50  void processInstruction(MachineBasicBlock::iterator &I,
51  MachineBasicBlock &MBB);
52 
53  /// Given a LEA instruction which is unprofitable
54  /// on SlowLEA targets try to replace it with an equivalent ADD instruction.
55  void processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
56  MachineBasicBlock &MBB);
57 
58  /// Given a LEA instruction which is unprofitable
59  /// on SNB+ try to replace it with other instructions.
60  /// According to Intel's Optimization Reference Manual:
61  /// " For LEA instructions with three source operands and some specific
62  /// situations, instruction latency has increased to 3 cycles, and must
63  /// dispatch via port 1:
64  /// - LEA that has all three source operands: base, index, and offset
65  /// - LEA that uses base and index registers where the base is EBP, RBP,
66  /// or R13
67  /// - LEA that uses RIP relative addressing mode
68  /// - LEA that uses 16-bit addressing mode "
69  /// This function currently handles the first 2 cases only.
70  MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
71  MachineBasicBlock &MBB);
72 
73  /// Look for LEAs that are really two address LEAs that we might be able to
74  /// turn into regular ADD instructions.
75  bool optTwoAddrLEA(MachineBasicBlock::iterator &I,
76  MachineBasicBlock &MBB, bool OptIncDec,
77  bool UseLEAForSP) const;
78 
79  /// Determine if an instruction references a machine register
80  /// and, if so, whether it reads or writes the register.
81  RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
82 
83  /// Step backwards through a basic block, looking
84  /// for an instruction which writes a register within
85  /// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
88  MachineBasicBlock &MBB);
89 
90  /// if an instruction can be converted to an
91  /// equivalent LEA, insert the new instruction into the basic block
92  /// and return a pointer to it. Otherwise, return zero.
93  MachineInstr *postRAConvertToLEA(MachineBasicBlock &MBB,
94  MachineBasicBlock::iterator &MBBI) const;
95 
96 public:
97  static char ID;
98 
99  StringRef getPassName() const override { return FIXUPLEA_DESC; }
100 
101  FixupLEAPass() : MachineFunctionPass(ID) { }
102 
103  /// Loop over all of the basic blocks,
104  /// replacing instructions by equivalent LEA instructions
105  /// if needed and when possible.
106  bool runOnMachineFunction(MachineFunction &MF) override;
107 
108  // This pass runs after regalloc and doesn't support VReg operands.
109  MachineFunctionProperties getRequiredProperties() const override {
112  }
113 
114 private:
115  TargetSchedModel TSM;
116  const X86InstrInfo *TII;
117  const X86RegisterInfo *TRI;
118 };
119 }
120 
121 char FixupLEAPass::ID = 0;
122 
123 INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
124 
125 MachineInstr *
126 FixupLEAPass::postRAConvertToLEA(MachineBasicBlock &MBB,
127  MachineBasicBlock::iterator &MBBI) const {
128  MachineInstr &MI = *MBBI;
129  switch (MI.getOpcode()) {
130  case X86::MOV32rr:
131  case X86::MOV64rr: {
132  const MachineOperand &Src = MI.getOperand(1);
133  const MachineOperand &Dest = MI.getOperand(0);
134  MachineInstr *NewMI =
135  BuildMI(MBB, MBBI, MI.getDebugLoc(),
136  TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
137  : X86::LEA64r))
138  .add(Dest)
139  .add(Src)
140  .addImm(1)
141  .addReg(0)
142  .addImm(0)
143  .addReg(0);
144  return NewMI;
145  }
146  }
147 
148  if (!MI.isConvertibleTo3Addr())
149  return nullptr;
150 
151  switch (MI.getOpcode()) {
152  case X86::ADD64ri32:
153  case X86::ADD64ri8:
154  case X86::ADD64ri32_DB:
155  case X86::ADD64ri8_DB:
156  case X86::ADD32ri:
157  case X86::ADD32ri8:
158  case X86::ADD32ri_DB:
159  case X86::ADD32ri8_DB:
160  case X86::ADD16ri:
161  case X86::ADD16ri8:
162  case X86::ADD16ri_DB:
163  case X86::ADD16ri8_DB:
164  if (!MI.getOperand(2).isImm()) {
165  // convertToThreeAddress will call getImm()
166  // which requires isImm() to be true
167  return nullptr;
168  }
169  break;
170  case X86::ADD16rr:
171  case X86::ADD16rr_DB:
172  if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
173  // if src1 != src2, then convertToThreeAddress will
174  // need to create a Virtual register, which we cannot do
175  // after register allocation.
176  return nullptr;
177  }
178  }
179  MachineFunction::iterator MFI = MBB.getIterator();
180  return TII->convertToThreeAddress(MFI, MI, nullptr);
181 }
182 
183 FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
184 
185 static bool isLEA(unsigned Opcode) {
186  return Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
187  Opcode == X86::LEA64_32r;
188 }
189 
190 bool FixupLEAPass::runOnMachineFunction(MachineFunction &MF) {
191  if (skipFunction(MF.getFunction()))
192  return false;
193 
194  const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
195  bool IsSlowLEA = ST.slowLEA();
196  bool IsSlow3OpsLEA = ST.slow3OpsLEA();
197  bool LEAUsesAG = ST.LEAusesAG();
198 
199  bool OptIncDec = !ST.slowIncDec() || MF.getFunction().hasOptSize();
200  bool UseLEAForSP = ST.useLeaForSP();
201 
202  TSM.init(&ST);
203  TII = ST.getInstrInfo();
204  TRI = ST.getRegisterInfo();
205 
206  LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
207  for (MachineBasicBlock &MBB : MF) {
208  // First pass. Try to remove or optimize existing LEAs.
209  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
210  if (!isLEA(I->getOpcode()))
211  continue;
212 
213  if (optTwoAddrLEA(I, MBB, OptIncDec, UseLEAForSP))
214  continue;
215 
216  if (IsSlowLEA) {
217  processInstructionForSlowLEA(I, MBB);
218  } else if (IsSlow3OpsLEA) {
219  if (auto *NewMI = processInstrForSlow3OpLEA(*I, MBB)) {
220  MBB.erase(I);
221  I = NewMI;
222  }
223  }
224  }
225 
226  // Second pass for creating LEAs. This may reverse some of the
227  // transformations above.
228  if (LEAUsesAG) {
229  for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
230  processInstruction(I, MBB);
231  }
232  }
233 
234  LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
235 
236  return true;
237 }
238 
239 FixupLEAPass::RegUsageState
240 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
241  RegUsageState RegUsage = RU_NotUsed;
242  MachineInstr &MI = *I;
243 
244  for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
245  MachineOperand &opnd = MI.getOperand(i);
246  if (opnd.isReg() && opnd.getReg() == p.getReg()) {
247  if (opnd.isDef())
248  return RU_Write;
249  RegUsage = RU_Read;
250  }
251  }
252  return RegUsage;
253 }
254 
255 /// getPreviousInstr - Given a reference to an instruction in a basic
256 /// block, return a reference to the previous instruction in the block,
257 /// wrapping around to the last instruction of the block if the block
258 /// branches to itself.
260  MachineBasicBlock &MBB) {
261  if (I == MBB.begin()) {
262  if (MBB.isPredecessor(&MBB)) {
263  I = --MBB.end();
264  return true;
265  } else
266  return false;
267  }
268  --I;
269  return true;
270 }
271 
273 FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
274  MachineBasicBlock &MBB) {
275  int InstrDistance = 1;
277  static const int INSTR_DISTANCE_THRESHOLD = 5;
278 
279  CurInst = I;
280  bool Found;
281  Found = getPreviousInstr(CurInst, MBB);
282  while (Found && I != CurInst) {
283  if (CurInst->isCall() || CurInst->isInlineAsm())
284  break;
285  if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
286  break; // too far back to make a difference
287  if (usesRegister(p, CurInst) == RU_Write) {
288  return CurInst;
289  }
290  InstrDistance += TSM.computeInstrLatency(&*CurInst);
291  Found = getPreviousInstr(CurInst, MBB);
292  }
294 }
295 
296 static inline bool isInefficientLEAReg(unsigned Reg) {
297  return Reg == X86::EBP || Reg == X86::RBP ||
298  Reg == X86::R13D || Reg == X86::R13;
299 }
300 
301 static inline bool isRegOperand(const MachineOperand &Op) {
302  return Op.isReg() && Op.getReg() != X86::NoRegister;
303 }
304 
305 /// Returns true if this LEA uses base an index registers, and the base register
306 /// is known to be inefficient for the subtarget.
307 // TODO: use a variant scheduling class to model the latency profile
308 // of LEA instructions, and implement this logic as a scheduling predicate.
309 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
310  const MachineOperand &Index) {
311  return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
312  isRegOperand(Index);
313 }
314 
315 static inline bool hasLEAOffset(const MachineOperand &Offset) {
316  return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
317 }
318 
319 static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
320  switch (LEAOpcode) {
321  default:
322  llvm_unreachable("Unexpected LEA instruction");
323  case X86::LEA32r:
324  case X86::LEA64_32r:
325  return X86::ADD32rr;
326  case X86::LEA64r:
327  return X86::ADD64rr;
328  }
329 }
330 
331 static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
332  const MachineOperand &Offset) {
333  bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
334  switch (LEAOpcode) {
335  default:
336  llvm_unreachable("Unexpected LEA instruction");
337  case X86::LEA32r:
338  case X86::LEA64_32r:
339  return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
340  case X86::LEA64r:
341  return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
342  }
343 }
344 
345 static inline unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC) {
346  switch (LEAOpcode) {
347  default:
348  llvm_unreachable("Unexpected LEA instruction");
349  case X86::LEA32r:
350  case X86::LEA64_32r:
351  return IsINC ? X86::INC32r : X86::DEC32r;
352  case X86::LEA64r:
353  return IsINC ? X86::INC64r : X86::DEC64r;
354  }
355 }
356 
357 bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
358  MachineBasicBlock &MBB, bool OptIncDec,
359  bool UseLEAForSP) const {
360  MachineInstr &MI = *I;
361 
363  const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
365  const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
366  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
367 
368  if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
369  !TII->isSafeToClobberEFLAGS(MBB, I))
370  return false;
371 
372  unsigned DestReg = MI.getOperand(0).getReg();
373  unsigned BaseReg = Base.getReg();
374  unsigned IndexReg = Index.getReg();
375 
376  // Don't change stack adjustment LEAs.
377  if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
378  return false;
379 
380  // LEA64_32 has 64-bit operands but 32-bit result.
381  if (MI.getOpcode() == X86::LEA64_32r) {
382  if (BaseReg != 0)
383  BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
384  if (IndexReg != 0)
385  IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
386  }
387 
388  MachineInstr *NewMI = nullptr;
389 
390  // Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
391  // which can be turned into add %reg2, %reg1
392  if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
393  (DestReg == BaseReg || DestReg == IndexReg)) {
394  unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
395  if (DestReg != BaseReg)
396  std::swap(BaseReg, IndexReg);
397 
398  if (MI.getOpcode() == X86::LEA64_32r) {
399  // TODO: Do we need the super register implicit use?
400  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
401  .addReg(BaseReg).addReg(IndexReg)
403  .addReg(Index.getReg(), RegState::Implicit);
404  } else {
405  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
406  .addReg(BaseReg).addReg(IndexReg);
407  }
408  } else if (DestReg == BaseReg && IndexReg == 0) {
409  // This is an LEA with only a base register and a displacement,
410  // We can use ADDri or INC/DEC.
411 
412  // Does this LEA have one these forms:
413  // lea %reg, 1(%reg)
414  // lea %reg, -1(%reg)
415  if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
416  bool IsINC = Disp.getImm() == 1;
417  unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC);
418 
419  if (MI.getOpcode() == X86::LEA64_32r) {
420  // TODO: Do we need the super register implicit use?
421  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
422  .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
423  } else {
424  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
425  .addReg(BaseReg);
426  }
427  } else {
428  unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
429  if (MI.getOpcode() == X86::LEA64_32r) {
430  // TODO: Do we need the super register implicit use?
431  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
432  .addReg(BaseReg).addImm(Disp.getImm())
433  .addReg(Base.getReg(), RegState::Implicit);
434  } else {
435  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
436  .addReg(BaseReg).addImm(Disp.getImm());
437  }
438  }
439  } else
440  return false;
441 
442  MBB.erase(I);
443  I = NewMI;
444  return true;
445 }
446 
447 void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
448  MachineBasicBlock &MBB) {
449  // Process a load, store, or LEA instruction.
450  MachineInstr &MI = *I;
451  const MCInstrDesc &Desc = MI.getDesc();
452  int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
453  if (AddrOffset >= 0) {
454  AddrOffset += X86II::getOperandBias(Desc);
455  MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
456  if (p.isReg() && p.getReg() != X86::ESP) {
457  seekLEAFixup(p, I, MBB);
458  }
459  MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
460  if (q.isReg() && q.getReg() != X86::ESP) {
461  seekLEAFixup(q, I, MBB);
462  }
463  }
464 }
465 
466 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
468  MachineBasicBlock &MBB) {
469  MachineBasicBlock::iterator MBI = searchBackwards(p, I, MBB);
470  if (MBI != MachineBasicBlock::iterator()) {
471  MachineInstr *NewMI = postRAConvertToLEA(MBB, MBI);
472  if (NewMI) {
473  ++NumLEAs;
474  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
475  // now to replace with an equivalent LEA...
476  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
477  MBB.erase(MBI);
479  static_cast<MachineBasicBlock::iterator>(NewMI);
480  processInstruction(J, MBB);
481  }
482  }
483 }
484 
485 void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
486  MachineBasicBlock &MBB) {
487  MachineInstr &MI = *I;
488  const unsigned Opcode = MI.getOpcode();
489 
490  const MachineOperand &Dst = MI.getOperand(0);
492  const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
495  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
496 
497  if (Segment.getReg() != 0 || !Offset.isImm() ||
498  !TII->isSafeToClobberEFLAGS(MBB, I))
499  return;
500  const unsigned DstR = Dst.getReg();
501  const unsigned SrcR1 = Base.getReg();
502  const unsigned SrcR2 = Index.getReg();
503  if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
504  return;
505  if (Scale.getImm() > 1)
506  return;
507  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
508  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
509  MachineInstr *NewMI = nullptr;
510  // Make ADD instruction for two registers writing to LEA's destination
511  if (SrcR1 != 0 && SrcR2 != 0) {
512  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
513  const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
514  NewMI =
515  BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
516  LLVM_DEBUG(NewMI->dump(););
517  }
518  // Make ADD instruction for immediate
519  if (Offset.getImm() != 0) {
520  const MCInstrDesc &ADDri =
521  TII->get(getADDriFromLEA(Opcode, Offset));
522  const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
523  NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR)
524  .add(SrcR)
525  .addImm(Offset.getImm());
526  LLVM_DEBUG(NewMI->dump(););
527  }
528  if (NewMI) {
529  MBB.erase(I);
530  I = NewMI;
531  }
532 }
533 
534 MachineInstr *
535 FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
536  MachineBasicBlock &MBB) {
537  const unsigned LEAOpcode = MI.getOpcode();
538 
539  const MachineOperand &Dst = MI.getOperand(0);
541  const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
544  const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
545 
546  if (!(TII->isThreeOperandsLEA(MI) ||
547  hasInefficientLEABaseReg(Base, Index)) ||
548  !TII->isSafeToClobberEFLAGS(MBB, MI) ||
549  Segment.getReg() != X86::NoRegister)
550  return nullptr;
551 
552  unsigned DstR = Dst.getReg();
553  unsigned BaseR = Base.getReg();
554  unsigned IndexR = Index.getReg();
555  unsigned SSDstR =
556  (LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
557  bool IsScale1 = Scale.getImm() == 1;
558  bool IsInefficientBase = isInefficientLEAReg(BaseR);
559  bool IsInefficientIndex = isInefficientLEAReg(IndexR);
560 
561  // Skip these cases since it takes more than 2 instructions
562  // to replace the LEA instruction.
563  if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
564  return nullptr;
565  if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
566  (IsInefficientIndex || !IsScale1))
567  return nullptr;
568 
569  const DebugLoc DL = MI.getDebugLoc();
570  const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
571  const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
572 
573  LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
574  LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
575 
576  // First try to replace LEA with one or two (for the 3-op LEA case)
577  // add instructions:
578  // 1.lea (%base,%index,1), %base => add %index,%base
579  // 2.lea (%base,%index,1), %index => add %base,%index
580  if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
581  const MachineOperand &Src = DstR == BaseR ? Index : Base;
582  MachineInstr *NewMI =
583  BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
584  LLVM_DEBUG(NewMI->dump(););
585  // Create ADD instruction for the Offset in case of 3-Ops LEA.
586  if (hasLEAOffset(Offset)) {
587  NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
588  LLVM_DEBUG(NewMI->dump(););
589  }
590  return NewMI;
591  }
592  // If the base is inefficient try switching the index and base operands,
593  // otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
594  // lea offset(%base,%index,scale),%dst =>
595  // lea (%base,%index,scale); add offset,%dst
596  if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
597  MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
598  .add(Dst)
599  .add(IsInefficientBase ? Index : Base)
600  .add(Scale)
601  .add(IsInefficientBase ? Base : Index)
602  .addImm(0)
603  .add(Segment);
604  LLVM_DEBUG(NewMI->dump(););
605  // Create ADD instruction for the Offset in case of 3-Ops LEA.
606  if (hasLEAOffset(Offset)) {
607  NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
608  LLVM_DEBUG(NewMI->dump(););
609  }
610  return NewMI;
611  }
612  // Handle the rest of the cases with inefficient base register:
613  assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
614  assert(IsInefficientBase && "efficient base should be handled already!");
615 
616  // lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
617  if (IsScale1 && !hasLEAOffset(Offset)) {
618  bool BIK = Base.isKill() && BaseR != IndexR;
619  TII->copyPhysReg(MBB, MI, DL, DstR, BaseR, BIK);
620  LLVM_DEBUG(MI.getPrevNode()->dump(););
621 
622  MachineInstr *NewMI =
623  BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
624  LLVM_DEBUG(NewMI->dump(););
625  return NewMI;
626  }
627  // lea offset(%base,%index,scale), %dst =>
628  // lea offset( ,%index,scale), %dst; add %base,%dst
629  MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
630  .add(Dst)
631  .addReg(0)
632  .add(Scale)
633  .add(Index)
634  .add(Offset)
635  .add(Segment);
636  LLVM_DEBUG(NewMI->dump(););
637 
638  NewMI = BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
639  LLVM_DEBUG(NewMI->dump(););
640  return NewMI;
641 }
const MachineInstrBuilder & add(const MachineOperand &MO) const
static bool isRegOperand(const MachineOperand &Op)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:614
const X86InstrInfo * getInstrInfo() const override
Definition: X86Subtarget.h:501
bool slowLEA() const
Definition: X86Subtarget.h:672
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
unsigned getReg() const
getReg - Returns the register number.
unsigned Reg
static bool isInefficientLEAReg(unsigned Reg)
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
STATISTIC(NumFunctions, "Total number of functions")
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static bool hasInefficientLEABaseReg(const MachineOperand &Base, const MachineOperand &Index)
Returns true if this LEA uses base an index registers, and the base register is known to be inefficie...
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
static bool getPreviousInstr(MachineBasicBlock::iterator &I, MachineBasicBlock &MBB)
getPreviousInstr - Given a reference to an instruction in a basic block, return a reference to the pr...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
bool slow3OpsLEA() const
Definition: X86Subtarget.h:673
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MachineInstrBundleIterator< MachineInstr > iterator
bool isConvertibleTo3Addr(QueryType Type=IgnoreBundle) const
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...
Definition: MachineInstr.h:878
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
bool useLeaForSP() const
Definition: X86Subtarget.h:646
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
unsigned getOperandBias(const MCInstrDesc &Desc)
getOperandBias - compute whether all of the def operands are repeated in the uses and therefore shoul...
Definition: X86BaseInfo.h:721
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static unsigned getADDriFromLEA(unsigned LEAOpcode, const MachineOperand &Offset)
bool slowIncDec() const
Definition: X86Subtarget.h:674
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:33
#define FIXUPLEA_DESC
const X86RegisterInfo * getRegisterInfo() const override
Definition: X86Subtarget.h:511
Iterator for intrusive lists based on ilist_node.
bool LEAusesAG() const
Definition: X86Subtarget.h:671
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
static uint64_t add(uint64_t LeftOp, uint64_t RightOp)
Definition: FileCheck.cpp:169
MachineOperand class - Representation of each machine instruction operand.
static unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC)
int64_t getImm() const
const Function & getFunction() const
Return the LLVM function that this machine code represents.
static unsigned getADDrrFromLEA(unsigned LEAOpcode)
static bool isLEA(unsigned Opcode)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getX86SubSuperRegister(unsigned, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:940
#define FIXUPLEA_NAME
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
static bool hasLEAOffset(const MachineOperand &Offset)
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Properties which a MachineFunction may have at a given point in time.
int getMemoryOperandNo(uint64_t TSFlags)
getMemoryOperandNo - The function returns the MCInst operand # for the first field of the memory oper...
Definition: X86BaseInfo.h:761