30 #define FIXUPLEA_DESC "X86 LEA Fixup"
31 #define FIXUPLEA_NAME "x86-fixup-LEAs"
33 #define DEBUG_TYPE FIXUPLEA_NAME
35 STATISTIC(NumLEAs,
"Number of LEA instructions created");
39 enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
80 bool UseLEAForSP)
const;
162 switch (
MI.getOpcode()) {
169 TII->get(
MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
181 if (!
MI.isConvertibleTo3Addr())
184 switch (
MI.getOpcode()) {
190 case X86::ADD64ri32_DB:
191 case X86::ADD64ri8_DB:
194 case X86::ADD32ri_DB:
195 case X86::ADD32ri8_DB:
196 if (!
MI.getOperand(2).isImm()) {
209 case X86::ADD64rr_DB:
211 case X86::ADD32rr_DB:
215 return TII->convertToThreeAddress(
MI,
nullptr,
nullptr);
220 static bool isLEA(
unsigned Opcode) {
221 return Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
222 Opcode == X86::LEA64_32r;
230 bool IsSlowLEA =
ST.slowLEA();
231 bool IsSlow3OpsLEA =
ST.slow3OpsLEA();
232 bool LEAUsesAG =
ST.leaUsesAG();
235 bool UseLEAForSP =
ST.useLeaForSP();
238 TII =
ST.getInstrInfo();
239 TRI =
ST.getRegisterInfo();
240 auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
241 auto *MBFI = (PSI && PSI->hasProfileSummary())
242 ? &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI()
248 bool OptIncDecPerBB =
251 if (!
isLEA(
I->getOpcode()))
254 if (optTwoAddrLEA(
I,
MBB, OptIncDecPerBB, UseLEAForSP))
258 processInstructionForSlowLEA(
I,
MBB);
259 else if (IsSlow3OpsLEA)
260 processInstrForSlow3OpLEA(
I,
MBB, OptIncDecPerBB);
267 processInstruction(
I,
MBB);
276 FixupLEAPass::RegUsageState
278 RegUsageState
RegUsage = RU_NotUsed;
282 if (MO.isReg() && MO.getReg() ==
p.getReg()) {
311 int InstrDistance = 1;
313 static const int INSTR_DISTANCE_THRESHOLD = 5;
318 while (Found &&
I != CurInst) {
319 if (CurInst->isCall() || CurInst->isInlineAsm())
321 if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
323 if (usesRegister(
p, CurInst) == RU_Write) {
326 InstrDistance += TSM.computeInstrLatency(&*CurInst);
333 return Reg == X86::EBP ||
Reg == X86::RBP ||
334 Reg == X86::R13D ||
Reg == X86::R13;
344 Index.getReg() != X86::NoRegister;
377 bool IsInt8 =
Offset.isImm() && isInt<8>(
Offset.getImm());
383 return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
385 return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
395 return IsINC ? X86::INC32r : X86::DEC32r;
397 return IsINC ? X86::INC64r : X86::DEC64r;
404 const int InstrDistanceThreshold = 5;
405 int InstrDistance = 1;
408 unsigned LEAOpcode =
I->getOpcode();
411 Register DestReg =
I->getOperand(0).getReg();
413 while (CurInst !=
MBB.
end()) {
414 if (CurInst->isCall() || CurInst->isInlineAsm())
416 if (InstrDistance > InstrDistanceThreshold)
420 for (
unsigned I = 0,
E = CurInst->getNumOperands();
I !=
E; ++
I) {
423 if (Opnd.
getReg() == DestReg) {
427 unsigned AluOpcode = CurInst->getOpcode();
428 if (AluOpcode != AddOpcode && AluOpcode != SubOpcode)
439 if (!CurInst->registerDefIsDead(X86::EFLAGS,
TRI))
457 bool &BaseIndexDef,
bool &AluDestRef,
460 BaseIndexDef = AluDestRef =
false;
461 *KilledBase = *KilledIndex =
nullptr;
464 Register AluDestReg = AluI->getOperand(0).getReg();
467 while (CurInst != AluI) {
468 for (
unsigned I = 0,
E = CurInst->getNumOperands();
I !=
E; ++
I) {
485 *KilledIndex = &Opnd;
500 bool BaseIndexDef, AluDestRef;
502 checkRegUsage(
I, AluI, BaseIndexDef, AluDestRef, &KilledBase, &KilledIndex);
509 KilledBase = KilledIndex =
nullptr;
513 Register AluDestReg = AluI->getOperand(0).getReg();
516 if (
I->getOpcode() == X86::LEA64_32r) {
520 if (AluDestReg == IndexReg) {
521 if (BaseReg == IndexReg)
526 if (BaseReg == IndexReg)
527 KilledBase =
nullptr;
531 unsigned NewOpcode = AluI->getOpcode();
532 NewMI1 =
BuildMI(
MBB, InsertPos, AluI->getDebugLoc(),
TII->get(NewOpcode),
537 NewMI2 =
BuildMI(
MBB, InsertPos, AluI->getDebugLoc(),
TII->get(NewOpcode),
558 bool UseLEAForSP)
const {
577 if (UseLEAForSP && (DestReg ==
X86::ESP || DestReg == X86::RSP))
581 if (
MI.getOpcode() == X86::LEA64_32r) {
593 if (BaseReg != 0 && IndexReg != 0 && Disp.
getImm() == 0 &&
594 (DestReg == BaseReg || DestReg == IndexReg)) {
596 if (DestReg != BaseReg)
599 if (
MI.getOpcode() == X86::LEA64_32r) {
609 }
else if (DestReg == BaseReg && IndexReg == 0) {
617 if (OptIncDec && (Disp.
getImm() == 1 || Disp.
getImm() == -1)) {
618 bool IsINC = Disp.
getImm() == 1;
621 if (
MI.getOpcode() == X86::LEA64_32r) {
631 if (
MI.getOpcode() == X86::LEA64_32r) {
641 }
else if (BaseReg != 0 && IndexReg != 0 && Disp.
getImm() == 0) {
646 return optLEAALU(
I,
MBB);
662 if (AddrOffset >= 0) {
666 seekLEAFixup(
p,
I,
MBB);
670 seekLEAFixup(q,
I,
MBB);
683 LLVM_DEBUG(
dbgs() <<
"FixLEA: Candidate to replace:"; MBI->dump(););
690 processInstruction(J,
MBB);
698 const unsigned Opcode =
MI.getOpcode();
714 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
722 if (SrcR1 != 0 && SrcR2 != 0) {
730 if (
Offset.getImm() != 0) {
750 const unsigned LEAOpcode =
MI.getOpcode();
762 Segment.
getReg() != X86::NoRegister)
769 if (
MI.getOpcode() == X86::LEA64_32r) {
776 bool IsScale1 = Scale.
getImm() == 1;
782 if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
794 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {
796 if (DestReg != BaseReg)
799 if (
MI.getOpcode() == X86::LEA64_32r) {
811 }
else if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
818 .
add(IsInefficientBase ?
Index : Base)
820 .
add(IsInefficientBase ? Base :
Index)
831 if (OptIncDec &&
Offset.isImm() &&
854 assert(DestReg != BaseReg &&
"DestReg == BaseReg should be handled already!");
855 assert(IsInefficientBase &&
"efficient base should be handled already!");
858 if (LEAOpcode == X86::LEA64_32r)
863 bool BIK =
Base.isKill() && BaseReg != IndexReg;