LLVM 18.0.0git
X86TargetParser.cpp
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1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/Bitset.h"
16#include <numeric>
17
18using namespace llvm;
19using namespace llvm::X86;
20
21namespace {
22
24
25struct ProcInfo {
28 unsigned KeyFeature;
29 FeatureBitset Features;
30 char Mangling;
31 bool OnlyForCPUDispatchSpecific;
32};
33
34struct FeatureInfo {
35 StringLiteral NameWithPlus;
36 FeatureBitset ImpliedFeatures;
37
38 StringRef getName(bool WithPlus = false) const {
39 assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
40 if (WithPlus)
41 return NameWithPlus;
42 return NameWithPlus.drop_front();
43 }
44};
45
46} // end anonymous namespace
47
48#define X86_FEATURE(ENUM, STRING) \
49 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
50#include "llvm/TargetParser/X86TargetParser.def"
51
52// Pentium with MMX.
54 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
55
56// Pentium 2 and 3.
58 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
60
61// Pentium 4 CPUs
65 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
66
67// Basic 64-bit capable CPU.
70 FeaturePOPCNT | FeatureCRC32 |
71 FeatureSSE4_2 | FeatureCMPXCHG16B;
73 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
74 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
76 FeatureAVX512BW | FeatureAVX512CD |
77 FeatureAVX512DQ | FeatureAVX512VL;
78
79// Intel Core CPUs
81 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
82constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
84 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
87 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
89 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
91 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
92 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
94 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
95
96// Intel Knights Landing and Knights Mill
97// Knights Landing has feature parity with Broadwell.
99 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureEVEX512 |
100 FeatureAVX512CD | FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
101constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
102
103// Intel Skylake processors.
105 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
106 FeatureXSAVES | FeatureSGX;
107// SkylakeServer inherits all SkylakeClient features except SGX.
108// FIXME: That doesn't match gcc.
110 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 |
111 FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL |
112 FeatureCLWB | FeaturePKU;
114 FeaturesSkylakeServer | FeatureAVX512VNNI;
116 FeaturesCascadeLake | FeatureAVX512BF16;
117
118// Intel 10nm processors.
120 FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
121 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
122 FeatureAVX512VBMI | FeaturePKU | FeatureSHA;
124 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
125 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
126 FeatureVAES | FeatureVPCLMULQDQ;
129 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
131 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
132 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
134 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
135 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
136 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
137 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
138 FeatureWAITPKG;
140 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
141
142// Intel Atom processors.
143// Bonnell has feature parity with Core2 and adds MOVBE.
144constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
145// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
147 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
149 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
150 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
151 FeatureXSAVEOPT | FeatureXSAVES;
153 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
155 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
157 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
158 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
159 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
160 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
161 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
163 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
164 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
166 FeaturesSierraforest | FeatureRAOINT;
168 FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
170 FeaturesArrowlakeS | FeaturePREFETCHI;
172 FeaturesArrowlakeS | FeatureUSERMSR | FeaturePREFETCHI;
173
174// Geode Processor.
176 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
177
178// K6 processor.
179constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
180
181// K7 and K8 architecture processors.
183 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
185 FeaturesAthlon | FeatureFXSR | FeatureSSE;
187 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
188constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
190 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
191 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
192
193// Bobcat architecture processors.
195 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
196 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
197 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
198 FeatureSAHF;
200 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
201 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
202
203// AMD Bulldozer architecture processors.
205 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
206 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
207 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
208 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
209 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
210 FeatureXOP | FeatureXSAVE;
212 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
214 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
215constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
216 FeatureBMI2 | FeatureMOVBE |
217 FeatureMWAITX | FeatureRDRND;
218
219// AMD Zen architecture processors.
221 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
222 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
223 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
224 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
225 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
226 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
227 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
228 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
229 FeatureXSAVEOPT | FeatureXSAVES;
230constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
231 FeatureRDPID | FeatureRDPRU |
232 FeatureWBNOINVD;
234 FeatureINVPCID | FeaturePKU |
235 FeatureVAES | FeatureVPCLMULQDQ;
237 FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
238 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
239 FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI |
240 FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
241 FeatureGFNI | FeatureSHSTK;
242
243// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
244// X86TargetParser.def to here. They are assigned by following ways:
245// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
246// to '\0' by default, which means not support cpu_specific/dispatch feature.
247// 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
248// listed here before, which means it doesn't support -march, -mtune and so on.
249// FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
250// cpu_dispatch/specific() feature and -march, -mtune, and so on.
251// clang-format off
252constexpr ProcInfo Processors[] = {
253 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
254 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
255 { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
256 // i386-generation processors.
257 { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
258 // i486-generation processors.
259 { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
260 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
261 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
262 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false },
263 // i586-generation processors, P5 microarchitecture based.
264 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
265 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
266 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
267 { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
268 // i686-generation processors, P6 / Pentium M microarchitecture based.
269 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
270 { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
271 { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
272 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
273 { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
274 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
275 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
276 { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
277 { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
278 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
279 { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
280 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
281 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
282 // Netburst microarchitecture based processors.
283 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
284 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
285 { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
286 { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
287 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
288 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
289 // Core microarchitecture based processors.
290 { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
291 { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
292 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
293 { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
294 // Atom processors
295 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
296 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
297 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
298 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
299 { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
300 { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
301 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
302 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
303 { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
304 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
305 // Nehalem microarchitecture based processors.
306 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
307 { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
308 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
309 // Westmere microarchitecture based processors.
310 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
311 { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
312 // Sandy Bridge microarchitecture based processors.
313 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
314 { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
315 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
316 // Ivy Bridge microarchitecture based processors.
317 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
318 { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
319 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
320 // Haswell microarchitecture based processors.
321 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
322 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
323 { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
324 { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
325 // Broadwell microarchitecture based processors.
326 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
327 { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
328 { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
329 // Skylake client microarchitecture based processors.
330 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
331 // Skylake server microarchitecture based processors.
332 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
333 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
334 { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
335 // Cascadelake Server microarchitecture based processors.
336 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
337 // Cooperlake Server microarchitecture based processors.
338 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
339 // Cannonlake client microarchitecture based processors.
340 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
341 // Icelake client microarchitecture based processors.
342 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
343 { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
344 // Rocketlake microarchitecture based processors.
345 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
346 // Icelake server microarchitecture based processors.
347 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
348 { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
349 // Tigerlake microarchitecture based processors.
350 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
351 // Sapphire Rapids microarchitecture based processors.
352 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
353 // Alderlake microarchitecture based processors.
354 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
355 // Raptorlake microarchitecture based processors.
356 { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
357 // Meteorlake microarchitecture based processors.
358 { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
359 // Arrowlake microarchitecture based processors.
360 { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
361 { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
362 { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
363 // Lunarlake microarchitecture based processors.
364 { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
365 // Gracemont microarchitecture based processors.
366 { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
367 // Pantherlake microarchitecture based processors.
368 { {"pantherlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesPantherlake, 'p', false },
369 // Sierraforest microarchitecture based processors.
370 { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
371 // Grandridge microarchitecture based processors.
372 { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge, 'p', false },
373 // Granite Rapids microarchitecture based processors.
374 { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids, 'n', false },
375 // Granite Rapids D microarchitecture based processors.
376 { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
377 { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512BF16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
378 // Emerald Rapids microarchitecture based processors.
379 { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids, 'n', false },
380 // Clearwaterforest microarchitecture based processors.
381 { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
382 // Knights Landing processor.
383 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
384 { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
385 // Knights Mill processor.
386 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
387 // Lakemont microarchitecture based processors.
388 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
389 // K6 architecture processors.
390 { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
391 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
392 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW, '\0', false },
393 // K7 architecture processors.
394 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
395 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
396 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
397 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
398 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
399 // K8 architecture processors.
400 { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
401 { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
402 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
403 { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
404 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
405 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
406 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
407 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
408 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
409 // Bobcat architecture processors.
410 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
411 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
412 // Bulldozer architecture processors.
413 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
414 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
415 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
416 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
417 // Zen architecture processors.
418 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
419 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
420 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
421 { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
422 // Generic 64-bit processor.
423 { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
424 { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
425 { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
426 { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
427 // Geode processors.
428 { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
429};
430// clang-format on
431
432constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
433
435 for (const auto &P : Processors)
436 if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
437 (P.Features[FEATURE_64BIT] || !Only64Bit))
438 return P.Kind;
439
440 return CK_None;
441}
442
445 return CK_None;
446 return parseArchX86(CPU, Only64Bit);
447}
448
450 bool Only64Bit) {
451 for (const auto &P : Processors)
452 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
453 (P.Features[FEATURE_64BIT] || !Only64Bit))
454 Values.emplace_back(P.Name);
455}
456
458 bool Only64Bit) {
459 for (const ProcInfo &P : Processors)
460 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
461 (P.Features[FEATURE_64BIT] || !Only64Bit) &&
463 Values.emplace_back(P.Name);
464}
465
467 // FIXME: Can we avoid a linear search here? The table might be sorted by
468 // CPUKind so we could binary search?
469 for (const auto &P : Processors) {
470 if (P.Kind == Kind) {
471 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
472 return static_cast<ProcessorFeatures>(P.KeyFeature);
473 }
474 }
475
476 llvm_unreachable("Unable to find CPU kind!");
477}
478
479// Features with no dependencies.
526
527// Not really CPU features, but need to be in the table because clang uses
528// target features to communicate them to the backend.
534
535// XSAVE features are dependent on basic XSAVE.
536constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
537constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
538constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
539
540// MMX->3DNOW->3DNOWA chain.
542constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
543constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
544
545// SSE/AVX/AVX512F chain.
547constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
548constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
549constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
550constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
551constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
552constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
553constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
556 FeatureAVX2 | FeatureF16C | FeatureFMA;
557
558// Vector extensions that build on SSE or AVX.
559constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
560constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
561constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
562constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
563constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
564constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
565constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
566constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
567constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
568constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
569
570// AVX512 features.
571constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
572constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
573constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
574constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
575constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
576constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
577
578constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
579constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
580constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
581constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
583constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
584constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
586
587// FIXME: These two aren't really implemented and just exist in the feature
588// list for __builtin_cpu_supports. So omit their dependencies.
591
592// SSE4_A->FMA4->XOP chain.
593constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
594constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
595constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
596
597// AMX Features
599constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
600constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
601constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
602constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
604
610constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
612constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
614 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
615// Key Locker Features
616constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
618
619// AVXVNNI Features
620constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
621
622// AVX10 Features
624 FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
625 FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
626 FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ |
627 FeatureAVX512FP16;
629 FeatureAVX10_1 | FeatureEVEX512;
630
631// APX Features
638
639constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
640#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
641#include "llvm/TargetParser/X86TargetParser.def"
642};
643
645 SmallVectorImpl<StringRef> &EnabledFeatures,
646 bool NeedPlus) {
648 [&](const ProcInfo &P) { return P.Name == CPU; });
649 assert(I != std::end(Processors) && "Processor not found!");
650
651 FeatureBitset Bits = I->Features;
652
653 // Remove the 64-bit feature which we only use to validate if a CPU can
654 // be used with 64-bit mode.
655 Bits &= ~Feature64BIT;
656
657 // Add the string version of all set bits.
658 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
659 if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty())
660 EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus));
661}
662
663// For each feature that is (transitively) implied by this feature, set it.
665 const FeatureBitset &Implies) {
666 // Fast path: Implies is often empty.
667 if (!Implies.any())
668 return;
669 FeatureBitset Prev;
670 Bits |= Implies;
671 do {
672 Prev = Bits;
673 for (unsigned i = CPU_FEATURE_MAX; i;)
674 if (Bits[--i])
675 Bits |= FeatureInfos[i].ImpliedFeatures;
676 } while (Prev != Bits);
677}
678
679/// Create bit vector of features that are implied disabled if the feature
680/// passed in Value is disabled.
681static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
682 // Check all features looking for any dependent on this feature. If we find
683 // one, mark it and recursively find any feature that depend on it.
684 FeatureBitset Prev;
685 Bits.set(Value);
686 do {
687 Prev = Bits;
688 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
689 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
690 Bits.set(i);
691 } while (Prev != Bits);
692}
693
695 StringRef Feature, bool Enabled,
696 StringMap<bool> &Features) {
697 auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) {
698 return FI.getName() == Feature;
699 });
700 if (I == std::end(FeatureInfos)) {
701 // FIXME: This shouldn't happen, but may not have all features in the table
702 // yet.
703 return;
704 }
705
706 FeatureBitset ImpliedBits;
707 if (Enabled)
708 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
709 else
710 getImpliedDisabledFeatures(ImpliedBits,
711 std::distance(std::begin(FeatureInfos), I));
712
713 // Update the map entry for all implied features.
714 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
715 if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
716 Features[FeatureInfos[i].getName()] = Enabled;
717}
718
721 [&](const ProcInfo &P) { return P.Name == CPU; });
722 assert(I != std::end(Processors) && "Processor not found!");
723 assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
724 return I->Mangling;
725}
726
729 [&](const ProcInfo &P) { return P.Name == Name; });
730 return I != std::end(Processors);
731}
732
733std::array<uint32_t, 4>
735 // Processor features and mapping to processor feature value.
736 std::array<uint32_t, 4> FeatureMask{};
737 for (StringRef FeatureStr : FeatureStrs) {
738 unsigned Feature = StringSwitch<unsigned>(FeatureStr)
739#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
740 .Case(STR, llvm::X86::FEATURE_##ENUM)
741#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) \
742 .Case(STR, llvm::X86::FEATURE_##ENUM)
743#include "llvm/TargetParser/X86TargetParser.def"
744 ;
745 assert(Feature / 32 < FeatureMask.size());
746 FeatureMask[Feature / 32] |= 1U << (Feature % 32);
747 }
748 return FeatureMask;
749}
750
752#ifndef NDEBUG
753 // Check that priorities are set properly in the .def file. We expect that
754 // "compat" features are assigned non-duplicate consecutive priorities
755 // starting from zero (0, 1, ..., num_features - 1).
756#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
757 unsigned Priorities[] = {
758#include "llvm/TargetParser/X86TargetParser.def"
759 };
760 std::array<unsigned, std::size(Priorities)> HelperList;
761 std::iota(HelperList.begin(), HelperList.end(), 0);
762 assert(std::is_permutation(HelperList.begin(), HelperList.end(),
763 std::begin(Priorities), std::end(Priorities)) &&
764 "Priorities don't form consecutive range!");
765#endif
766
767 switch (Feat) {
768#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
769 case X86::FEATURE_##ENUM: \
770 return PRIORITY;
771#include "llvm/TargetParser/X86TargetParser.def"
772 default:
773 llvm_unreachable("No Feature Priority for non-CPUSupports Features");
774 }
775}
std::string Name
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
static StringRef getName(Value *V)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool Enabled
Definition: Statistic.cpp:46
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
constexpr FeatureBitset FeaturesClearwaterforest
constexpr FeatureBitset FeaturesX86_64
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset FeaturesWestmere
constexpr FeatureBitset ImpliedFeaturesNDD
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset FeaturesAthlon
constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesSSE4_1
constexpr FeatureBitset FeaturesZNVER2
constexpr FeatureBitset FeaturesBDVER3
constexpr FeatureBitset ImpliedFeaturesBMI2
constexpr FeatureBitset FeaturesGeode
constexpr FeatureBitset ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesPREFETCHI
constexpr FeatureBitset ImpliedFeaturesAVX512FP16
constexpr FeatureBitset FeaturesCascadeLake
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset FeaturesGrandridge
constexpr FeatureBitset FeaturesK8SSE3
constexpr FeatureBitset FeaturesZNVER1
constexpr FeatureBitset FeaturesNocona
constexpr FeatureBitset ImpliedFeaturesEVEX512
constexpr FeatureBitset ImpliedFeaturesSSE4_A
constexpr FeatureBitset FeaturesPrescott
constexpr FeatureBitset FeaturesCooperLake
constexpr FeatureBitset ImpliedFeaturesEGPR
constexpr FeatureBitset ImpliedFeaturesFXSR
constexpr FeatureBitset FeaturesSapphireRapids
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesAES
constexpr FeatureBitset FeaturesTremont
constexpr FeatureBitset ImpliedFeaturesPush2Pop2
constexpr FeatureBitset FeaturesBDVER1
constexpr FeatureBitset ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesCRC32
static constexpr FeatureBitset FeaturesZNVER3
constexpr FeatureBitset FeaturesGoldmontPlus
constexpr FeatureBitset ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesPRFCHW
constexpr FeatureBitset FeaturesCannonlake
constexpr FeatureBitset ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesVAES
constexpr FeatureBitset FeaturesSandyBridge
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesRDPRU
constexpr FeatureBitset FeaturesAMDFAM10
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
constexpr FeatureBitset FeaturesSkylakeServer
constexpr FeatureBitset FeaturesPentiumMMX
constexpr FeatureBitset ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset FeaturesKNL
constexpr FeatureBitset FeaturesNehalem
constexpr FeatureBitset FeaturesBTVER1
constexpr FeatureBitset FeaturesPentium3
constexpr FeatureBitset ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT
constexpr FeatureBitset FeaturesAthlonXP
constexpr FeatureBitset FeaturesGraniteRapids
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
constexpr FeatureBitset FeaturesPantherlake
constexpr FeatureBitset ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesAVX
constexpr FeatureBitset FeaturesX86_64_V3
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesXSAVE
constexpr FeatureBitset FeaturesX86_64_V2
constexpr FeatureBitset FeaturesArrowlakeS
constexpr FeatureBitset ImpliedFeaturesMOVBE
constexpr FeatureBitset FeaturesIvyBridge
constexpr FeatureBitset FeaturesHaswell
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8
constexpr FeatureBitset ImpliedFeaturesCCMP
constexpr FeatureBitset FeaturesICLClient
constexpr FeatureBitset ImpliedFeaturesCF
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
constexpr FeatureBitset ImpliedFeaturesHRESET
constexpr const char * NoTuneList[]
constexpr FeatureBitset ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesRTM
constexpr FeatureBitset FeaturesRocketlake
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset FeaturesBTVER2
constexpr FeatureBitset FeaturesSkylakeClient
constexpr FeatureBitset ImpliedFeatures3DNOWA
constexpr FeatureBitset ImpliedFeaturesPPX
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
constexpr FeatureBitset FeaturesPentium2
constexpr FeatureBitset ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesAMX_FP16
constexpr FeatureBitset ImpliedFeaturesMMX
constexpr FeatureBitset FeaturesICLServer
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
constexpr FeatureBitset FeaturesBroadwell
constexpr ProcInfo Processors[]
constexpr FeatureBitset ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16
constexpr FeatureBitset ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA
constexpr FeatureBitset FeaturesSierraforest
constexpr FeatureBitset FeaturesK6
constexpr FeatureBitset ImpliedFeaturesRAOINT
constexpr FeatureBitset FeaturesX86_64_V4
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesSSE2
constexpr FeatureBitset FeaturesBonnell
constexpr FeatureBitset FeaturesPenryn
constexpr FeatureBitset ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeatures64BIT
constexpr FeatureBitset FeaturesK8
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesSM4
constexpr FeatureBitset ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPTWRITE
constexpr FeatureBitset FeaturesPentium4
constexpr FeatureBitset ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset FeaturesAlderlake
constexpr FeatureBitset ImpliedFeaturesSHA512
constexpr FeatureBitset ImpliedFeaturesAVXIFMA
constexpr FeatureBitset ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesXSAVEC
constexpr FeatureBitset FeaturesBDVER2
constexpr FeatureBitset ImpliedFeaturesSSE
constexpr FeatureBitset FeaturesKNM
constexpr FeatureBitset ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesAVX10_1_512
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset FeaturesGoldmont
constexpr FeatureBitset ImpliedFeaturesAVX2
constexpr FeatureBitset FeaturesBDVER4
constexpr FeatureBitset ImpliedFeaturesAVX512VL
constexpr FeatureBitset FeaturesSilvermont
constexpr FeatureBitset FeaturesCore2
constexpr FeatureBitset ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesRDSEED
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
constexpr FeatureBitset ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesSM3
constexpr FeatureBitset ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesADX
static constexpr FeatureBitset FeaturesZNVER4
constexpr FeatureBitset ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesUSERMSR
constexpr FeatureBitset FeaturesTigerlake
constexpr FeatureBitset ImpliedFeaturesAVX10_1
constexpr FeatureBitset ImpliedFeaturesRDRND
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This is a constexpr reimplementation of a subset of std::bitset.
Definition: Bitset.h:30
Container class for subtarget features.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
void push_back(const T &Elt)
Definition: SmallVector.h:416
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:857
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:112
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
Definition: StringRef.h:613
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Define some predicates that are used for node matching.
std::array< uint32_t, 4 > getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
char getCPUDispatchMangling(StringRef Name)
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features, bool NeedPlus=false)
Fill in the features that CPU supports into Features.
unsigned getFeaturePriority(ProcessorFeatures Feat)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
bool validateCPUSpecificCPUDispatch(StringRef Name)
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1753
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1883