LLVM 17.0.0git
X86TargetParser.cpp
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1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
15#include <numeric>
16
17using namespace llvm;
18using namespace llvm::X86;
19
20namespace {
21
22/// Container class for CPU features.
23/// This is a constexpr reimplementation of a subset of std::bitset. It would be
24/// nice to use std::bitset directly, but it doesn't support constant
25/// initialization.
26class FeatureBitset {
27 static constexpr unsigned NUM_FEATURE_WORDS =
28 (X86::CPU_FEATURE_MAX + 31) / 32;
29
30 // This cannot be a std::array, operator[] is not constexpr until C++17.
31 uint32_t Bits[NUM_FEATURE_WORDS] = {};
32
33public:
34 constexpr FeatureBitset() = default;
35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36 for (auto I : Init)
37 set(I);
38 }
39
40 bool any() const {
41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42 }
43
44 constexpr FeatureBitset &set(unsigned I) {
45 // GCC <6.2 crashes if this is written in a single statement.
46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47 Bits[I / 32] = NewBits;
48 return *this;
49 }
50
51 constexpr bool operator[](unsigned I) const {
52 uint32_t Mask = uint32_t(1) << (I % 32);
53 return (Bits[I / 32] & Mask) != 0;
54 }
55
56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
58 // GCC <6.2 crashes if this is written in a single statement.
59 uint32_t NewBits = Bits[I] & RHS.Bits[I];
60 Bits[I] = NewBits;
61 }
62 return *this;
63 }
64
65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
67 // GCC <6.2 crashes if this is written in a single statement.
68 uint32_t NewBits = Bits[I] | RHS.Bits[I];
69 Bits[I] = NewBits;
70 }
71 return *this;
72 }
73
74 // gcc 5.3 miscompiles this if we try to write this using operator&=.
75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
77 for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
78 Result.Bits[I] = Bits[I] & RHS.Bits[I];
79 return Result;
80 }
81
82 // gcc 5.3 miscompiles this if we try to write this using operator&=.
83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
85 for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
86 Result.Bits[I] = Bits[I] | RHS.Bits[I];
87 return Result;
88 }
89
90 constexpr FeatureBitset operator~() const {
92 for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
93 Result.Bits[I] = ~Bits[I];
94 return Result;
95 }
96
97 constexpr bool operator!=(const FeatureBitset &RHS) const {
98 for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
99 if (Bits[I] != RHS.Bits[I])
100 return true;
101 return false;
102 }
103};
104
105struct ProcInfo {
108 unsigned KeyFeature;
109 FeatureBitset Features;
110};
111
112struct FeatureInfo {
114 FeatureBitset ImpliedFeatures;
115};
116
117} // end anonymous namespace
118
119#define X86_FEATURE(ENUM, STRING) \
120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121#include "llvm/TargetParser/X86TargetParser.def"
122
123// Pentium with MMX.
125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126
127// Pentium 2 and 3.
129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
131
132// Pentium 4 CPUs
136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
137
138// Basic 64-bit capable CPU.
141 FeaturePOPCNT | FeatureCRC32 |
142 FeatureSSE4_2 | FeatureCMPXCHG16B;
144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
147 FeatureAVX512BW | FeatureAVX512CD |
148 FeatureAVX512DQ | FeatureAVX512VL;
149
150// Intel Core CPUs
152 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
153constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
155 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166
167// Intel Knights Landing and Knights Mill
168// Knights Landing has feature parity with Broadwell.
170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
172constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
173
174// Intel Skylake processors.
176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177 FeatureXSAVES | FeatureSGX;
178// SkylakeServer inherits all SkylakeClient features except SGX.
179// FIXME: That doesn't match gcc.
181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183 FeaturePKU;
185 FeaturesSkylakeServer | FeatureAVX512VNNI;
187 FeaturesCascadeLake | FeatureAVX512BF16;
188
189// Intel 10nm processors.
191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193 FeaturePKU | FeatureSHA;
195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
197 FeatureVAES | FeatureVPCLMULQDQ;
200 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
202 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
203 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
205 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
206 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
207 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
208 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
209 FeatureWAITPKG;
211 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI |
212 FeatureAMX_COMPLEX;
213
214// Intel Atom processors.
215// Bonnell has feature parity with Core2 and adds MOVBE.
216constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
217// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
219 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
221 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
222 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
223 FeatureXSAVEOPT | FeatureXSAVES;
225 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
227 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
229 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
230 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
231 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
232 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
233 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
235 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
236 FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
238 FeaturesSierraforest | FeatureRAOINT;
239
240// Geode Processor.
242 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
243
244// K6 processor.
245constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
246
247// K7 and K8 architecture processors.
249 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
251 FeaturesAthlon | FeatureFXSR | FeatureSSE;
253 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
254constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
256 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
257 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
258
259// Bobcat architecture processors.
261 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
262 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
263 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
264 FeatureSAHF;
266 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
267 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
268
269// AMD Bulldozer architecture processors.
271 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
272 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
273 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
274 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
275 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
276 FeatureXOP | FeatureXSAVE;
278 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
280 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
281constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
282 FeatureBMI2 | FeatureMOVBE |
283 FeatureMWAITX | FeatureRDRND;
284
285// AMD Zen architecture processors.
287 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
288 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
289 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
290 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
291 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
292 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
293 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
294 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
295 FeatureXSAVEOPT | FeatureXSAVES;
296constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
297 FeatureRDPID | FeatureRDPRU |
298 FeatureWBNOINVD;
300 FeatureINVPCID | FeaturePKU |
301 FeatureVAES | FeatureVPCLMULQDQ;
303 FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
304 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
305 FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
306 FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI |
307 FeatureSHSTK;
308
309constexpr ProcInfo Processors[] = {
310 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
311 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
312 // i386-generation processors.
313 { {"i386"}, CK_i386, ~0U, FeatureX87 },
314 // i486-generation processors.
315 { {"i486"}, CK_i486, ~0U, FeatureX87 },
316 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
317 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
318 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
319 // i586-generation processors, P5 microarchitecture based.
320 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
321 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
322 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
323 // i686-generation processors, P6 / Pentium M microarchitecture based.
324 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
325 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
326 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
327 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
328 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
329 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
330 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
331 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
332 // Netburst microarchitecture based processors.
333 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
334 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
335 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
336 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
337 // Core microarchitecture based processors.
338 { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2 },
339 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
340 // Atom processors
341 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
342 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
343 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
344 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
345 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
346 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
347 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
348 // Nehalem microarchitecture based processors.
349 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
350 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
351 // Westmere microarchitecture based processors.
352 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
353 // Sandy Bridge microarchitecture based processors.
354 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
355 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
356 // Ivy Bridge microarchitecture based processors.
357 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
358 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
359 // Haswell microarchitecture based processors.
360 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
361 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
362 // Broadwell microarchitecture based processors.
363 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
364 // Skylake client microarchitecture based processors.
365 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
366 // Skylake server microarchitecture based processors.
367 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
368 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
369 // Cascadelake Server microarchitecture based processors.
370 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
371 // Cooperlake Server microarchitecture based processors.
372 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
373 // Cannonlake client microarchitecture based processors.
374 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
375 // Icelake client microarchitecture based processors.
376 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
377 // Rocketlake microarchitecture based processors.
378 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
379 // Icelake server microarchitecture based processors.
380 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
381 // Tigerlake microarchitecture based processors.
382 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
383 // Sapphire Rapids microarchitecture based processors.
384 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
385 // Alderlake microarchitecture based processors.
386 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
387 // Raptorlake microarchitecture based processors.
388 { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake },
389 // Meteorlake microarchitecture based processors.
390 { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake },
391 // Sierraforest microarchitecture based processors.
392 { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest },
393 // Grandridge microarchitecture based processors.
394 { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge },
395 // Granite Rapids microarchitecture based processors.
396 { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids },
397 // Emerald Rapids microarchitecture based processors.
398 { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
399 // Knights Landing processor.
400 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
401 // Knights Mill processor.
402 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
403 // Lakemont microarchitecture based processors.
404 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
405 // K6 architecture processors.
406 { {"k6"}, CK_K6, ~0U, FeaturesK6 },
407 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
408 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
409 // K7 architecture processors.
410 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
411 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
412 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
413 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
414 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
415 // K8 architecture processors.
416 { {"k8"}, CK_K8, ~0U, FeaturesK8 },
417 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
418 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
419 { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
420 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
421 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
422 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
423 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
424 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
425 // Bobcat architecture processors.
426 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
427 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
428 // Bulldozer architecture processors.
429 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
430 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
431 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
432 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
433 // Zen architecture processors.
434 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
435 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
436 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
437 { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4 },
438 // Generic 64-bit processor.
439 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
440 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
441 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
442 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
443 // Geode processors.
444 { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
445};
446
447constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
448
450 for (const auto &P : Processors)
451 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
452 return P.Kind;
453
454 return CK_None;
455}
456
459 return CK_None;
460 return parseArchX86(CPU, Only64Bit);
461}
462
464 bool Only64Bit) {
465 for (const auto &P : Processors)
466 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
467 Values.emplace_back(P.Name);
468}
469
471 bool Only64Bit) {
472 for (const ProcInfo &P : Processors)
473 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
475 Values.emplace_back(P.Name);
476}
477
479 // FIXME: Can we avoid a linear search here? The table might be sorted by
480 // CPUKind so we could binary search?
481 for (const auto &P : Processors) {
482 if (P.Kind == Kind) {
483 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
484 return static_cast<ProcessorFeatures>(P.KeyFeature);
485 }
486 }
487
488 llvm_unreachable("Unable to find CPU kind!");
489}
490
491// Features with no dependencies.
537
538// Not really CPU features, but need to be in the table because clang uses
539// target features to communicate them to the backend.
545
546// XSAVE features are dependent on basic XSAVE.
547constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
548constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
549constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
550
551// MMX->3DNOW->3DNOWA chain.
553constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
554constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
555
556// SSE/AVX/AVX512F chain.
558constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
559constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
560constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
561constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
562constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
563constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
564constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
566 FeatureAVX2 | FeatureF16C | FeatureFMA;
567
568// Vector extensions that build on SSE or AVX.
569constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
570constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
571constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
572constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
573constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
574constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
575constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
576constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
577
578// AVX512 features.
579constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
580constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
581constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
582constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
583constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
584constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
585
586constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
587constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
588constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
589constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
591constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
592constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
594
595// FIXME: These two aren't really implemented and just exist in the feature
596// list for __builtin_cpu_supports. So omit their dependencies.
599
600// SSE4_A->FMA4->XOP chain.
601constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
602constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
603constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
604
605// AMX Features
607constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
608constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
609constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
610constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
612
617constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
620 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
621// Key Locker Features
622constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
624
625// AVXVNNI Features
626constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
627
628constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
629#define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
630#include "llvm/TargetParser/X86TargetParser.def"
631};
632
634 SmallVectorImpl<StringRef> &EnabledFeatures) {
636 [&](const ProcInfo &P) { return P.Name == CPU; });
637 assert(I != std::end(Processors) && "Processor not found!");
638
639 FeatureBitset Bits = I->Features;
640
641 // Remove the 64-bit feature which we only use to validate if a CPU can
642 // be used with 64-bit mode.
643 Bits &= ~Feature64BIT;
644
645 // Add the string version of all set bits.
646 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
647 if (Bits[i] && !FeatureInfos[i].Name.empty())
648 EnabledFeatures.push_back(FeatureInfos[i].Name);
649}
650
651// For each feature that is (transitively) implied by this feature, set it.
653 const FeatureBitset &Implies) {
654 // Fast path: Implies is often empty.
655 if (!Implies.any())
656 return;
657 FeatureBitset Prev;
658 Bits |= Implies;
659 do {
660 Prev = Bits;
661 for (unsigned i = CPU_FEATURE_MAX; i;)
662 if (Bits[--i])
663 Bits |= FeatureInfos[i].ImpliedFeatures;
664 } while (Prev != Bits);
665}
666
667/// Create bit vector of features that are implied disabled if the feature
668/// passed in Value is disabled.
669static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
670 // Check all features looking for any dependent on this feature. If we find
671 // one, mark it and recursively find any feature that depend on it.
672 FeatureBitset Prev;
673 Bits.set(Value);
674 do {
675 Prev = Bits;
676 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
677 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
678 Bits.set(i);
679 } while (Prev != Bits);
680}
681
683 StringRef Feature, bool Enabled,
684 StringMap<bool> &Features) {
685 auto I = llvm::find_if(
686 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
687 if (I == std::end(FeatureInfos)) {
688 // FIXME: This shouldn't happen, but may not have all features in the table
689 // yet.
690 return;
691 }
692
693 FeatureBitset ImpliedBits;
694 if (Enabled)
695 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
696 else
697 getImpliedDisabledFeatures(ImpliedBits,
698 std::distance(std::begin(FeatureInfos), I));
699
700 // Update the map entry for all implied features.
701 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
702 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
703 Features[FeatureInfos[i].Name] = Enabled;
704}
705
707 // Processor features and mapping to processor feature value.
708 uint64_t FeaturesMask = 0;
709 for (const StringRef &FeatureStr : FeatureStrs) {
710 unsigned Feature = StringSwitch<unsigned>(FeatureStr)
711#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
712 .Case(STR, llvm::X86::FEATURE_##ENUM)
713#include "llvm/TargetParser/X86TargetParser.def"
714 ;
715 FeaturesMask |= (1ULL << Feature);
716 }
717 return FeaturesMask;
718}
719
721#ifndef NDEBUG
722 // Check that priorities are set properly in the .def file. We expect that
723 // "compat" features are assigned non-duplicate consecutive priorities
724 // starting from zero (0, 1, ..., num_features - 1).
725#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
726 unsigned Priorities[] = {
727#include "llvm/TargetParser/X86TargetParser.def"
728 std::numeric_limits<unsigned>::max() // Need to consume last comma.
729 };
730 std::array<unsigned, std::size(Priorities) - 1> HelperList;
731 std::iota(HelperList.begin(), HelperList.end(), 0);
732 assert(std::is_permutation(HelperList.begin(), HelperList.end(),
733 std::begin(Priorities),
734 std::prev(std::end(Priorities))) &&
735 "Priorities don't form consecutive range!");
736#endif
737
738 switch (Feat) {
739#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
740 case X86::FEATURE_##ENUM: \
741 return PRIORITY;
742#include "llvm/TargetParser/X86TargetParser.def"
743 default:
744 llvm_unreachable("No Feature Priority for non-CPUSupports Features");
745 }
746}
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
std::string Name
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool Enabled
Definition: Statistic.cpp:46
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Value * RHS
constexpr FeatureBitset FeaturesX86_64
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset FeaturesWestmere
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset FeaturesAthlon
constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesSSE4_1
constexpr FeatureBitset FeaturesZNVER2
constexpr FeatureBitset FeaturesBDVER3
constexpr FeatureBitset ImpliedFeaturesBMI2
constexpr FeatureBitset FeaturesGeode
constexpr FeatureBitset ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesPREFETCHI
constexpr FeatureBitset ImpliedFeaturesAVX512FP16
constexpr FeatureBitset FeaturesCascadeLake
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset FeaturesGrandridge
constexpr FeatureBitset FeaturesK8SSE3
constexpr FeatureBitset FeaturesZNVER1
constexpr FeatureBitset FeaturesNocona
constexpr FeatureBitset ImpliedFeaturesSSE4_A
constexpr FeatureBitset FeaturesPrescott
constexpr FeatureBitset FeaturesCooperLake
constexpr FeatureBitset ImpliedFeaturesFXSR
constexpr FeatureBitset FeaturesSapphireRapids
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesAES
constexpr FeatureBitset FeaturesTremont
constexpr FeatureBitset FeaturesBDVER1
constexpr FeatureBitset ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesCRC32
static constexpr FeatureBitset FeaturesZNVER3
constexpr FeatureBitset FeaturesGoldmontPlus
constexpr FeatureBitset ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesPRFCHW
constexpr FeatureBitset FeaturesCannonlake
constexpr FeatureBitset ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesVAES
constexpr FeatureBitset FeaturesSandyBridge
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesRDPRU
constexpr FeatureBitset FeaturesAMDFAM10
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
constexpr FeatureBitset FeaturesSkylakeServer
constexpr FeatureBitset FeaturesPentiumMMX
constexpr FeatureBitset ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset FeaturesKNL
constexpr FeatureBitset FeaturesNehalem
constexpr FeatureBitset FeaturesBTVER1
constexpr FeatureBitset FeaturesPentium3
constexpr FeatureBitset ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT
constexpr FeatureBitset FeaturesAthlonXP
constexpr FeatureBitset FeaturesGraniteRapids
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
constexpr FeatureBitset ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesAVX
constexpr FeatureBitset FeaturesX86_64_V3
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesXSAVE
constexpr FeatureBitset FeaturesX86_64_V2
constexpr FeatureBitset ImpliedFeaturesMOVBE
constexpr FeatureBitset FeaturesIvyBridge
constexpr FeatureBitset FeaturesHaswell
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8
constexpr FeatureBitset FeaturesICLClient
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
constexpr FeatureBitset ImpliedFeaturesHRESET
constexpr const char * NoTuneList[]
constexpr FeatureBitset ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesRTM
constexpr FeatureBitset FeaturesRocketlake
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset FeaturesBTVER2
constexpr FeatureBitset FeaturesSkylakeClient
constexpr FeatureBitset ImpliedFeatures3DNOWA
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
constexpr FeatureBitset FeaturesPentium2
constexpr FeatureBitset ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesAMX_FP16
constexpr FeatureBitset ImpliedFeaturesMMX
constexpr FeatureBitset FeaturesICLServer
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
constexpr FeatureBitset FeaturesBroadwell
constexpr ProcInfo Processors[]
constexpr FeatureBitset ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA
constexpr FeatureBitset FeaturesSierraforest
constexpr FeatureBitset FeaturesK6
constexpr FeatureBitset ImpliedFeaturesRAOINT
constexpr FeatureBitset FeaturesX86_64_V4
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesSSE2
constexpr FeatureBitset FeaturesBonnell
constexpr FeatureBitset FeaturesPenryn
constexpr FeatureBitset ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeatures64BIT
constexpr FeatureBitset FeaturesK8
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPTWRITE
constexpr FeatureBitset FeaturesPentium4
constexpr FeatureBitset ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset FeaturesAlderlake
constexpr FeatureBitset ImpliedFeaturesAVXIFMA
constexpr FeatureBitset ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesXSAVEC
constexpr FeatureBitset FeaturesBDVER2
constexpr FeatureBitset ImpliedFeaturesSSE
constexpr FeatureBitset FeaturesKNM
constexpr FeatureBitset ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset FeaturesGoldmont
constexpr FeatureBitset ImpliedFeaturesAVX2
constexpr FeatureBitset FeaturesBDVER4
constexpr FeatureBitset ImpliedFeaturesAVX512VL
constexpr FeatureBitset FeaturesSilvermont
constexpr FeatureBitset FeaturesCore2
constexpr FeatureBitset ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesRDSEED
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
constexpr FeatureBitset ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesADX
static constexpr FeatureBitset FeaturesZNVER4
constexpr FeatureBitset ImpliedFeaturesSHA
constexpr FeatureBitset FeaturesTigerlake
constexpr FeatureBitset ImpliedFeaturesRDRND
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Container class for subtarget features.
constexpr FeatureBitset & operator&=(const FeatureBitset &RHS)
constexpr FeatureBitset & operator|=(const FeatureBitset &RHS)
constexpr bool operator[](unsigned I) const
bool operator!=(const FeatureBitset &RHS) const
FeatureBitset & set()
constexpr FeatureBitset()=default
constexpr FeatureBitset operator|(const FeatureBitset &RHS) const
constexpr FeatureBitset operator&(const FeatureBitset &RHS) const
constexpr FeatureBitset operator~() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
void push_back(const T &Elt)
Definition: SmallVector.h:416
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:851
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:111
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:119
Define some predicates that are used for node matching.
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features)
Fill in the features that CPU supports into Features.
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
unsigned getFeaturePriority(ProcessorFeatures Feat)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1826
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1846
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1976