LLVM 20.0.0git
X86TargetParser.cpp
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1//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise X86 hardware features.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/Bitset.h"
16#include <numeric>
17
18using namespace llvm;
19using namespace llvm::X86;
20
21namespace {
22
24
25struct ProcInfo {
28 unsigned KeyFeature;
29 FeatureBitset Features;
30 char Mangling;
31 bool OnlyForCPUDispatchSpecific;
32};
33
34struct FeatureInfo {
35 StringLiteral NameWithPlus;
36 FeatureBitset ImpliedFeatures;
37
38 StringRef getName(bool WithPlus = false) const {
39 assert(NameWithPlus[0] == '+' && "Expected string to start with '+'");
40 if (WithPlus)
41 return NameWithPlus;
42 return NameWithPlus.drop_front();
43 }
44};
45
46} // end anonymous namespace
47
48#define X86_FEATURE(ENUM, STRING) \
49 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
50#include "llvm/TargetParser/X86TargetParser.def"
51
52// Pentium with MMX.
54 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
55
56// Pentium 2 and 3.
58 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV;
60
61// Pentium 4 CPUs
65 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
66
67// Basic 64-bit capable CPU.
70 FeaturePOPCNT | FeatureCRC32 |
71 FeatureSSE4_2 | FeatureCMPXCHG16B;
73 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
74 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
76 FeatureAVX512BW | FeatureAVX512CD |
77 FeatureAVX512DQ | FeatureAVX512VL;
78
79// Intel Core CPUs
81 FeaturesNocona | FeatureSAHF | FeatureSSSE3;
82constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
84 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
87 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
89 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
91 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
92 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
94 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
95
96// Intel Knights Landing and Knights Mill
97// Knights Landing has feature parity with Broadwell.
99 FeatureAVX512F | FeatureEVEX512 |
100 FeatureAVX512CD;
101constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
102
103// Intel Skylake processors.
105 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
106 FeatureXSAVES | FeatureSGX;
107// SkylakeServer inherits all SkylakeClient features except SGX.
108// FIXME: That doesn't match gcc.
110 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 |
111 FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL |
112 FeatureCLWB | FeaturePKU;
114 FeaturesSkylakeServer | FeatureAVX512VNNI;
116 FeaturesCascadeLake | FeatureAVX512BF16;
117
118// Intel 10nm processors.
120 FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
121 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
122 FeatureAVX512VBMI | FeaturePKU | FeatureSHA;
124 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
125 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
126 FeatureVAES | FeatureVPCLMULQDQ;
129 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
131 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
132 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
134 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
135 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
136 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
137 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
138 FeatureWAITPKG;
140 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
141
142// Intel Atom processors.
143// Bonnell has feature parity with Core2 and adds MOVBE.
144constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
145// Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
147 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
149 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
150 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
151 FeatureXSAVEOPT | FeatureXSAVES;
153 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
155 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
157 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
158 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
159 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
160 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
161 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
163 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR |
164 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
166 FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4;
168 FeaturesArrowlakeS | FeaturePREFETCHI;
170 FeaturesArrowlakeS | FeatureUSERMSR | FeaturePREFETCHI;
171
172// Geode Processor.
174 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
175
176// K6 processor.
177constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
178
179// K7 and K8 architecture processors.
181 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeaturePRFCHW;
183 FeaturesAthlon | FeatureFXSR | FeatureSSE;
185 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
186constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
188 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
189 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
190
191// Bobcat architecture processors.
193 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
194 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
195 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
196 FeatureSAHF;
198 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
199 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
200
201// AMD Bulldozer architecture processors.
203 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
204 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
205 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
206 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
207 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
208 FeatureXOP | FeatureXSAVE;
210 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
212 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
213constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
214 FeatureBMI2 | FeatureMOVBE |
215 FeatureMWAITX | FeatureRDRND;
216
217// AMD Zen architecture processors.
219 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
220 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
221 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
222 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
223 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
224 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
225 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
226 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
227 FeatureXSAVEOPT | FeatureXSAVES;
228constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
229 FeatureRDPID | FeatureRDPRU |
230 FeatureWBNOINVD;
232 FeatureINVPCID | FeaturePKU |
233 FeatureVAES | FeatureVPCLMULQDQ;
235 FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD |
236 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA |
237 FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI |
238 FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 |
239 FeatureGFNI | FeatureSHSTK;
240
241// D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from
242// X86TargetParser.def to here. They are assigned by following ways:
243// 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign
244// to '\0' by default, which means not support cpu_specific/dispatch feature.
245// 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not
246// listed here before, which means it doesn't support -march, -mtune and so on.
247// FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both
248// cpu_dispatch/specific() feature and -march, -mtune, and so on.
249// clang-format off
250constexpr ProcInfo Processors[] = {
251 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
252 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
253 { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true },
254 // i386-generation processors.
255 { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false },
256 // i486-generation processors.
257 { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false },
258 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false },
259 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
260 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | FeaturePRFCHW, '\0', false },
261 // i586-generation processors, P5 microarchitecture based.
262 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false },
263 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false },
264 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false },
265 { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true },
266 // i686-generation processors, P6 / Pentium M microarchitecture based.
267 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false },
268 { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true },
269 { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false },
270 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false },
271 { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true },
272 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
273 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false },
274 { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
275 { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true },
276 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false },
277 { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true },
278 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false },
279 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false },
280 // Netburst microarchitecture based processors.
281 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
282 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false },
283 { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true },
284 { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true },
285 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false },
286 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false },
287 // Core microarchitecture based processors.
288 { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false },
289 { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true },
290 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false },
291 { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true },
292 // Atom processors
293 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
294 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false },
295 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
296 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false },
297 { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true },
298 { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true },
299 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false },
300 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false },
301 { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true },
302 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false },
303 // Nehalem microarchitecture based processors.
304 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
305 { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true },
306 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false },
307 // Westmere microarchitecture based processors.
308 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false },
309 { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true },
310 // Sandy Bridge microarchitecture based processors.
311 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false },
312 { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true },
313 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false },
314 // Ivy Bridge microarchitecture based processors.
315 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false },
316 { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true },
317 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false },
318 // Haswell microarchitecture based processors.
319 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false },
320 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false },
321 { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true },
322 { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true },
323 // Broadwell microarchitecture based processors.
324 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false },
325 { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true },
326 { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true },
327 // Skylake client microarchitecture based processors.
328 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false },
329 // Skylake server microarchitecture based processors.
330 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false },
331 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false },
332 { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true },
333 // Cascadelake Server microarchitecture based processors.
334 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false },
335 // Cooperlake Server microarchitecture based processors.
336 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false },
337 // Cannonlake client microarchitecture based processors.
338 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false },
339 // Icelake client microarchitecture based processors.
340 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false },
341 { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true },
342 // Rocketlake microarchitecture based processors.
343 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false },
344 // Icelake server microarchitecture based processors.
345 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false },
346 { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true },
347 // Tigerlake microarchitecture based processors.
348 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false },
349 // Sapphire Rapids microarchitecture based processors.
350 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
351 // Alderlake microarchitecture based processors.
352 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
353 // Raptorlake microarchitecture based processors.
354 { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
355 // Meteorlake microarchitecture based processors.
356 { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
357 // Arrowlake microarchitecture based processors.
358 { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
359 { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false },
360 { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true },
361 // Lunarlake microarchitecture based processors.
362 { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false },
363 // Gracemont microarchitecture based processors.
364 { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false },
365 // Pantherlake microarchitecture based processors.
366 { {"pantherlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesPantherlake, 'p', false },
367 // Sierraforest microarchitecture based processors.
368 { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
369 // Grandridge microarchitecture based processors.
370 { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false },
371 // Granite Rapids microarchitecture based processors.
372 { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512FP16, FeaturesGraniteRapids, 'n', false },
373 // Granite Rapids D microarchitecture based processors.
374 { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false },
375 { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true },
376 // Emerald Rapids microarchitecture based processors.
377 { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
378 // Clearwaterforest microarchitecture based processors.
379 { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
380 // Knights Landing processor.
381 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
382 { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
383 // Knights Mill processor.
384 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false },
385 // Lakemont microarchitecture based processors.
386 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false },
387 // K6 architecture processors.
388 { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false },
389 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
390 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | FeaturePRFCHW, '\0', false },
391 // K7 architecture processors.
392 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
393 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false },
394 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
395 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
396 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false },
397 // K8 architecture processors.
398 { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false },
399 { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false },
400 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false },
401 { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false },
402 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
403 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
404 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false },
405 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
406 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false },
407 // Bobcat architecture processors.
408 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false },
409 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false },
410 // Bulldozer architecture processors.
411 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false },
412 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false },
413 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false },
414 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false },
415 // Zen architecture processors.
416 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false },
417 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false },
418 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false },
419 { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false },
420 // Generic 64-bit processor.
421 { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false },
422 { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false },
423 { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false },
424 { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false },
425 // Geode processors.
426 { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false },
427};
428// clang-format on
429
430constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
431
433 for (const auto &P : Processors)
434 if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU &&
435 (P.Features[FEATURE_64BIT] || !Only64Bit))
436 return P.Kind;
437
438 return CK_None;
439}
440
443 return CK_None;
444 return parseArchX86(CPU, Only64Bit);
445}
446
448 bool Only64Bit) {
449 for (const auto &P : Processors)
450 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
451 (P.Features[FEATURE_64BIT] || !Only64Bit))
452 Values.emplace_back(P.Name);
453}
454
456 bool Only64Bit) {
457 for (const ProcInfo &P : Processors)
458 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() &&
459 (P.Features[FEATURE_64BIT] || !Only64Bit) &&
461 Values.emplace_back(P.Name);
462}
463
465 // FIXME: Can we avoid a linear search here? The table might be sorted by
466 // CPUKind so we could binary search?
467 for (const auto &P : Processors) {
468 if (P.Kind == Kind) {
469 assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
470 return static_cast<ProcessorFeatures>(P.KeyFeature);
471 }
472 }
473
474 llvm_unreachable("Unable to find CPU kind!");
475}
476
477// Features with no dependencies.
526
527// Not really CPU features, but need to be in the table because clang uses
528// target features to communicate them to the backend.
534
535// XSAVE features are dependent on basic XSAVE.
536constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
537constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
538constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
539
540// SSE/AVX/AVX512F chain.
542constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
543constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
544constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
545constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
546constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
547constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
548constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
551 FeatureAVX2 | FeatureF16C | FeatureFMA;
552
553// Vector extensions that build on SSE or AVX.
554constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
555constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
556constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
557constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
558constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
559constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
560constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2;
561constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
562constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
563constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2;
564
565// AVX512 features.
566constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
567constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
568constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
569constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
570
571constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
572constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
573constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
574constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
576constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
577constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
579
580// FIXME: These two aren't really implemented and just exist in the feature
581// list for __builtin_cpu_supports. So omit their dependencies.
584
585// SSE4_A->FMA4->XOP chain.
586constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
587constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
588constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
589
590// AMX Features
592constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
593constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
594constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
595constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE;
597
603constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
605constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2;
607 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
608// Key Locker Features
609constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
611
612// AVXVNNI Features
613constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
614
615// AVX10 Features
617 FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA |
618 FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ |
619 FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ |
620 FeatureAVX512FP16;
622 FeatureAVX10_1 | FeatureEVEX512;
623constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1;
625 FeatureAVX10_2 | FeatureAVX10_1_512;
626
627// APX Features
636
637constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
638#define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM},
639#include "llvm/TargetParser/X86TargetParser.def"
640};
641
643 SmallVectorImpl<StringRef> &EnabledFeatures,
644 bool NeedPlus) {
646 [&](const ProcInfo &P) { return P.Name == CPU; });
647 assert(I != std::end(Processors) && "Processor not found!");
648
649 FeatureBitset Bits = I->Features;
650
651 // Remove the 64-bit feature which we only use to validate if a CPU can
652 // be used with 64-bit mode.
653 Bits &= ~Feature64BIT;
654
655 // Add the string version of all set bits.
656 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
657 if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty())
658 EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus));
659}
660
661// For each feature that is (transitively) implied by this feature, set it.
663 const FeatureBitset &Implies) {
664 // Fast path: Implies is often empty.
665 if (!Implies.any())
666 return;
667 FeatureBitset Prev;
668 Bits |= Implies;
669 do {
670 Prev = Bits;
671 for (unsigned i = CPU_FEATURE_MAX; i;)
672 if (Bits[--i])
673 Bits |= FeatureInfos[i].ImpliedFeatures;
674 } while (Prev != Bits);
675}
676
677/// Create bit vector of features that are implied disabled if the feature
678/// passed in Value is disabled.
679static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) {
680 // Check all features looking for any dependent on this feature. If we find
681 // one, mark it and recursively find any feature that depend on it.
682 FeatureBitset Prev;
683 Bits.set(Value);
684 do {
685 Prev = Bits;
686 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
687 if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
688 Bits.set(i);
689 } while (Prev != Bits);
690}
691
693 StringRef Feature, bool Enabled,
694 StringMap<bool> &Features) {
695 auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) {
696 return FI.getName() == Feature;
697 });
698 if (I == std::end(FeatureInfos)) {
699 // FIXME: This shouldn't happen, but may not have all features in the table
700 // yet.
701 return;
702 }
703
704 FeatureBitset ImpliedBits;
705 if (Enabled)
706 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
707 else
708 getImpliedDisabledFeatures(ImpliedBits,
709 std::distance(std::begin(FeatureInfos), I));
710
711 // Update the map entry for all implied features.
712 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
713 if (ImpliedBits[i] && !FeatureInfos[i].getName().empty())
714 Features[FeatureInfos[i].getName()] = Enabled;
715}
716
719 [&](const ProcInfo &P) { return P.Name == CPU; });
720 assert(I != std::end(Processors) && "Processor not found!");
721 assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!");
722 return I->Mangling;
723}
724
727 [&](const ProcInfo &P) { return P.Name == Name; });
728 return I != std::end(Processors);
729}
730
731std::array<uint32_t, 4>
733 // Processor features and mapping to processor feature value.
734 std::array<uint32_t, 4> FeatureMask{};
735 for (StringRef FeatureStr : FeatureStrs) {
736 unsigned Feature = StringSwitch<unsigned>(FeatureStr)
737#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
738 .Case(STR, llvm::X86::FEATURE_##ENUM)
739#define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) \
740 .Case(STR, llvm::X86::FEATURE_##ENUM)
741#include "llvm/TargetParser/X86TargetParser.def"
742 ;
743 assert(Feature / 32 < FeatureMask.size());
744 FeatureMask[Feature / 32] |= 1U << (Feature % 32);
745 }
746 return FeatureMask;
747}
748
750#ifndef NDEBUG
751 // Check that priorities are set properly in the .def file. We expect that
752 // "compat" features are assigned non-duplicate consecutive priorities
753 // starting from one (1, ..., 37) and multiple zeros.
754#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
755 unsigned Priorities[] = {
756#include "llvm/TargetParser/X86TargetParser.def"
757 };
758 std::array<unsigned, std::size(Priorities)> HelperList;
759 const size_t MaxPriority = 37;
760 std::iota(HelperList.begin(), HelperList.begin() + MaxPriority + 1, 0);
761 for (size_t i = MaxPriority + 1; i != std::size(Priorities); ++i)
762 HelperList[i] = 0;
763 assert(std::is_permutation(HelperList.begin(), HelperList.end(),
764 std::begin(Priorities), std::end(Priorities)) &&
765 "Priorities don't form consecutive range!");
766#endif
767
768 switch (Feat) {
769#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
770 case X86::FEATURE_##ENUM: \
771 return PRIORITY;
772#include "llvm/TargetParser/X86TargetParser.def"
773 default:
774 llvm_unreachable("No Feature Priority for non-CPUSupports Features");
775 }
776}
std::string Name
#define I(x, y, z)
Definition: MD5.cpp:58
#define P(N)
static StringRef getName(Value *V)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool Enabled
Definition: Statistic.cpp:46
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
constexpr FeatureBitset FeaturesClearwaterforest
constexpr FeatureBitset FeaturesX86_64
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset FeaturesWestmere
constexpr FeatureBitset ImpliedFeaturesNDD
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset FeaturesAthlon
constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesSSE4_1
constexpr FeatureBitset FeaturesZNVER2
constexpr FeatureBitset FeaturesBDVER3
constexpr FeatureBitset ImpliedFeaturesBMI2
constexpr FeatureBitset FeaturesGeode
constexpr FeatureBitset ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesPREFETCHI
constexpr FeatureBitset ImpliedFeaturesAVX512FP16
constexpr FeatureBitset FeaturesCascadeLake
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset FeaturesK8SSE3
constexpr FeatureBitset FeaturesZNVER1
constexpr FeatureBitset FeaturesNocona
constexpr FeatureBitset ImpliedFeaturesEVEX512
constexpr FeatureBitset ImpliedFeaturesSSE4_A
constexpr FeatureBitset FeaturesPrescott
constexpr FeatureBitset FeaturesCooperLake
constexpr FeatureBitset ImpliedFeaturesEGPR
constexpr FeatureBitset ImpliedFeaturesFXSR
constexpr FeatureBitset FeaturesSapphireRapids
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesAES
constexpr FeatureBitset FeaturesTremont
constexpr FeatureBitset ImpliedFeaturesPush2Pop2
constexpr FeatureBitset FeaturesBDVER1
constexpr FeatureBitset ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesCRC32
static constexpr FeatureBitset FeaturesZNVER3
constexpr FeatureBitset FeaturesGoldmontPlus
constexpr FeatureBitset ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesPRFCHW
constexpr FeatureBitset FeaturesCannonlake
constexpr FeatureBitset ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesVAES
constexpr FeatureBitset FeaturesSandyBridge
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesRDPRU
constexpr FeatureBitset FeaturesAMDFAM10
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
constexpr FeatureBitset FeaturesSkylakeServer
constexpr FeatureBitset FeaturesPentiumMMX
constexpr FeatureBitset ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset FeaturesKNL
constexpr FeatureBitset FeaturesNehalem
constexpr FeatureBitset FeaturesBTVER1
constexpr FeatureBitset FeaturesPentium3
constexpr FeatureBitset ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT
constexpr FeatureBitset FeaturesAthlonXP
constexpr FeatureBitset FeaturesGraniteRapids
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
constexpr FeatureBitset FeaturesPantherlake
constexpr FeatureBitset ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesAVX
constexpr FeatureBitset FeaturesX86_64_V3
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesAVX10_2
constexpr FeatureBitset ImpliedFeaturesXSAVE
constexpr FeatureBitset FeaturesX86_64_V2
constexpr FeatureBitset FeaturesArrowlakeS
constexpr FeatureBitset ImpliedFeaturesMOVBE
constexpr FeatureBitset FeaturesIvyBridge
constexpr FeatureBitset FeaturesHaswell
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8
constexpr FeatureBitset ImpliedFeaturesCCMP
constexpr FeatureBitset FeaturesICLClient
constexpr FeatureBitset ImpliedFeaturesCF
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
constexpr FeatureBitset ImpliedFeaturesHRESET
constexpr const char * NoTuneList[]
constexpr FeatureBitset ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesRTM
constexpr FeatureBitset FeaturesRocketlake
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset FeaturesBTVER2
constexpr FeatureBitset FeaturesSkylakeClient
constexpr FeatureBitset ImpliedFeaturesPPX
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
constexpr FeatureBitset FeaturesPentium2
constexpr FeatureBitset ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE2
constexpr FeatureBitset ImpliedFeaturesAMX_FP16
constexpr FeatureBitset ImpliedFeaturesMMX
constexpr FeatureBitset FeaturesICLServer
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
constexpr FeatureBitset FeaturesBroadwell
constexpr ProcInfo Processors[]
constexpr FeatureBitset ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16
constexpr FeatureBitset ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA
constexpr FeatureBitset FeaturesSierraforest
constexpr FeatureBitset FeaturesK6
constexpr FeatureBitset ImpliedFeaturesRAOINT
constexpr FeatureBitset FeaturesX86_64_V4
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesSSE2
constexpr FeatureBitset FeaturesBonnell
constexpr FeatureBitset FeaturesPenryn
constexpr FeatureBitset ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeaturesAVX10_2_512
constexpr FeatureBitset ImpliedFeatures64BIT
constexpr FeatureBitset FeaturesK8
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesSM4
constexpr FeatureBitset ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesPTWRITE
constexpr FeatureBitset FeaturesPentium4
constexpr FeatureBitset ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset FeaturesAlderlake
constexpr FeatureBitset ImpliedFeaturesSHA512
constexpr FeatureBitset ImpliedFeaturesAVXIFMA
constexpr FeatureBitset ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesXSAVEC
constexpr FeatureBitset FeaturesBDVER2
constexpr FeatureBitset ImpliedFeaturesSSE
constexpr FeatureBitset ImpliedFeaturesNF
constexpr FeatureBitset FeaturesKNM
constexpr FeatureBitset ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesAVX10_1_512
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset FeaturesGoldmont
constexpr FeatureBitset ImpliedFeaturesAVX2
constexpr FeatureBitset FeaturesBDVER4
constexpr FeatureBitset ImpliedFeaturesAVX512VL
constexpr FeatureBitset FeaturesSilvermont
constexpr FeatureBitset FeaturesCore2
constexpr FeatureBitset ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesRDSEED
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
constexpr FeatureBitset ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesSM3
constexpr FeatureBitset ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesADX
static constexpr FeatureBitset FeaturesZNVER4
constexpr FeatureBitset ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesDUMMYFEATURE1
constexpr FeatureBitset ImpliedFeaturesUSERMSR
constexpr FeatureBitset FeaturesTigerlake
constexpr FeatureBitset ImpliedFeaturesAVX10_1
constexpr FeatureBitset ImpliedFeaturesRDRND
constexpr FeatureBitset ImpliedFeaturesZU
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This is a constexpr reimplementation of a subset of std::bitset.
Definition: Bitset.h:30
Container class for subtarget features.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:951
void push_back(const T &Elt)
Definition: SmallVector.h:427
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:838
StringMap - This is an unconventional map that is specialized for handling keys that are "strings",...
Definition: StringMap.h:128
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
Definition: StringRef.h:594
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Define some predicates that are used for node matching.
std::array< uint32_t, 4 > getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
char getCPUDispatchMangling(StringRef Name)
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features, bool NeedPlus=false)
Fill in the features that CPU supports into Features.
unsigned getFeaturePriority(ProcessorFeatures Feat)
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
bool validateCPUSpecificCPUDispatch(StringRef Name)
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1749
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879