LLVM  13.0.0git
X86TargetParser.cpp
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1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/Triple.h"
15 
16 using namespace llvm;
17 using namespace llvm::X86;
18 
19 namespace {
20 
21 /// Container class for CPU features.
22 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
23 /// nice to use std::bitset directly, but it doesn't support constant
24 /// initialization.
25 class FeatureBitset {
26  static constexpr unsigned NUM_FEATURE_WORDS =
27  (X86::CPU_FEATURE_MAX + 31) / 32;
28 
29  // This cannot be a std::array, operator[] is not constexpr until C++17.
30  uint32_t Bits[NUM_FEATURE_WORDS] = {};
31 
32 public:
33  constexpr FeatureBitset() = default;
34  constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
35  for (auto I : Init)
36  set(I);
37  }
38 
39  bool any() const {
40  return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
41  }
42 
43  constexpr FeatureBitset &set(unsigned I) {
44  // GCC <6.2 crashes if this is written in a single statement.
45  uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
46  Bits[I / 32] = NewBits;
47  return *this;
48  }
49 
50  constexpr bool operator[](unsigned I) const {
51  uint32_t Mask = uint32_t(1) << (I % 32);
52  return (Bits[I / 32] & Mask) != 0;
53  }
54 
55  constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
56  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
57  // GCC <6.2 crashes if this is written in a single statement.
58  uint32_t NewBits = Bits[I] & RHS.Bits[I];
59  Bits[I] = NewBits;
60  }
61  return *this;
62  }
63 
64  constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
65  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I) {
66  // GCC <6.2 crashes if this is written in a single statement.
67  uint32_t NewBits = Bits[I] | RHS.Bits[I];
68  Bits[I] = NewBits;
69  }
70  return *this;
71  }
72 
73  // gcc 5.3 miscompiles this if we try to write this using operator&=.
74  constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
76  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
77  Result.Bits[I] = Bits[I] & RHS.Bits[I];
78  return Result;
79  }
80 
81  // gcc 5.3 miscompiles this if we try to write this using operator&=.
82  constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
84  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
85  Result.Bits[I] = Bits[I] | RHS.Bits[I];
86  return Result;
87  }
88 
89  constexpr FeatureBitset operator~() const {
91  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
92  Result.Bits[I] = ~Bits[I];
93  return Result;
94  }
95 
96  constexpr bool operator!=(const FeatureBitset &RHS) const {
97  for (unsigned I = 0, E = array_lengthof(Bits); I != E; ++I)
98  if (Bits[I] != RHS.Bits[I])
99  return true;
100  return false;
101  }
102 };
103 
104 struct ProcInfo {
107  unsigned KeyFeature;
108  FeatureBitset Features;
109 };
110 
111 struct FeatureInfo {
113  FeatureBitset ImpliedFeatures;
114 };
115 
116 } // end anonymous namespace
117 
118 #define X86_FEATURE(ENUM, STRING) \
119  constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
120 #include "llvm/Support/X86TargetParser.def"
121 
122 // Pentium with MMX.
124  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
125 
126 // Pentium 2 and 3.
128  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
130 
131 // Pentium 4 CPUs
135  FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
136 
137 // Basic 64-bit capable CPU.
138 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
139 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
140  FeaturePOPCNT | FeatureSSE4_2 |
141  FeatureCMPXCHG16B;
143  FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
144  FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
146  FeatureAVX512BW | FeatureAVX512CD |
147  FeatureAVX512DQ | FeatureAVX512VL;
148 
149 // Intel Core CPUs
151  FeaturesNocona | FeatureSAHF | FeatureSSSE3;
152 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
154  FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2;
155 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
157  FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
159  FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
161  FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
162  FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
164  FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
165 
166 // Intel Knights Landing and Knights Mill
167 // Knights Landing has feature parity with Broadwell.
169  FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
170  FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
171 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
172 
173 // Intel Skylake processors.
175  FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
176  FeatureXSAVES | FeatureSGX;
177 // SkylakeServer inherits all SkylakeClient features except SGX.
178 // FIXME: That doesn't match gcc.
180  (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
181  FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
182  FeaturePKU;
184  FeaturesSkylakeServer | FeatureAVX512VNNI;
186  FeaturesCascadeLake | FeatureAVX512BF16;
187 
188 // Intel 10nm processors.
190  FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
191  FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
192  FeaturePKU | FeatureSHA;
194  FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
195  FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
196  FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
198  FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
200  FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
201  FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
203  FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
204  FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE |
205  FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
206  FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
207  FeatureWAITPKG | FeatureAVXVNNI;
209  FeaturesSkylakeClient | FeatureCLDEMOTE | FeatureHRESET | FeaturePTWRITE |
210  FeatureSERIALIZE | FeatureWAITPKG | FeatureAVXVNNI;
211 
212 // Intel Atom processors.
213 // Bonnell has feature parity with Core2 and adds MOVBE.
214 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
215 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
217  FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
219  FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
220  FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
221  FeatureXSAVEOPT | FeatureXSAVES;
223  FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
225  FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
226 
227 // Geode Processor.
229  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
230 
231 // K6 processor.
232 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
233 
234 // K7 and K8 architecture processors.
236  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
238  FeaturesAthlon | FeatureFXSR | FeatureSSE;
240  FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
241 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
243  FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
244  FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
245 
246 // Bobcat architecture processors.
248  FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
249  FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
250  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
251  FeatureSAHF;
253  FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C |
254  FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
255 
256 // AMD Bulldozer architecture processors.
258  FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
259  FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP |
260  FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW |
261  FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 |
262  FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE;
264  FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
266  FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
267 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
268  FeatureBMI2 | FeatureMOVBE |
269  FeatureMWAITX | FeatureRDRND;
270 
271 // AMD Zen architecture processors.
273  FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
274  FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
275  FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C |
276  FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX |
277  FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
278  FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
279  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
280  FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
281  FeatureXSAVEOPT | FeatureXSAVES;
283  FeaturesZNVER1 | FeatureCLWB | FeatureRDPID | FeatureWBNOINVD;
285  FeatureINVPCID | FeaturePKU |
286  FeatureVAES | FeatureVPCLMULQDQ;
287 
288 constexpr ProcInfo Processors[] = {
289  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
290  { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
291  // i386-generation processors.
292  { {"i386"}, CK_i386, ~0U, FeatureX87 },
293  // i486-generation processors.
294  { {"i486"}, CK_i486, ~0U, FeatureX87 },
295  { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
296  { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
297  { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
298  // i586-generation processors, P5 microarchitecture based.
299  { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
300  { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
301  { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
302  // i686-generation processors, P6 / Pentium M microarchitecture based.
303  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
304  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
305  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
306  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
307  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
308  { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
309  { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
310  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
311  // Netburst microarchitecture based processors.
312  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
313  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
314  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
315  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
316  // Core microarchitecture based processors.
317  { {"core2"}, CK_Core2, ~0U, FeaturesCore2 },
318  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
319  // Atom processors
320  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
321  { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
322  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
323  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
324  { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
325  { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
326  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
327  // Nehalem microarchitecture based processors.
328  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
329  { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
330  // Westmere microarchitecture based processors.
331  { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
332  // Sandy Bridge microarchitecture based processors.
333  { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
334  { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
335  // Ivy Bridge microarchitecture based processors.
336  { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
337  { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
338  // Haswell microarchitecture based processors.
339  { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
340  { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
341  // Broadwell microarchitecture based processors.
342  { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
343  // Skylake client microarchitecture based processors.
344  { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
345  // Skylake server microarchitecture based processors.
346  { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
347  { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
348  // Cascadelake Server microarchitecture based processors.
349  { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
350  // Cooperlake Server microarchitecture based processors.
351  { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
352  // Cannonlake client microarchitecture based processors.
353  { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
354  // Icelake client microarchitecture based processors.
355  { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
356  // Icelake server microarchitecture based processors.
357  { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
358  // Tigerlake microarchitecture based processors.
359  { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
360  // Sapphire Rapids microarchitecture based processors.
361  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
362  // Alderlake microarchitecture based processors.
363  { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
364  // Knights Landing processor.
365  { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
366  // Knights Mill processor.
367  { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
368  // Lakemont microarchitecture based processors.
369  { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
370  // K6 architecture processors.
371  { {"k6"}, CK_K6, ~0U, FeaturesK6 },
372  { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
373  { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
374  // K7 architecture processors.
375  { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
376  { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
377  { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
378  { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
379  { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
380  // K8 architecture processors.
381  { {"k8"}, CK_K8, ~0U, FeaturesK8 },
382  { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
383  { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
384  { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
385  { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
386  { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
387  { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
388  { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
389  { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
390  // Bobcat architecture processors.
391  { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
392  { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
393  // Bulldozer architecture processors.
394  { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
395  { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
396  { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
397  { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
398  // Zen architecture processors.
399  { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
400  { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
401  { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
402  // Generic 64-bit processor.
403  { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
404  { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
405  { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
406  { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
407  // Geode processors.
408  { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
409 };
410 
411 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
412 
414  for (const auto &P : Processors)
415  if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
416  return P.Kind;
417 
418  return CK_None;
419 }
420 
422  if (llvm::is_contained(NoTuneList, CPU))
423  return CK_None;
424  return parseArchX86(CPU, Only64Bit);
425 }
426 
428  bool Only64Bit) {
429  for (const auto &P : Processors)
430  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
431  Values.emplace_back(P.Name);
432 }
433 
435  bool Only64Bit) {
436  for (const ProcInfo &P : Processors)
437  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
439  Values.emplace_back(P.Name);
440 }
441 
443  // FIXME: Can we avoid a linear search here? The table might be sorted by
444  // CPUKind so we could binary search?
445  for (const auto &P : Processors) {
446  if (P.Kind == Kind) {
447  assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
448  return static_cast<ProcessorFeatures>(P.KeyFeature);
449  }
450  }
451 
452  llvm_unreachable("Unable to find CPU kind!");
453 }
454 
455 // Features with no dependencies.
499 
500 // Not really CPU features, but need to be in the table because clang uses
501 // target features to communicate them to the backend.
507 
508 // XSAVE features are dependent on basic XSAVE.
509 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
510 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
511 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
512 
513 // MMX->3DNOW->3DNOWA chain.
515 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
516 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
517 
518 // SSE/AVX/AVX512F chain.
520 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
521 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
522 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
523 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
524 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
525 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
526 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
528  FeatureAVX2 | FeatureF16C | FeatureFMA;
529 
530 // Vector extensions that build on SSE or AVX.
531 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
532 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
533 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
534 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
535 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
536 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
537 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
538 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
539 
540 // AVX512 features.
541 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
542 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
543 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
544 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
545 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
546 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
547 
548 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
549 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
550 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
551 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
553 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
554 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
556 
557 // FIXME: These two aren't really implemented and just exist in the feature
558 // list for __builtin_cpu_supports. So omit their dependencies.
561 
562 // SSE4_A->FMA4->XOP chain.
563 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
564 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
565 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
566 
567 // AMX Features
569 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
570 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
572 
573 // Key Locker Features
574 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
575 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
576 
577 // AVXVNNI Features
578 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
579 
580 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
581 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
582 #include "llvm/Support/X86TargetParser.def"
583 };
584 
586  SmallVectorImpl<StringRef> &EnabledFeatures) {
587  auto I = llvm::find_if(Processors,
588  [&](const ProcInfo &P) { return P.Name == CPU; });
589  assert(I != std::end(Processors) && "Processor not found!");
590 
591  FeatureBitset Bits = I->Features;
592 
593  // Remove the 64-bit feature which we only use to validate if a CPU can
594  // be used with 64-bit mode.
595  Bits &= ~Feature64BIT;
596 
597  // Add the string version of all set bits.
598  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
599  if (Bits[i] && !FeatureInfos[i].Name.empty())
600  EnabledFeatures.push_back(FeatureInfos[i].Name);
601 }
602 
603 // For each feature that is (transitively) implied by this feature, set it.
605  const FeatureBitset &Implies) {
606  // Fast path: Implies is often empty.
607  if (!Implies.any())
608  return;
609  FeatureBitset Prev;
610  Bits |= Implies;
611  do {
612  Prev = Bits;
613  for (unsigned i = CPU_FEATURE_MAX; i;)
614  if (Bits[--i])
615  Bits |= FeatureInfos[i].ImpliedFeatures;
616  } while (Prev != Bits);
617 }
618 
619 /// Create bit vector of features that are implied disabled if the feature
620 /// passed in Value is disabled.
622  // Check all features looking for any dependent on this feature. If we find
623  // one, mark it and recursively find any feature that depend on it.
624  FeatureBitset Prev;
625  Bits.set(Value);
626  do {
627  Prev = Bits;
628  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
629  if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
630  Bits.set(i);
631  } while (Prev != Bits);
632 }
633 
635  StringRef Feature, bool Enabled,
636  StringMap<bool> &Features) {
637  auto I = llvm::find_if(
638  FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
639  if (I == std::end(FeatureInfos)) {
640  // FIXME: This shouldn't happen, but may not have all features in the table
641  // yet.
642  return;
643  }
644 
645  FeatureBitset ImpliedBits;
646  if (Enabled)
647  getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
648  else
649  getImpliedDisabledFeatures(ImpliedBits,
650  std::distance(std::begin(FeatureInfos), I));
651 
652  // Update the map entry for all implied features.
653  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
654  if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
655  Features[FeatureInfos[i].Name] = Enabled;
656 }
i
i
Definition: README.txt:29
llvm::EngineKind::Kind
Kind
Definition: ExecutionEngine.h:524
FeaturesBonnell
constexpr FeatureBitset FeaturesBonnell
Definition: X86TargetParser.cpp:214
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
FeaturesZNVER3
static constexpr FeatureBitset FeaturesZNVER3
Definition: X86TargetParser.cpp:284
llvm::X86::CK_Prescott
@ CK_Prescott
Definition: X86TargetParser.h:80
ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesUINTR
Definition: X86TargetParser.cpp:493
ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesCLZERO
Definition: X86TargetParser.cpp:463
ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
Definition: X86TargetParser.cpp:475
FeaturesIvyBridge
constexpr FeatureBitset FeaturesIvyBridge
Definition: X86TargetParser.cpp:158
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::X86::CPUKind
CPUKind
Definition: X86TargetParser.h:62
ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
Definition: X86TargetParser.cpp:495
ImpliedFeaturesMOVBE
constexpr FeatureBitset ImpliedFeaturesMOVBE
Definition: X86TargetParser.cpp:474
FeaturesPentium3
constexpr FeatureBitset FeaturesPentium3
Definition: X86TargetParser.cpp:129
llvm::X86::CK_IcelakeClient
@ CK_IcelakeClient
Definition: X86TargetParser.h:100
FeaturesPentium2
constexpr FeatureBitset FeaturesPentium2
Definition: X86TargetParser.cpp:127
ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesSHA
Definition: X86TargetParser.cpp:536
ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesAVX512CD
Definition: X86TargetParser.cpp:541
FeaturesICLServer
constexpr FeatureBitset FeaturesICLServer
Definition: X86TargetParser.cpp:197
llvm::X86::CK_Athlon
@ CK_Athlon
Definition: X86TargetParser.h:111
ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
Definition: X86TargetParser.cpp:492
llvm::X86::CK_C3_2
@ CK_C3_2
Definition: X86TargetParser.h:77
ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesLZCNT
Definition: X86TargetParser.cpp:472
FeaturesBroadwell
constexpr FeatureBitset FeaturesBroadwell
Definition: X86TargetParser.cpp:163
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
Definition: X86TargetParser.cpp:578
FeaturesPenryn
constexpr FeatureBitset FeaturesPenryn
Definition: X86TargetParser.cpp:152
FeaturesAthlon
constexpr FeatureBitset FeaturesAthlon
Definition: X86TargetParser.cpp:235
ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeaturesGFNI
Definition: X86TargetParser.cpp:534
getImpliedDisabledFeatures
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
Definition: X86TargetParser.cpp:621
getImpliedEnabledFeatures
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
Definition: X86TargetParser.cpp:604
llvm::X86::CK_BDVER2
@ CK_BDVER2
Definition: X86TargetParser.h:119
llvm::X86::CK_x86_64_v2
@ CK_x86_64_v2
Definition: X86TargetParser.h:126
ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
Definition: X86TargetParser.cpp:465
ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesMWAITX
Definition: X86TargetParser.cpp:473
FeaturesBDVER3
constexpr FeatureBitset FeaturesBDVER3
Definition: X86TargetParser.cpp:265
ImpliedFeaturesAES
constexpr FeatureBitset ImpliedFeaturesAES
Definition: X86TargetParser.cpp:531
llvm::X86::CK_SkylakeClient
@ CK_SkylakeClient
Definition: X86TargetParser.h:95
llvm::X86::CK_i686
@ CK_i686
Definition: X86TargetParser.h:73
FeaturesNehalem
constexpr FeatureBitset FeaturesNehalem
Definition: X86TargetParser.cpp:153
llvm::X86::CK_PentiumPro
@ CK_PentiumPro
Definition: X86TargetParser.h:72
ImpliedFeatures64BIT
constexpr FeatureBitset ImpliedFeatures64BIT
Definition: X86TargetParser.cpp:456
llvm::X86::CK_SkylakeServer
@ CK_SkylakeServer
Definition: X86TargetParser.h:96
llvm::X86
Define some predicates that are used for node matching.
Definition: X86TargetParser.h:22
ImpliedFeaturesRDRND
constexpr FeatureBitset ImpliedFeaturesRDRND
Definition: X86TargetParser.cpp:484
llvm::X86::CK_K6
@ CK_K6
Definition: X86TargetParser.h:108
FeaturesCore2
constexpr FeatureBitset FeaturesCore2
Definition: X86TargetParser.cpp:150
llvm::X86::CK_KNL
@ CK_KNL
Definition: X86TargetParser.h:105
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesBMI
Definition: X86TargetParser.cpp:458
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
llvm::X86::getKeyFeature
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
Definition: X86TargetParser.cpp:442
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:2037
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
FeaturesK8
constexpr FeatureBitset FeaturesK8
Definition: X86TargetParser.cpp:239
ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
Definition: X86TargetParser.cpp:510
llvm::X86::CK_SandyBridge
@ CK_SandyBridge
Definition: X86TargetParser.h:91
ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesXSAVES
Definition: X86TargetParser.cpp:511
ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
Definition: X86TargetParser.cpp:476
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
FeaturesNocona
constexpr FeatureBitset FeaturesNocona
Definition: X86TargetParser.cpp:134
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:209
ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
Definition: X86TargetParser.cpp:552
llvm::X86::CK_Nocona
@ CK_Nocona
Definition: X86TargetParser.h:81
llvm::X86::CK_Bonnell
@ CK_Bonnell
Definition: X86TargetParser.h:84
llvm::X86::CK_Lakemont
@ CK_Lakemont
Definition: X86TargetParser.h:107
FeaturesK6
constexpr FeatureBitset FeaturesK6
Definition: X86TargetParser.cpp:232
ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
Definition: X86TargetParser.cpp:496
ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesAVX512BW
Definition: X86TargetParser.cpp:542
llvm::X86::CK_PentiumMMX
@ CK_PentiumMMX
Definition: X86TargetParser.h:71
llvm::X86::CK_GoldmontPlus
@ CK_GoldmontPlus
Definition: X86TargetParser.h:87
llvm::operator&=
bool operator&=(SparseBitVector< ElementSize > *LHS, const SparseBitVector< ElementSize > &RHS)
Definition: SparseBitVector.h:834
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:872
llvm::X86::parseArchX86
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
Definition: X86TargetParser.cpp:413
llvm::X86::CK_KNM
@ CK_KNM
Definition: X86TargetParser.h:106
llvm::X86::CK_x86_64
@ CK_x86_64
Definition: X86TargetParser.h:125
llvm::X86::CK_None
@ CK_None
Definition: X86TargetParser.h:63
ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesXOP
Definition: X86TargetParser.cpp:565
ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesF16C
Definition: X86TargetParser.cpp:532
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:59
llvm::X86::CK_ZNVER1
@ CK_ZNVER1
Definition: X86TargetParser.h:122
ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
Definition: X86TargetParser.cpp:548
FeaturesZNVER1
constexpr FeatureBitset FeaturesZNVER1
Definition: X86TargetParser.cpp:272
llvm::X86::CK_WinChip2
@ CK_WinChip2
Definition: X86TargetParser.h:67
llvm::X86::CK_C3
@ CK_C3
Definition: X86TargetParser.h:68
llvm::X86::fillValidCPUArchList
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
Definition: X86TargetParser.cpp:427
FeaturesPentiumMMX
constexpr FeatureBitset FeaturesPentiumMMX
Definition: X86TargetParser.cpp:123
ImpliedFeaturesSSE2
constexpr FeatureBitset ImpliedFeaturesSSE2
Definition: X86TargetParser.cpp:520
FeaturesICLClient
constexpr FeatureBitset FeaturesICLClient
Definition: X86TargetParser.cpp:193
FeaturesX86_64_V3
constexpr FeatureBitset FeaturesX86_64_V3
Definition: X86TargetParser.cpp:142
ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesINVPCID
Definition: X86TargetParser.cpp:470
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeatures3DNOW
Definition: X86TargetParser.cpp:515
ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesAVX512ER
Definition: X86TargetParser.cpp:544
ImpliedFeaturesXSAVEC
constexpr FeatureBitset ImpliedFeaturesXSAVEC
Definition: X86TargetParser.cpp:509
ImpliedFeaturesFSGSBASE
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
Definition: X86TargetParser.cpp:468
ImpliedFeaturesXSAVE
constexpr FeatureBitset ImpliedFeaturesXSAVE
Definition: X86TargetParser.cpp:498
FeaturesAthlonXP
constexpr FeatureBitset FeaturesAthlonXP
Definition: X86TargetParser.cpp:237
ImpliedFeaturesMMX
constexpr FeatureBitset ImpliedFeaturesMMX
Definition: X86TargetParser.cpp:514
ImpliedFeaturesVAES
constexpr FeatureBitset ImpliedFeaturesVAES
Definition: X86TargetParser.cpp:537
ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA4
Definition: X86TargetParser.cpp:564
ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesLWP
Definition: X86TargetParser.cpp:471
ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
Definition: X86TargetParser.cpp:551
FeaturesPentium4
constexpr FeatureBitset FeaturesPentium4
Definition: X86TargetParser.cpp:132
FeaturesGeode
constexpr FeatureBitset FeaturesGeode
Definition: X86TargetParser.cpp:228
FeaturesTigerlake
constexpr FeatureBitset FeaturesTigerlake
Definition: X86TargetParser.cpp:199
llvm::X86::CK_K8SSE3
@ CK_K8SSE3
Definition: X86TargetParser.h:114
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1341
ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesENQCMD
Definition: X86TargetParser.cpp:467
ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesPKU
Definition: X86TargetParser.cpp:479
llvm::X86::CK_PentiumM
@ CK_PentiumM
Definition: X86TargetParser.h:76
FeaturesHaswell
constexpr FeatureBitset FeaturesHaswell
Definition: X86TargetParser.cpp:160
FeaturesCooperLake
constexpr FeatureBitset FeaturesCooperLake
Definition: X86TargetParser.cpp:185
ImpliedFeaturesPTWRITE
constexpr FeatureBitset ImpliedFeaturesPTWRITE
Definition: X86TargetParser.cpp:482
llvm::StringMap< bool >
FeaturesCannonlake
constexpr FeatureBitset FeaturesCannonlake
Definition: X86TargetParser.cpp:189
ImpliedFeaturesAMX_TILE
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
Definition: X86TargetParser.cpp:568
llvm::X86::CK_Nehalem
@ CK_Nehalem
Definition: X86TargetParser.h:89
FeaturesK8SSE3
constexpr FeatureBitset FeaturesK8SSE3
Definition: X86TargetParser.cpp:241
ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesSSE4_2
Definition: X86TargetParser.cpp:524
ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSGX
Definition: X86TargetParser.cpp:489
ImpliedFeaturesSSE
constexpr FeatureBitset ImpliedFeaturesSSE
Definition: X86TargetParser.cpp:519
llvm::X86::CK_Cannonlake
@ CK_Cannonlake
Definition: X86TargetParser.h:99
ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesAVX512F
Definition: X86TargetParser.cpp:527
ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesPCONFIG
Definition: X86TargetParser.cpp:477
FeaturesAlderlake
constexpr FeatureBitset FeaturesAlderlake
Definition: X86TargetParser.cpp:208
ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesWAITPKG
Definition: X86TargetParser.cpp:494
X86TargetParser.h
llvm::X86::CK_Haswell
@ CK_Haswell
Definition: X86TargetParser.h:93
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:114
FeaturesX86_64_V2
constexpr FeatureBitset FeaturesX86_64_V2
Definition: X86TargetParser.cpp:139
ImpliedFeaturesFMA
constexpr FeatureBitset ImpliedFeaturesFMA
Definition: X86TargetParser.cpp:533
llvm::operator|
APInt operator|(APInt a, const APInt &b)
Definition: APInt.h:2067
llvm::X86::CK_ZNVER3
@ CK_ZNVER3
Definition: X86TargetParser.h:124
ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesTBM
Definition: X86TargetParser.cpp:491
ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
Definition: X86TargetParser.cpp:480
ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
Definition: X86TargetParser.cpp:503
FeaturesBTVER2
constexpr FeatureBitset FeaturesBTVER2
Definition: X86TargetParser.cpp:252
ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesAVX512PF
Definition: X86TargetParser.cpp:545
llvm::X86::CK_BDVER3
@ CK_BDVER3
Definition: X86TargetParser.h:120
ImpliedFeaturesADX
constexpr FeatureBitset ImpliedFeaturesADX
Definition: X86TargetParser.cpp:457
llvm::X86::CK_Pentium
@ CK_Pentium
Definition: X86TargetParser.h:70
llvm::X86::updateImpliedFeatures
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
Definition: X86TargetParser.cpp:634
FeaturesSapphireRapids
constexpr FeatureBitset FeaturesSapphireRapids
Definition: X86TargetParser.cpp:202
llvm::X86::CK_BDVER4
@ CK_BDVER4
Definition: X86TargetParser.h:121
llvm::X86::CK_AMDFAM10
@ CK_AMDFAM10
Definition: X86TargetParser.h:115
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1563
ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesCLWB
Definition: X86TargetParser.cpp:462
ImpliedFeaturesAVX512VL
constexpr FeatureBitset ImpliedFeaturesAVX512VL
Definition: X86TargetParser.cpp:546
ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
Definition: X86TargetParser.cpp:505
FeaturesBDVER4
constexpr FeatureBitset FeaturesBDVER4
Definition: X86TargetParser.cpp:267
ImpliedFeaturesAVX2
constexpr FeatureBitset ImpliedFeaturesAVX2
Definition: X86TargetParser.cpp:526
llvm::X86::getFeaturesForCPU
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features)
Fill in the features that CPU supports into Features.
Definition: X86TargetParser.cpp:585
ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
Definition: X86TargetParser.cpp:555
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FeaturesGoldmont
constexpr FeatureBitset FeaturesGoldmont
Definition: X86TargetParser.cpp:218
ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesSHSTK
Definition: X86TargetParser.cpp:490
ImpliedFeaturesFXSR
constexpr FeatureBitset ImpliedFeaturesFXSR
Definition: X86TargetParser.cpp:469
llvm::X86::CK_Westmere
@ CK_Westmere
Definition: X86TargetParser.h:90
llvm::X86::CK_Broadwell
@ CK_Broadwell
Definition: X86TargetParser.h:94
llvm::X86::CK_K8
@ CK_K8
Definition: X86TargetParser.h:113
llvm::X86::CK_WinChipC6
@ CK_WinChipC6
Definition: X86TargetParser.h:66
llvm::X86::CK_BDVER1
@ CK_BDVER1
Definition: X86TargetParser.h:118
Triple.h
ImpliedFeaturesRTM
constexpr FeatureBitset ImpliedFeaturesRTM
Definition: X86TargetParser.cpp:486
llvm::X86::CK_x86_64_v3
@ CK_x86_64_v3
Definition: X86TargetParser.h:127
llvm::X86::CK_SapphireRapids
@ CK_SapphireRapids
Definition: X86TargetParser.h:103
ImpliedFeaturesSSE4_1
constexpr FeatureBitset ImpliedFeaturesSSE4_1
Definition: X86TargetParser.cpp:523
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1505
llvm::X86::CK_K6_3
@ CK_K6_3
Definition: X86TargetParser.h:110
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::X86::CK_Silvermont
@ CK_Silvermont
Definition: X86TargetParser.h:85
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::operator|=
bool operator|=(SparseBitVector< ElementSize > &LHS, const SparseBitVector< ElementSize > *RHS)
Definition: SparseBitVector.h:822
ImpliedFeaturesAMX_BF16
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
Definition: X86TargetParser.cpp:569
uint32_t
llvm::X86::CK_Pentium2
@ CK_Pentium2
Definition: X86TargetParser.h:74
FeaturesSilvermont
constexpr FeatureBitset FeaturesSilvermont
Definition: X86TargetParser.cpp:216
FeaturesKNM
constexpr FeatureBitset FeaturesKNM
Definition: X86TargetParser.cpp:171
FeaturesBDVER2
constexpr FeatureBitset FeaturesBDVER2
Definition: X86TargetParser.cpp:263
FeaturesX86_64_V4
constexpr FeatureBitset FeaturesX86_64_V4
Definition: X86TargetParser.cpp:145
ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
Definition: X86TargetParser.cpp:538
ImpliedFeaturesSSE4_A
constexpr FeatureBitset ImpliedFeaturesSSE4_A
Definition: X86TargetParser.cpp:563
llvm::X86::CK_IcelakeServer
@ CK_IcelakeServer
Definition: X86TargetParser.h:101
llvm::X86::ProcessorFeatures
ProcessorFeatures
Definition: X86TargetParser.h:56
llvm::X86::CK_Tigerlake
@ CK_Tigerlake
Definition: X86TargetParser.h:102
llvm::Init
Definition: Record.h:271
ImpliedFeaturesRDSEED
constexpr FeatureBitset ImpliedFeaturesRDSEED
Definition: X86TargetParser.cpp:485
llvm::X86::CK_x86_64_v4
@ CK_x86_64_v4
Definition: X86TargetParser.h:128
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1525
ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
Definition: X86TargetParser.cpp:502
FeaturesGoldmontPlus
constexpr FeatureBitset FeaturesGoldmontPlus
Definition: X86TargetParser.cpp:222
llvm::operator~
APInt operator~(APInt v)
Unary bitwise complement operator.
Definition: APInt.h:2042
ImpliedFeaturesBMI2
constexpr FeatureBitset ImpliedFeaturesBMI2
Definition: X86TargetParser.cpp:459
llvm::operator&
APInt operator&(APInt a, const APInt &b)
Definition: APInt.h:2047
llvm::X86::CK_BTVER1
@ CK_BTVER1
Definition: X86TargetParser.h:116
ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
Definition: X86TargetParser.cpp:488
ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
Definition: X86TargetParser.cpp:506
llvm::X86::CK_i486
@ CK_i486
Definition: X86TargetParser.h:65
ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
Definition: X86TargetParser.cpp:550
FeaturesPrescott
constexpr FeatureBitset FeaturesPrescott
Definition: X86TargetParser.cpp:133
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
ImpliedFeaturesPRFCHW
constexpr FeatureBitset ImpliedFeaturesPRFCHW
Definition: X86TargetParser.cpp:481
FeaturesKNL
constexpr FeatureBitset FeaturesKNL
Definition: X86TargetParser.cpp:168
llvm::X86::CK_K6_2
@ CK_K6_2
Definition: X86TargetParser.h:109
Processors
constexpr ProcInfo Processors[]
Definition: X86TargetParser.cpp:288
ImpliedFeaturesAVX
constexpr FeatureBitset ImpliedFeaturesAVX
Definition: X86TargetParser.cpp:525
Enabled
static bool Enabled
Definition: Statistic.cpp:50
FeaturesZNVER2
constexpr FeatureBitset FeaturesZNVER2
Definition: X86TargetParser.cpp:282
FeaturesSkylakeClient
constexpr FeatureBitset FeaturesSkylakeClient
Definition: X86TargetParser.cpp:174
llvm::X86::CK_Goldmont
@ CK_Goldmont
Definition: X86TargetParser.h:86
llvm::X86::CK_BTVER2
@ CK_BTVER2
Definition: X86TargetParser.h:117
FeaturesWestmere
constexpr FeatureBitset FeaturesWestmere
Definition: X86TargetParser.cpp:155
llvm::X86::CK_ZNVER2
@ CK_ZNVER2
Definition: X86TargetParser.h:123
ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
Definition: X86TargetParser.cpp:461
FeatureInfos
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
Definition: X86TargetParser.cpp:580
FeaturesCascadeLake
constexpr FeatureBitset FeaturesCascadeLake
Definition: X86TargetParser.cpp:183
ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
Definition: X86TargetParser.cpp:559
ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesSSE3
Definition: X86TargetParser.cpp:521
FeaturesSkylakeServer
constexpr FeatureBitset FeaturesSkylakeServer
Definition: X86TargetParser.cpp:179
llvm::X86::CK_i586
@ CK_i586
Definition: X86TargetParser.h:69
llvm::X86::CK_Pentium4
@ CK_Pentium4
Definition: X86TargetParser.h:79
llvm::X86::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
Definition: X86TargetParser.cpp:434
ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesPOPCNT
Definition: X86TargetParser.cpp:478
llvm::X86::CK_Core2
@ CK_Core2
Definition: X86TargetParser.h:82
ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesKL
Definition: X86TargetParser.cpp:574
llvm::X86::parseTuneCPU
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
Definition: X86TargetParser.cpp:421
ImpliedFeaturesHRESET
constexpr FeatureBitset ImpliedFeaturesHRESET
Definition: X86TargetParser.cpp:571
FeaturesX86_64
constexpr FeatureBitset FeaturesX86_64
Definition: X86TargetParser.cpp:138
ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
Definition: X86TargetParser.cpp:460
ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesX87
Definition: X86TargetParser.cpp:497
llvm::X86::CK_IvyBridge
@ CK_IvyBridge
Definition: X86TargetParser.h:92
ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesSAHF
Definition: X86TargetParser.cpp:487
NoTuneList
constexpr const char * NoTuneList[]
Definition: X86TargetParser.cpp:411
ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
Definition: X86TargetParser.cpp:504
FeaturesAMDFAM10
constexpr FeatureBitset FeaturesAMDFAM10
Definition: X86TargetParser.cpp:242
ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
Definition: X86TargetParser.cpp:553
ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesSSSE3
Definition: X86TargetParser.cpp:522
FeaturesTremont
constexpr FeatureBitset FeaturesTremont
Definition: X86TargetParser.cpp:224
ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
Definition: X86TargetParser.cpp:560
llvm::X86::CK_Tremont
@ CK_Tremont
Definition: X86TargetParser.h:88
llvm::X86::CK_Alderlake
@ CK_Alderlake
Definition: X86TargetParser.h:104
ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
Definition: X86TargetParser.cpp:570
llvm::SmallVectorImpl< StringRef >
llvm::X86::CK_Cascadelake
@ CK_Cascadelake
Definition: X86TargetParser.h:97
FeaturesSandyBridge
constexpr FeatureBitset FeaturesSandyBridge
Definition: X86TargetParser.cpp:156
llvm::X86::CK_Penryn
@ CK_Penryn
Definition: X86TargetParser.h:83
ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
Definition: X86TargetParser.cpp:554
ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
Definition: X86TargetParser.cpp:543
llvm::X86::CK_Cooperlake
@ CK_Cooperlake
Definition: X86TargetParser.h:98
llvm::X86::CK_AthlonXP
@ CK_AthlonXP
Definition: X86TargetParser.h:112
llvm::X86::CK_i386
@ CK_i386
Definition: X86TargetParser.h:64
ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
Definition: X86TargetParser.cpp:466
llvm::FeatureBitset::any
bool any() const
Definition: SubtargetFeature.h:94
llvm::X86::CK_Pentium3
@ CK_Pentium3
Definition: X86TargetParser.h:75
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
FeaturesBDVER1
constexpr FeatureBitset FeaturesBDVER1
Definition: X86TargetParser.cpp:257
ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesWIDEKL
Definition: X86TargetParser.cpp:575
ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesRDPID
Definition: X86TargetParser.cpp:483
FeaturesBTVER1
constexpr FeatureBitset FeaturesBTVER1
Definition: X86TargetParser.cpp:247
ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
Definition: X86TargetParser.cpp:549
ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesPCLMUL
Definition: X86TargetParser.cpp:535
ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesCMOV
Definition: X86TargetParser.cpp:464
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:908
llvm::X86::CK_Yonah
@ CK_Yonah
Definition: X86TargetParser.h:78
ImpliedFeatures3DNOWA
constexpr FeatureBitset ImpliedFeatures3DNOWA
Definition: X86TargetParser.cpp:516
llvm::X86::CK_Geode
@ CK_Geode
Definition: X86TargetParser.h:129