LLVM  17.0.0git
X86TargetParser.cpp
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1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise X86 hardware features.
10 //
11 //===----------------------------------------------------------------------===//
12 
14 #include "llvm/ADT/StringSwitch.h"
15 #include <numeric>
16 
17 using namespace llvm;
18 using namespace llvm::X86;
19 
20 namespace {
21 
22 /// Container class for CPU features.
23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be
24 /// nice to use std::bitset directly, but it doesn't support constant
25 /// initialization.
26 class FeatureBitset {
27  static constexpr unsigned NUM_FEATURE_WORDS =
28  (X86::CPU_FEATURE_MAX + 31) / 32;
29 
30  // This cannot be a std::array, operator[] is not constexpr until C++17.
31  uint32_t Bits[NUM_FEATURE_WORDS] = {};
32 
33 public:
34  constexpr FeatureBitset() = default;
35  constexpr FeatureBitset(std::initializer_list<unsigned> Init) {
36  for (auto I : Init)
37  set(I);
38  }
39 
40  bool any() const {
41  return llvm::any_of(Bits, [](uint64_t V) { return V != 0; });
42  }
43 
44  constexpr FeatureBitset &set(unsigned I) {
45  // GCC <6.2 crashes if this is written in a single statement.
46  uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32));
47  Bits[I / 32] = NewBits;
48  return *this;
49  }
50 
51  constexpr bool operator[](unsigned I) const {
52  uint32_t Mask = uint32_t(1) << (I % 32);
53  return (Bits[I / 32] & Mask) != 0;
54  }
55 
56  constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) {
57  for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
58  // GCC <6.2 crashes if this is written in a single statement.
59  uint32_t NewBits = Bits[I] & RHS.Bits[I];
60  Bits[I] = NewBits;
61  }
62  return *this;
63  }
64 
65  constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) {
66  for (unsigned I = 0, E = std::size(Bits); I != E; ++I) {
67  // GCC <6.2 crashes if this is written in a single statement.
68  uint32_t NewBits = Bits[I] | RHS.Bits[I];
69  Bits[I] = NewBits;
70  }
71  return *this;
72  }
73 
74  // gcc 5.3 miscompiles this if we try to write this using operator&=.
75  constexpr FeatureBitset operator&(const FeatureBitset &RHS) const {
77  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
78  Result.Bits[I] = Bits[I] & RHS.Bits[I];
79  return Result;
80  }
81 
82  // gcc 5.3 miscompiles this if we try to write this using operator&=.
83  constexpr FeatureBitset operator|(const FeatureBitset &RHS) const {
85  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
86  Result.Bits[I] = Bits[I] | RHS.Bits[I];
87  return Result;
88  }
89 
90  constexpr FeatureBitset operator~() const {
92  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
93  Result.Bits[I] = ~Bits[I];
94  return Result;
95  }
96 
97  constexpr bool operator!=(const FeatureBitset &RHS) const {
98  for (unsigned I = 0, E = std::size(Bits); I != E; ++I)
99  if (Bits[I] != RHS.Bits[I])
100  return true;
101  return false;
102  }
103 };
104 
105 struct ProcInfo {
108  unsigned KeyFeature;
109  FeatureBitset Features;
110 };
111 
112 struct FeatureInfo {
114  FeatureBitset ImpliedFeatures;
115 };
116 
117 } // end anonymous namespace
118 
119 #define X86_FEATURE(ENUM, STRING) \
120  constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM};
121 #include "llvm/TargetParser/X86TargetParser.def"
122 
123 // Pentium with MMX.
125  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
126 
127 // Pentium 2 and 3.
129  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR;
131 
132 // Pentium 4 CPUs
136  FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B;
137 
138 // Basic 64-bit capable CPU.
139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT;
140 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF |
141  FeaturePOPCNT | FeatureCRC32 |
142  FeatureSSE4_2 | FeatureCMPXCHG16B;
144  FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C |
145  FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE;
147  FeatureAVX512BW | FeatureAVX512CD |
148  FeatureAVX512DQ | FeatureAVX512VL;
149 
150 // Intel Core CPUs
152  FeaturesNocona | FeatureSAHF | FeatureSSSE3;
153 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1;
155  FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2;
156 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL;
158  FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT;
160  FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND;
162  FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA |
163  FeatureINVPCID | FeatureLZCNT | FeatureMOVBE;
165  FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED;
166 
167 // Intel Knights Landing and Knights Mill
168 // Knights Landing has feature parity with Broadwell.
170  FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD |
171  FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1;
172 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ;
173 
174 // Intel Skylake processors.
176  FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC |
177  FeatureXSAVES | FeatureSGX;
178 // SkylakeServer inherits all SkylakeClient features except SGX.
179 // FIXME: That doesn't match gcc.
181  (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD |
182  FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB |
183  FeaturePKU;
185  FeaturesSkylakeServer | FeatureAVX512VNNI;
187  FeaturesCascadeLake | FeatureAVX512BF16;
188 
189 // Intel 10nm processors.
191  FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
192  FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
193  FeaturePKU | FeatureSHA;
195  FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
196  FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID |
197  FeatureVAES | FeatureVPCLMULQDQ;
200  FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD;
202  FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
203  FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL;
205  FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE |
206  FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE |
207  FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE |
208  FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR |
209  FeatureWAITPKG;
211  FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
212 
213 // Intel Atom processors.
214 // Bonnell has feature parity with Core2 and adds MOVBE.
215 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
216 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
218  FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
220  FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE |
221  FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC |
222  FeatureXSAVEOPT | FeatureXSAVES;
224  FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX;
226  FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI;
228  FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C |
229  FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU |
230  FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ |
231  FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG |
232  FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL;
234  FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA |
235  FeatureAVXNECONVERT | FeatureAVXVNNIINT8;
237  FeaturesSierraforest | FeatureRAOINT;
238 
239 // Geode Processor.
241  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
242 
243 // K6 processor.
244 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX;
245 
246 // K7 and K8 architecture processors.
248  FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA;
250  FeaturesAthlon | FeatureFXSR | FeatureSSE;
252  FeaturesAthlonXP | FeatureSSE2 | Feature64BIT;
253 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3;
255  FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT |
256  FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A;
257 
258 // Bobcat architecture processors.
260  FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT |
261  FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW |
262  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A |
263  FeatureSAHF;
265  FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 |
266  FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT;
267 
268 // AMD Bulldozer architecture processors.
270  FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B |
271  FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 |
272  FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL |
273  FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 |
274  FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A |
275  FeatureXOP | FeatureXSAVE;
277  FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM;
279  FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT;
280 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 |
281  FeatureBMI2 | FeatureMOVBE |
282  FeatureMWAITX | FeatureRDRND;
283 
284 // AMD Zen architecture processors.
286  FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 |
287  FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO |
288  FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT |
289  FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT |
290  FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT |
291  FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA |
292  FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 |
293  FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC |
294  FeatureXSAVEOPT | FeatureXSAVES;
295 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB |
296  FeatureRDPID | FeatureRDPRU |
297  FeatureWBNOINVD;
299  FeatureINVPCID | FeaturePKU |
300  FeatureVAES | FeatureVPCLMULQDQ;
301 static constexpr FeatureBitset FeaturesZNVER4 =
302  FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ |
303  FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI |
304  FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG |
305  FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI |
306  FeatureSHSTK;
307 
308 constexpr ProcInfo Processors[] = {
309  // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility.
310  { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B },
311  // i386-generation processors.
312  { {"i386"}, CK_i386, ~0U, FeatureX87 },
313  // i486-generation processors.
314  { {"i486"}, CK_i486, ~0U, FeatureX87 },
315  { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX },
316  { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW },
317  { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW },
318  // i586-generation processors, P5 microarchitecture based.
319  { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B },
320  { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B },
321  { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX },
322  // i686-generation processors, P6 / Pentium M microarchitecture based.
323  { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B },
324  { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B },
325  { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 },
326  { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 },
327  { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 },
328  { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 },
329  { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 },
330  { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott },
331  // Netburst microarchitecture based processors.
332  { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 },
333  { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 },
334  { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott },
335  { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona },
336  // Core microarchitecture based processors.
337  { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2 },
338  { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn },
339  // Atom processors
340  { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
341  { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell },
342  { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
343  { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont },
344  { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont },
345  { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus },
346  { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont },
347  // Nehalem microarchitecture based processors.
348  { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
349  { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem },
350  // Westmere microarchitecture based processors.
351  { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere },
352  // Sandy Bridge microarchitecture based processors.
353  { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
354  { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge },
355  // Ivy Bridge microarchitecture based processors.
356  { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
357  { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge },
358  // Haswell microarchitecture based processors.
359  { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
360  { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell },
361  // Broadwell microarchitecture based processors.
362  { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell },
363  // Skylake client microarchitecture based processors.
364  { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient },
365  // Skylake server microarchitecture based processors.
366  { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
367  { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer },
368  // Cascadelake Server microarchitecture based processors.
369  { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake },
370  // Cooperlake Server microarchitecture based processors.
371  { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake },
372  // Cannonlake client microarchitecture based processors.
373  { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
374  // Icelake client microarchitecture based processors.
375  { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
376  // Rocketlake microarchitecture based processors.
377  { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake },
378  // Icelake server microarchitecture based processors.
379  { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
380  // Tigerlake microarchitecture based processors.
381  { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
382  // Sapphire Rapids microarchitecture based processors.
383  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
384  // Alderlake microarchitecture based processors.
385  { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake },
386  // Raptorlake microarchitecture based processors.
387  { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake },
388  // Meteorlake microarchitecture based processors.
389  { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake },
390  // Sierraforest microarchitecture based processors.
391  { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest },
392  // Grandridge microarchitecture based processors.
393  { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge },
394  // Granite Rapids microarchitecture based processors.
395  { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids },
396  // Emerald Rapids microarchitecture based processors.
397  { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids },
398  // Knights Landing processor.
399  { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
400  // Knights Mill processor.
401  { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
402  // Lakemont microarchitecture based processors.
403  { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
404  // K6 architecture processors.
405  { {"k6"}, CK_K6, ~0U, FeaturesK6 },
406  { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW },
407  { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW },
408  // K7 architecture processors.
409  { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon },
410  { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon },
411  { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
412  { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
413  { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP },
414  // K8 architecture processors.
415  { {"k8"}, CK_K8, ~0U, FeaturesK8 },
416  { {"athlon64"}, CK_K8, ~0U, FeaturesK8 },
417  { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 },
418  { {"opteron"}, CK_K8, ~0U, FeaturesK8 },
419  { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
420  { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
421  { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 },
422  { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
423  { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 },
424  // Bobcat architecture processors.
425  { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 },
426  { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 },
427  // Bulldozer architecture processors.
428  { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 },
429  { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 },
430  { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 },
431  { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 },
432  // Zen architecture processors.
433  { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 },
434  { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 },
435  { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 },
436  { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4 },
437  // Generic 64-bit processor.
438  { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 },
439  { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 },
440  { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 },
441  { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 },
442  // Geode processors.
443  { {"geode"}, CK_Geode, ~0U, FeaturesGeode },
444 };
445 
446 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"};
447 
449  for (const auto &P : Processors)
450  if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit))
451  return P.Kind;
452 
453  return CK_None;
454 }
455 
457  if (llvm::is_contained(NoTuneList, CPU))
458  return CK_None;
459  return parseArchX86(CPU, Only64Bit);
460 }
461 
463  bool Only64Bit) {
464  for (const auto &P : Processors)
465  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit))
466  Values.emplace_back(P.Name);
467 }
468 
470  bool Only64Bit) {
471  for (const ProcInfo &P : Processors)
472  if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) &&
474  Values.emplace_back(P.Name);
475 }
476 
478  // FIXME: Can we avoid a linear search here? The table might be sorted by
479  // CPUKind so we could binary search?
480  for (const auto &P : Processors) {
481  if (P.Kind == Kind) {
482  assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
483  return static_cast<ProcessorFeatures>(P.KeyFeature);
484  }
485  }
486 
487  llvm_unreachable("Unable to find CPU kind!");
488 }
489 
490 // Features with no dependencies.
536 
537 // Not really CPU features, but need to be in the table because clang uses
538 // target features to communicate them to the backend.
544 
545 // XSAVE features are dependent on basic XSAVE.
546 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE;
547 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE;
548 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE;
549 
550 // MMX->3DNOW->3DNOWA chain.
552 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX;
553 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW;
554 
555 // SSE/AVX/AVX512F chain.
557 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE;
558 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2;
559 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3;
560 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3;
561 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1;
562 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2;
563 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX;
565  FeatureAVX2 | FeatureF16C | FeatureFMA;
566 
567 // Vector extensions that build on SSE or AVX.
568 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2;
569 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
570 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
571 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
572 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
573 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
574 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
575 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
576 
577 // AVX512 features.
578 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
579 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
580 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
581 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
582 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
583 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;
584 
585 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW;
586 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW;
587 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F;
588 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F;
590 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW;
591 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW;
593 
594 // FIXME: These two aren't really implemented and just exist in the feature
595 // list for __builtin_cpu_supports. So omit their dependencies.
598 
599 // SSE4_A->FMA4->XOP chain.
600 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3;
601 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A;
602 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
603 
604 // AMX Features
606 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
607 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE;
608 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
610 
615 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2;
618  FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL;
619 // Key Locker Features
620 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;
621 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL;
622 
623 // AVXVNNI Features
624 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2;
625 
626 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = {
627 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM},
628 #include "llvm/TargetParser/X86TargetParser.def"
629 };
630 
632  SmallVectorImpl<StringRef> &EnabledFeatures) {
633  auto I = llvm::find_if(Processors,
634  [&](const ProcInfo &P) { return P.Name == CPU; });
635  assert(I != std::end(Processors) && "Processor not found!");
636 
637  FeatureBitset Bits = I->Features;
638 
639  // Remove the 64-bit feature which we only use to validate if a CPU can
640  // be used with 64-bit mode.
641  Bits &= ~Feature64BIT;
642 
643  // Add the string version of all set bits.
644  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
645  if (Bits[i] && !FeatureInfos[i].Name.empty())
646  EnabledFeatures.push_back(FeatureInfos[i].Name);
647 }
648 
649 // For each feature that is (transitively) implied by this feature, set it.
651  const FeatureBitset &Implies) {
652  // Fast path: Implies is often empty.
653  if (!Implies.any())
654  return;
655  FeatureBitset Prev;
656  Bits |= Implies;
657  do {
658  Prev = Bits;
659  for (unsigned i = CPU_FEATURE_MAX; i;)
660  if (Bits[--i])
661  Bits |= FeatureInfos[i].ImpliedFeatures;
662  } while (Prev != Bits);
663 }
664 
665 /// Create bit vector of features that are implied disabled if the feature
666 /// passed in Value is disabled.
668  // Check all features looking for any dependent on this feature. If we find
669  // one, mark it and recursively find any feature that depend on it.
670  FeatureBitset Prev;
671  Bits.set(Value);
672  do {
673  Prev = Bits;
674  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
675  if ((FeatureInfos[i].ImpliedFeatures & Bits).any())
676  Bits.set(i);
677  } while (Prev != Bits);
678 }
679 
681  StringRef Feature, bool Enabled,
682  StringMap<bool> &Features) {
683  auto I = llvm::find_if(
684  FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; });
685  if (I == std::end(FeatureInfos)) {
686  // FIXME: This shouldn't happen, but may not have all features in the table
687  // yet.
688  return;
689  }
690 
691  FeatureBitset ImpliedBits;
692  if (Enabled)
693  getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures);
694  else
695  getImpliedDisabledFeatures(ImpliedBits,
696  std::distance(std::begin(FeatureInfos), I));
697 
698  // Update the map entry for all implied features.
699  for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i)
700  if (ImpliedBits[i] && !FeatureInfos[i].Name.empty())
701  Features[FeatureInfos[i].Name] = Enabled;
702 }
703 
705  // Processor features and mapping to processor feature value.
706  uint64_t FeaturesMask = 0;
707  for (const StringRef &FeatureStr : FeatureStrs) {
708  unsigned Feature = StringSwitch<unsigned>(FeatureStr)
709 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
710  .Case(STR, llvm::X86::FEATURE_##ENUM)
711 #include "llvm/TargetParser/X86TargetParser.def"
712  ;
713  FeaturesMask |= (1ULL << Feature);
714  }
715  return FeaturesMask;
716 }
717 
719 #ifndef NDEBUG
720  // Check that priorities are set properly in the .def file. We expect that
721  // "compat" features are assigned non-duplicate consecutive priorities
722  // starting from zero (0, 1, ..., num_features - 1).
723 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY,
724  unsigned Priorities[] = {
725 #include "llvm/TargetParser/X86TargetParser.def"
726  std::numeric_limits<unsigned>::max() // Need to consume last comma.
727  };
728  std::array<unsigned, std::size(Priorities) - 1> HelperList;
729  std::iota(HelperList.begin(), HelperList.end(), 0);
730  assert(std::is_permutation(HelperList.begin(), HelperList.end(),
731  std::begin(Priorities),
732  std::prev(std::end(Priorities))) &&
733  "Priorities don't form consecutive range!");
734 #endif
735 
736  switch (Feat) {
737 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \
738  case X86::FEATURE_##ENUM: \
739  return PRIORITY;
740 #include "llvm/TargetParser/X86TargetParser.def"
741  default:
742  llvm_unreachable("No Feature Priority for non-CPUSupports Features");
743  }
744 }
i
i
Definition: README.txt:29
FeaturesBonnell
constexpr FeatureBitset FeaturesBonnell
Definition: X86TargetParser.cpp:215
set
We currently generate a but we really shouldn eax ecx xorl edx divl ecx eax divl ecx movl eax ret A similar code sequence works for division We currently compile i32 v2 eax eax jo LBB1_2 atomic and others It is also currently not done for read modify write instructions It is also current not done if the OF or CF flags are needed The shift operators have the complication that when the shift count is EFLAGS is not set
Definition: README.txt:1277
FeaturesZNVER3
static constexpr FeatureBitset FeaturesZNVER3
Definition: X86TargetParser.cpp:298
llvm::X86::CK_Prescott
@ CK_Prescott
Definition: X86TargetParser.h:81
ImpliedFeaturesUINTR
constexpr FeatureBitset ImpliedFeaturesUINTR
Definition: X86TargetParser.cpp:530
ImpliedFeaturesCLZERO
constexpr FeatureBitset ImpliedFeaturesCLZERO
Definition: X86TargetParser.cpp:498
ImpliedFeaturesMOVDIR64B
constexpr FeatureBitset ImpliedFeaturesMOVDIR64B
Definition: X86TargetParser.cpp:511
FeaturesIvyBridge
constexpr FeatureBitset FeaturesIvyBridge
Definition: X86TargetParser.cpp:159
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::X86::CPUKind
CPUKind
Definition: X86TargetParser.h:63
ImpliedFeaturesWBNOINVD
constexpr FeatureBitset ImpliedFeaturesWBNOINVD
Definition: X86TargetParser.cpp:532
ImpliedFeaturesAVXNECONVERT
constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT
Definition: X86TargetParser.cpp:616
FeaturesGraniteRapids
constexpr FeatureBitset FeaturesGraniteRapids
Definition: X86TargetParser.cpp:210
ImpliedFeaturesMOVBE
constexpr FeatureBitset ImpliedFeaturesMOVBE
Definition: X86TargetParser.cpp:510
FeaturesPentium3
constexpr FeatureBitset FeaturesPentium3
Definition: X86TargetParser.cpp:130
llvm::X86::CK_IcelakeClient
@ CK_IcelakeClient
Definition: X86TargetParser.h:101
FeaturesPentium2
constexpr FeatureBitset FeaturesPentium2
Definition: X86TargetParser.cpp:128
ImpliedFeaturesSHA
constexpr FeatureBitset ImpliedFeaturesSHA
Definition: X86TargetParser.cpp:573
ImpliedFeaturesAVX512CD
constexpr FeatureBitset ImpliedFeaturesAVX512CD
Definition: X86TargetParser.cpp:578
FeaturesICLServer
constexpr FeatureBitset FeaturesICLServer
Definition: X86TargetParser.cpp:199
llvm::X86::CK_Athlon
@ CK_Athlon
Definition: X86TargetParser.h:119
ImpliedFeaturesTSXLDTRK
constexpr FeatureBitset ImpliedFeaturesTSXLDTRK
Definition: X86TargetParser.cpp:529
llvm::X86::CK_C3_2
@ CK_C3_2
Definition: X86TargetParser.h:78
ImpliedFeaturesLZCNT
constexpr FeatureBitset ImpliedFeaturesLZCNT
Definition: X86TargetParser.cpp:508
FeaturesBroadwell
constexpr FeatureBitset FeaturesBroadwell
Definition: X86TargetParser.cpp:164
ImpliedFeaturesAVX512FP16
constexpr FeatureBitset ImpliedFeaturesAVX512FP16
Definition: X86TargetParser.cpp:617
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
ImpliedFeaturesAVXVNNI
constexpr FeatureBitset ImpliedFeaturesAVXVNNI
Definition: X86TargetParser.cpp:624
FeaturesPenryn
constexpr FeatureBitset FeaturesPenryn
Definition: X86TargetParser.cpp:153
llvm::X86::CK_Raptorlake
@ CK_Raptorlake
Definition: X86TargetParser.h:107
FeaturesAthlon
constexpr FeatureBitset FeaturesAthlon
Definition: X86TargetParser.cpp:247
ImpliedFeaturesGFNI
constexpr FeatureBitset ImpliedFeaturesGFNI
Definition: X86TargetParser.cpp:571
getImpliedDisabledFeatures
static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value)
Create bit vector of features that are implied disabled if the feature passed in Value is disabled.
Definition: X86TargetParser.cpp:667
getImpliedEnabledFeatures
static void getImpliedEnabledFeatures(FeatureBitset &Bits, const FeatureBitset &Implies)
Definition: X86TargetParser.cpp:650
llvm::X86::CK_BDVER2
@ CK_BDVER2
Definition: X86TargetParser.h:127
llvm::X86::CK_x86_64_v2
@ CK_x86_64_v2
Definition: X86TargetParser.h:135
ImpliedFeaturesCMPXCHG16B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B
Definition: X86TargetParser.cpp:500
ImpliedFeaturesMWAITX
constexpr FeatureBitset ImpliedFeaturesMWAITX
Definition: X86TargetParser.cpp:509
FeaturesBDVER3
constexpr FeatureBitset FeaturesBDVER3
Definition: X86TargetParser.cpp:278
ImpliedFeaturesAES
constexpr FeatureBitset ImpliedFeaturesAES
Definition: X86TargetParser.cpp:568
llvm::X86::CK_SkylakeClient
@ CK_SkylakeClient
Definition: X86TargetParser.h:96
llvm::X86::CK_i686
@ CK_i686
Definition: X86TargetParser.h:74
FeaturesNehalem
constexpr FeatureBitset FeaturesNehalem
Definition: X86TargetParser.cpp:154
llvm::X86::CK_PentiumPro
@ CK_PentiumPro
Definition: X86TargetParser.h:73
ImpliedFeatures64BIT
constexpr FeatureBitset ImpliedFeatures64BIT
Definition: X86TargetParser.cpp:491
llvm::X86::CK_SkylakeServer
@ CK_SkylakeServer
Definition: X86TargetParser.h:97
llvm::X86
Define some predicates that are used for node matching.
Definition: X86TargetParser.h:23
ImpliedFeaturesRDRND
constexpr FeatureBitset ImpliedFeaturesRDRND
Definition: X86TargetParser.cpp:521
llvm::X86::CK_K6
@ CK_K6
Definition: X86TargetParser.h:116
FeaturesZNVER4
static constexpr FeatureBitset FeaturesZNVER4
Definition: X86TargetParser.cpp:301
FeaturesCore2
constexpr FeatureBitset FeaturesCore2
Definition: X86TargetParser.cpp:151
llvm::X86::CK_KNL
@ CK_KNL
Definition: X86TargetParser.h:113
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::X86::getCpuSupportsMask
uint64_t getCpuSupportsMask(ArrayRef< StringRef > FeatureStrs)
Definition: X86TargetParser.cpp:704
ImpliedFeaturesBMI
constexpr FeatureBitset ImpliedFeaturesBMI
Definition: X86TargetParser.cpp:493
llvm::sys::path::end
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:235
llvm::sys::path::begin
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:226
llvm::X86::getKeyFeature
ProcessorFeatures getKeyFeature(CPUKind Kind)
Get the key feature prioritizing target multiversioning.
Definition: X86TargetParser.cpp:477
llvm::operator!=
bool operator!=(uint64_t V1, const APInt &V2)
Definition: APInt.h:2040
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:41
FeaturesK8
constexpr FeatureBitset FeaturesK8
Definition: X86TargetParser.cpp:251
ImpliedFeaturesXSAVEOPT
constexpr FeatureBitset ImpliedFeaturesXSAVEOPT
Definition: X86TargetParser.cpp:547
llvm::X86::CK_SandyBridge
@ CK_SandyBridge
Definition: X86TargetParser.h:92
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
ImpliedFeaturesXSAVES
constexpr FeatureBitset ImpliedFeaturesXSAVES
Definition: X86TargetParser.cpp:548
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
ImpliedFeaturesRAOINT
constexpr FeatureBitset ImpliedFeaturesRAOINT
Definition: X86TargetParser.cpp:613
ImpliedFeaturesCMPCCXADD
constexpr FeatureBitset ImpliedFeaturesCMPCCXADD
Definition: X86TargetParser.cpp:612
ImpliedFeaturesMOVDIRI
constexpr FeatureBitset ImpliedFeaturesMOVDIRI
Definition: X86TargetParser.cpp:512
FeaturesNocona
constexpr FeatureBitset FeaturesNocona
Definition: X86TargetParser.cpp:135
llvm::LegalityPredicates::any
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
Definition: LegalizerInfo.h:241
ImpliedFeaturesAVX512VPOPCNTDQ
constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ
Definition: X86TargetParser.cpp:589
llvm::X86::CK_Nocona
@ CK_Nocona
Definition: X86TargetParser.h:82
llvm::X86::CK_Bonnell
@ CK_Bonnell
Definition: X86TargetParser.h:85
llvm::X86::CK_Lakemont
@ CK_Lakemont
Definition: X86TargetParser.h:115
FeaturesK6
constexpr FeatureBitset FeaturesK6
Definition: X86TargetParser.cpp:244
ImpliedFeaturesVZEROUPPER
constexpr FeatureBitset ImpliedFeaturesVZEROUPPER
Definition: X86TargetParser.cpp:533
ImpliedFeaturesAVX512BW
constexpr FeatureBitset ImpliedFeaturesAVX512BW
Definition: X86TargetParser.cpp:579
llvm::X86::CK_PentiumMMX
@ CK_PentiumMMX
Definition: X86TargetParser.h:72
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::X86::CK_GoldmontPlus
@ CK_GoldmontPlus
Definition: X86TargetParser.h:88
llvm::operator&=
bool operator&=(SparseBitVector< ElementSize > *LHS, const SparseBitVector< ElementSize > &RHS)
Definition: SparseBitVector.h:835
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:841
llvm::X86::parseArchX86
CPUKind parseArchX86(StringRef CPU, bool Only64Bit=false)
Parse CPU string into a CPUKind.
Definition: X86TargetParser.cpp:448
llvm::X86::CK_KNM
@ CK_KNM
Definition: X86TargetParser.h:114
llvm::X86::CK_x86_64
@ CK_x86_64
Definition: X86TargetParser.h:134
llvm::X86::CK_None
@ CK_None
Definition: X86TargetParser.h:64
llvm::X86::CK_Sierraforest
@ CK_Sierraforest
Definition: X86TargetParser.h:109
ImpliedFeaturesXOP
constexpr FeatureBitset ImpliedFeaturesXOP
Definition: X86TargetParser.cpp:602
ImpliedFeaturesF16C
constexpr FeatureBitset ImpliedFeaturesF16C
Definition: X86TargetParser.cpp:569
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::X86::CPU_FEATURE_MAX
@ CPU_FEATURE_MAX
Definition: X86TargetParser.h:60
llvm::X86::CK_ZNVER1
@ CK_ZNVER1
Definition: X86TargetParser.h:130
ImpliedFeaturesAVX512BF16
constexpr FeatureBitset ImpliedFeaturesAVX512BF16
Definition: X86TargetParser.cpp:585
llvm::X86::getFeaturePriority
unsigned getFeaturePriority(ProcessorFeatures Feat)
Definition: X86TargetParser.cpp:718
FeaturesZNVER1
constexpr FeatureBitset FeaturesZNVER1
Definition: X86TargetParser.cpp:285
llvm::X86::CK_WinChip2
@ CK_WinChip2
Definition: X86TargetParser.h:68
ImpliedFeaturesCRC32
constexpr FeatureBitset ImpliedFeaturesCRC32
Definition: X86TargetParser.cpp:502
llvm::X86::CK_C3
@ CK_C3
Definition: X86TargetParser.h:69
llvm::X86::fillValidCPUArchList
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid CPU names.
Definition: X86TargetParser.cpp:462
FeaturesPentiumMMX
constexpr FeatureBitset FeaturesPentiumMMX
Definition: X86TargetParser.cpp:124
ImpliedFeaturesSSE2
constexpr FeatureBitset ImpliedFeaturesSSE2
Definition: X86TargetParser.cpp:557
FeaturesICLClient
constexpr FeatureBitset FeaturesICLClient
Definition: X86TargetParser.cpp:194
FeaturesX86_64_V3
constexpr FeatureBitset FeaturesX86_64_V3
Definition: X86TargetParser.cpp:143
ImpliedFeaturesINVPCID
constexpr FeatureBitset ImpliedFeaturesINVPCID
Definition: X86TargetParser.cpp:506
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
ImpliedFeatures3DNOW
constexpr FeatureBitset ImpliedFeatures3DNOW
Definition: X86TargetParser.cpp:552
FeaturesRocketlake
constexpr FeatureBitset FeaturesRocketlake
Definition: X86TargetParser.cpp:198
ImpliedFeaturesAVX512ER
constexpr FeatureBitset ImpliedFeaturesAVX512ER
Definition: X86TargetParser.cpp:581
ImpliedFeaturesXSAVEC
constexpr FeatureBitset ImpliedFeaturesXSAVEC
Definition: X86TargetParser.cpp:546
ImpliedFeaturesFSGSBASE
constexpr FeatureBitset ImpliedFeaturesFSGSBASE
Definition: X86TargetParser.cpp:504
ImpliedFeaturesXSAVE
constexpr FeatureBitset ImpliedFeaturesXSAVE
Definition: X86TargetParser.cpp:535
llvm::X86::CK_ZNVER4
@ CK_ZNVER4
Definition: X86TargetParser.h:133
FeaturesAthlonXP
constexpr FeatureBitset FeaturesAthlonXP
Definition: X86TargetParser.cpp:249
ImpliedFeaturesMMX
constexpr FeatureBitset ImpliedFeaturesMMX
Definition: X86TargetParser.cpp:551
ImpliedFeaturesVAES
constexpr FeatureBitset ImpliedFeaturesVAES
Definition: X86TargetParser.cpp:574
ImpliedFeaturesFMA4
constexpr FeatureBitset ImpliedFeaturesFMA4
Definition: X86TargetParser.cpp:601
FeaturesGrandridge
constexpr FeatureBitset FeaturesGrandridge
Definition: X86TargetParser.cpp:236
ImpliedFeaturesLWP
constexpr FeatureBitset ImpliedFeaturesLWP
Definition: X86TargetParser.cpp:507
ImpliedFeaturesAVX512VNNI
constexpr FeatureBitset ImpliedFeaturesAVX512VNNI
Definition: X86TargetParser.cpp:588
FeaturesPentium4
constexpr FeatureBitset FeaturesPentium4
Definition: X86TargetParser.cpp:133
FeaturesSierraforest
constexpr FeatureBitset FeaturesSierraforest
Definition: X86TargetParser.cpp:233
FeaturesGeode
constexpr FeatureBitset FeaturesGeode
Definition: X86TargetParser.cpp:240
FeaturesTigerlake
constexpr FeatureBitset FeaturesTigerlake
Definition: X86TargetParser.cpp:201
llvm::X86::CK_K8SSE3
@ CK_K8SSE3
Definition: X86TargetParser.h:122
ImpliedFeaturesENQCMD
constexpr FeatureBitset ImpliedFeaturesENQCMD
Definition: X86TargetParser.cpp:503
ImpliedFeaturesPKU
constexpr FeatureBitset ImpliedFeaturesPKU
Definition: X86TargetParser.cpp:515
llvm::X86::CK_PentiumM
@ CK_PentiumM
Definition: X86TargetParser.h:77
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
FeaturesHaswell
constexpr FeatureBitset FeaturesHaswell
Definition: X86TargetParser.cpp:161
FeaturesCooperLake
constexpr FeatureBitset FeaturesCooperLake
Definition: X86TargetParser.cpp:186
ImpliedFeaturesPTWRITE
constexpr FeatureBitset ImpliedFeaturesPTWRITE
Definition: X86TargetParser.cpp:518
llvm::StringMap< bool >
FeaturesCannonlake
constexpr FeatureBitset FeaturesCannonlake
Definition: X86TargetParser.cpp:190
ImpliedFeaturesAMX_TILE
constexpr FeatureBitset ImpliedFeaturesAMX_TILE
Definition: X86TargetParser.cpp:605
llvm::X86::CK_Nehalem
@ CK_Nehalem
Definition: X86TargetParser.h:90
FeaturesK8SSE3
constexpr FeatureBitset FeaturesK8SSE3
Definition: X86TargetParser.cpp:253
ImpliedFeaturesSSE4_2
constexpr FeatureBitset ImpliedFeaturesSSE4_2
Definition: X86TargetParser.cpp:561
ImpliedFeaturesSGX
constexpr FeatureBitset ImpliedFeaturesSGX
Definition: X86TargetParser.cpp:526
ImpliedFeaturesSSE
constexpr FeatureBitset ImpliedFeaturesSSE
Definition: X86TargetParser.cpp:556
llvm::X86::CK_Cannonlake
@ CK_Cannonlake
Definition: X86TargetParser.h:100
ImpliedFeaturesAVX512F
constexpr FeatureBitset ImpliedFeaturesAVX512F
Definition: X86TargetParser.cpp:564
ImpliedFeaturesPCONFIG
constexpr FeatureBitset ImpliedFeaturesPCONFIG
Definition: X86TargetParser.cpp:513
FeaturesAlderlake
constexpr FeatureBitset FeaturesAlderlake
Definition: X86TargetParser.cpp:227
ImpliedFeaturesWAITPKG
constexpr FeatureBitset ImpliedFeaturesWAITPKG
Definition: X86TargetParser.cpp:531
llvm::X86::CK_Haswell
@ CK_Haswell
Definition: X86TargetParser.h:94
llvm::AMDGPU::FEATURE_FMA
@ FEATURE_FMA
Definition: TargetParser.h:125
FeaturesX86_64_V2
constexpr FeatureBitset FeaturesX86_64_V2
Definition: X86TargetParser.cpp:140
ImpliedFeaturesFMA
constexpr FeatureBitset ImpliedFeaturesFMA
Definition: X86TargetParser.cpp:570
llvm::operator|
APInt operator|(APInt a, const APInt &b)
Definition: APInt.h:2070
llvm::X86::CK_ZNVER3
@ CK_ZNVER3
Definition: X86TargetParser.h:132
ImpliedFeaturesTBM
constexpr FeatureBitset ImpliedFeaturesTBM
Definition: X86TargetParser.cpp:528
ImpliedFeaturesPREFETCHWT1
constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1
Definition: X86TargetParser.cpp:516
uint64_t
ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES
Definition: X86TargetParser.cpp:540
FeaturesBTVER2
constexpr FeatureBitset FeaturesBTVER2
Definition: X86TargetParser.cpp:264
ImpliedFeaturesAVX512PF
constexpr FeatureBitset ImpliedFeaturesAVX512PF
Definition: X86TargetParser.cpp:582
llvm::X86::CK_BDVER3
@ CK_BDVER3
Definition: X86TargetParser.h:128
ImpliedFeaturesADX
constexpr FeatureBitset ImpliedFeaturesADX
Definition: X86TargetParser.cpp:492
llvm::X86::CK_Pentium
@ CK_Pentium
Definition: X86TargetParser.h:71
llvm::X86::updateImpliedFeatures
void updateImpliedFeatures(StringRef Feature, bool Enabled, StringMap< bool > &Features)
Set or clear entries in Features that are implied to be enabled/disabled by the provided Feature.
Definition: X86TargetParser.cpp:680
FeaturesSapphireRapids
constexpr FeatureBitset FeaturesSapphireRapids
Definition: X86TargetParser.cpp:204
llvm::X86::CK_BDVER4
@ CK_BDVER4
Definition: X86TargetParser.h:129
llvm::X86::CK_AMDFAM10
@ CK_AMDFAM10
Definition: X86TargetParser.h:123
I
#define I(x, y, z)
Definition: MD5.cpp:58
size
i< reg-> size
Definition: README.txt:166
llvm::X86::CK_Meteorlake
@ CK_Meteorlake
Definition: X86TargetParser.h:108
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1869
ImpliedFeaturesCLWB
constexpr FeatureBitset ImpliedFeaturesCLWB
Definition: X86TargetParser.cpp:497
ImpliedFeaturesAVX512VL
constexpr FeatureBitset ImpliedFeaturesAVX512VL
Definition: X86TargetParser.cpp:583
ImpliedFeaturesLVI_CFI
constexpr FeatureBitset ImpliedFeaturesLVI_CFI
Definition: X86TargetParser.cpp:542
FeaturesBDVER4
constexpr FeatureBitset FeaturesBDVER4
Definition: X86TargetParser.cpp:280
ImpliedFeaturesAVX2
constexpr FeatureBitset ImpliedFeaturesAVX2
Definition: X86TargetParser.cpp:563
llvm::X86::CK_Grandridge
@ CK_Grandridge
Definition: X86TargetParser.h:110
llvm::X86::getFeaturesForCPU
void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< StringRef > &Features)
Fill in the features that CPU supports into Features.
Definition: X86TargetParser.cpp:631
ImpliedFeaturesAVX512VP2INTERSECT
constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT
Definition: X86TargetParser.cpp:592
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FeaturesGoldmont
constexpr FeatureBitset FeaturesGoldmont
Definition: X86TargetParser.cpp:219
ImpliedFeaturesSHSTK
constexpr FeatureBitset ImpliedFeaturesSHSTK
Definition: X86TargetParser.cpp:527
ImpliedFeaturesFXSR
constexpr FeatureBitset ImpliedFeaturesFXSR
Definition: X86TargetParser.cpp:505
llvm::X86::CK_Westmere
@ CK_Westmere
Definition: X86TargetParser.h:91
llvm::X86::CK_Rocketlake
@ CK_Rocketlake
Definition: X86TargetParser.h:102
llvm::X86::CK_Broadwell
@ CK_Broadwell
Definition: X86TargetParser.h:95
llvm::X86::CK_K8
@ CK_K8
Definition: X86TargetParser.h:121
llvm::X86::CK_WinChipC6
@ CK_WinChipC6
Definition: X86TargetParser.h:67
llvm::X86::CK_BDVER1
@ CK_BDVER1
Definition: X86TargetParser.h:126
ImpliedFeaturesRTM
constexpr FeatureBitset ImpliedFeaturesRTM
Definition: X86TargetParser.cpp:523
llvm::X86::CK_x86_64_v3
@ CK_x86_64_v3
Definition: X86TargetParser.h:136
llvm::X86::CK_SapphireRapids
@ CK_SapphireRapids
Definition: X86TargetParser.h:105
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
ImpliedFeaturesSSE4_1
constexpr FeatureBitset ImpliedFeaturesSSE4_1
Definition: X86TargetParser.cpp:560
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1742
llvm::X86::CK_K6_3
@ CK_K6_3
Definition: X86TargetParser.h:118
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::X86::CK_Silvermont
@ CK_Silvermont
Definition: X86TargetParser.h:86
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::operator|=
bool operator|=(SparseBitVector< ElementSize > &LHS, const SparseBitVector< ElementSize > *RHS)
Definition: SparseBitVector.h:823
ImpliedFeaturesAMX_BF16
constexpr FeatureBitset ImpliedFeaturesAMX_BF16
Definition: X86TargetParser.cpp:606
uint32_t
llvm::X86::CK_Pentium2
@ CK_Pentium2
Definition: X86TargetParser.h:75
FeaturesSilvermont
constexpr FeatureBitset FeaturesSilvermont
Definition: X86TargetParser.cpp:217
llvm::X86::CK_Graniterapids
@ CK_Graniterapids
Definition: X86TargetParser.h:111
FeaturesKNM
constexpr FeatureBitset FeaturesKNM
Definition: X86TargetParser.cpp:172
FeaturesBDVER2
constexpr FeatureBitset FeaturesBDVER2
Definition: X86TargetParser.cpp:276
FeaturesX86_64_V4
constexpr FeatureBitset FeaturesX86_64_V4
Definition: X86TargetParser.cpp:146
ImpliedFeaturesVPCLMULQDQ
constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ
Definition: X86TargetParser.cpp:575
ImpliedFeaturesSSE4_A
constexpr FeatureBitset ImpliedFeaturesSSE4_A
Definition: X86TargetParser.cpp:600
llvm::X86::CK_IcelakeServer
@ CK_IcelakeServer
Definition: X86TargetParser.h:103
llvm::X86::ProcessorFeatures
ProcessorFeatures
Definition: X86TargetParser.h:57
llvm::X86::CK_Tigerlake
@ CK_Tigerlake
Definition: X86TargetParser.h:104
llvm::Init
Definition: Record.h:282
ImpliedFeaturesRDSEED
constexpr FeatureBitset ImpliedFeaturesRDSEED
Definition: X86TargetParser.cpp:522
llvm::X86::CK_x86_64_v4
@ CK_x86_64_v4
Definition: X86TargetParser.h:137
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1762
ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK
Definition: X86TargetParser.cpp:539
FeaturesGoldmontPlus
constexpr FeatureBitset FeaturesGoldmontPlus
Definition: X86TargetParser.cpp:223
llvm::operator~
APInt operator~(APInt v)
Unary bitwise complement operator.
Definition: APInt.h:2045
ImpliedFeaturesBMI2
constexpr FeatureBitset ImpliedFeaturesBMI2
Definition: X86TargetParser.cpp:494
llvm::operator&
APInt operator&(APInt a, const APInt &b)
Definition: APInt.h:2050
llvm::X86::CK_BTVER1
@ CK_BTVER1
Definition: X86TargetParser.h:124
ImpliedFeaturesSERIALIZE
constexpr FeatureBitset ImpliedFeaturesSERIALIZE
Definition: X86TargetParser.cpp:525
ImpliedFeaturesLVI_LOAD_HARDENING
constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING
Definition: X86TargetParser.cpp:543
llvm::X86::CK_i486
@ CK_i486
Definition: X86TargetParser.h:66
ImpliedFeaturesAVX512IFMA
constexpr FeatureBitset ImpliedFeaturesAVX512IFMA
Definition: X86TargetParser.cpp:587
FeaturesPrescott
constexpr FeatureBitset FeaturesPrescott
Definition: X86TargetParser.cpp:134
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
ImpliedFeaturesPRFCHW
constexpr FeatureBitset ImpliedFeaturesPRFCHW
Definition: X86TargetParser.cpp:517
FeaturesKNL
constexpr FeatureBitset FeaturesKNL
Definition: X86TargetParser.cpp:169
llvm::X86::CK_K6_2
@ CK_K6_2
Definition: X86TargetParser.h:117
Processors
constexpr ProcInfo Processors[]
Definition: X86TargetParser.cpp:308
ImpliedFeaturesAVX
constexpr FeatureBitset ImpliedFeaturesAVX
Definition: X86TargetParser.cpp:562
Enabled
static bool Enabled
Definition: Statistic.cpp:46
FeaturesZNVER2
constexpr FeatureBitset FeaturesZNVER2
Definition: X86TargetParser.cpp:295
FeaturesSkylakeClient
constexpr FeatureBitset FeaturesSkylakeClient
Definition: X86TargetParser.cpp:175
llvm::X86::CK_Goldmont
@ CK_Goldmont
Definition: X86TargetParser.h:87
ImpliedFeaturesPREFETCHI
constexpr FeatureBitset ImpliedFeaturesPREFETCHI
Definition: X86TargetParser.cpp:611
llvm::X86::CK_BTVER2
@ CK_BTVER2
Definition: X86TargetParser.h:125
FeaturesWestmere
constexpr FeatureBitset FeaturesWestmere
Definition: X86TargetParser.cpp:156
llvm::X86::CK_ZNVER2
@ CK_ZNVER2
Definition: X86TargetParser.h:131
ImpliedFeaturesAVXVNNIINT8
constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8
Definition: X86TargetParser.cpp:614
ImpliedFeaturesCLFLUSHOPT
constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT
Definition: X86TargetParser.cpp:496
FeatureInfos
constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX]
Definition: X86TargetParser.cpp:626
FeaturesCascadeLake
constexpr FeatureBitset FeaturesCascadeLake
Definition: X86TargetParser.cpp:184
StringSwitch.h
ImpliedFeaturesAVX5124FMAPS
constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS
Definition: X86TargetParser.cpp:596
ImpliedFeaturesSSE3
constexpr FeatureBitset ImpliedFeaturesSSE3
Definition: X86TargetParser.cpp:558
FeaturesSkylakeServer
constexpr FeatureBitset FeaturesSkylakeServer
Definition: X86TargetParser.cpp:180
llvm::X86::CK_i586
@ CK_i586
Definition: X86TargetParser.h:70
llvm::X86::CK_Pentium4
@ CK_Pentium4
Definition: X86TargetParser.h:80
llvm::X86::fillValidTuneCPUList
void fillValidTuneCPUList(SmallVectorImpl< StringRef > &Values, bool Only64Bit=false)
Provide a list of valid -mtune names.
Definition: X86TargetParser.cpp:469
ImpliedFeaturesPOPCNT
constexpr FeatureBitset ImpliedFeaturesPOPCNT
Definition: X86TargetParser.cpp:514
llvm::X86::CK_Core2
@ CK_Core2
Definition: X86TargetParser.h:83
ImpliedFeaturesKL
constexpr FeatureBitset ImpliedFeaturesKL
Definition: X86TargetParser.cpp:620
llvm::X86::parseTuneCPU
CPUKind parseTuneCPU(StringRef CPU, bool Only64Bit=false)
Definition: X86TargetParser.cpp:456
X86TargetParser.h
ImpliedFeaturesHRESET
constexpr FeatureBitset ImpliedFeaturesHRESET
Definition: X86TargetParser.cpp:609
FeaturesX86_64
constexpr FeatureBitset FeaturesX86_64
Definition: X86TargetParser.cpp:139
ImpliedFeaturesCLDEMOTE
constexpr FeatureBitset ImpliedFeaturesCLDEMOTE
Definition: X86TargetParser.cpp:495
ImpliedFeaturesX87
constexpr FeatureBitset ImpliedFeaturesX87
Definition: X86TargetParser.cpp:534
llvm::X86::CK_IvyBridge
@ CK_IvyBridge
Definition: X86TargetParser.h:93
ImpliedFeaturesSAHF
constexpr FeatureBitset ImpliedFeaturesSAHF
Definition: X86TargetParser.cpp:524
llvm::X86::CK_Emeraldrapids
@ CK_Emeraldrapids
Definition: X86TargetParser.h:112
NoTuneList
constexpr const char * NoTuneList[]
Definition: X86TargetParser.cpp:446
ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS
Definition: X86TargetParser.cpp:541
FeaturesAMDFAM10
constexpr FeatureBitset FeaturesAMDFAM10
Definition: X86TargetParser.cpp:254
ImpliedFeaturesAVX512VBMI
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI
Definition: X86TargetParser.cpp:590
ImpliedFeaturesSSSE3
constexpr FeatureBitset ImpliedFeaturesSSSE3
Definition: X86TargetParser.cpp:559
FeaturesTremont
constexpr FeatureBitset FeaturesTremont
Definition: X86TargetParser.cpp:225
ImpliedFeaturesAVX5124VNNIW
constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW
Definition: X86TargetParser.cpp:597
ImpliedFeaturesAVXIFMA
constexpr FeatureBitset ImpliedFeaturesAVXIFMA
Definition: X86TargetParser.cpp:615
llvm::X86::CK_Tremont
@ CK_Tremont
Definition: X86TargetParser.h:89
llvm::X86::CK_Alderlake
@ CK_Alderlake
Definition: X86TargetParser.h:106
ImpliedFeaturesAMX_INT8
constexpr FeatureBitset ImpliedFeaturesAMX_INT8
Definition: X86TargetParser.cpp:608
llvm::SmallVectorImpl< StringRef >
ImpliedFeaturesRDPRU
constexpr FeatureBitset ImpliedFeaturesRDPRU
Definition: X86TargetParser.cpp:520
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::X86::CK_Cascadelake
@ CK_Cascadelake
Definition: X86TargetParser.h:98
FeaturesSandyBridge
constexpr FeatureBitset FeaturesSandyBridge
Definition: X86TargetParser.cpp:157
llvm::X86::CK_Penryn
@ CK_Penryn
Definition: X86TargetParser.h:84
ImpliedFeaturesAVX512VBMI2
constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2
Definition: X86TargetParser.cpp:591
ImpliedFeaturesAVX512DQ
constexpr FeatureBitset ImpliedFeaturesAVX512DQ
Definition: X86TargetParser.cpp:580
llvm::X86::CK_Cooperlake
@ CK_Cooperlake
Definition: X86TargetParser.h:99
llvm::X86::CK_AthlonXP
@ CK_AthlonXP
Definition: X86TargetParser.h:120
ImpliedFeaturesAMX_FP16
constexpr FeatureBitset ImpliedFeaturesAMX_FP16
Definition: X86TargetParser.cpp:607
llvm::X86::CK_i386
@ CK_i386
Definition: X86TargetParser.h:65
ImpliedFeaturesCMPXCHG8B
constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B
Definition: X86TargetParser.cpp:501
llvm::FeatureBitset::any
bool any() const
Definition: SubtargetFeature.h:92
llvm::X86::CK_Pentium3
@ CK_Pentium3
Definition: X86TargetParser.h:76
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
FeaturesBDVER1
constexpr FeatureBitset FeaturesBDVER1
Definition: X86TargetParser.cpp:269
ImpliedFeaturesWIDEKL
constexpr FeatureBitset ImpliedFeaturesWIDEKL
Definition: X86TargetParser.cpp:621
ImpliedFeaturesRDPID
constexpr FeatureBitset ImpliedFeaturesRDPID
Definition: X86TargetParser.cpp:519
FeaturesBTVER1
constexpr FeatureBitset FeaturesBTVER1
Definition: X86TargetParser.cpp:259
ImpliedFeaturesAVX512BITALG
constexpr FeatureBitset ImpliedFeaturesAVX512BITALG
Definition: X86TargetParser.cpp:586
ImpliedFeaturesPCLMUL
constexpr FeatureBitset ImpliedFeaturesPCLMUL
Definition: X86TargetParser.cpp:572
ImpliedFeaturesCMOV
constexpr FeatureBitset ImpliedFeaturesCMOV
Definition: X86TargetParser.cpp:499
llvm::SmallVectorImpl::emplace_back
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:941
llvm::X86::CK_Yonah
@ CK_Yonah
Definition: X86TargetParser.h:79
ImpliedFeatures3DNOWA
constexpr FeatureBitset ImpliedFeatures3DNOWA
Definition: X86TargetParser.cpp:553
llvm::X86::CK_Geode
@ CK_Geode
Definition: X86TargetParser.h:138