LLVM  14.0.0git
X86FloatingPoint.cpp
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1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the pass which converts floating point instructions from
10 // pseudo registers into register stack instructions. This pass uses live
11 // variable information to indicate where the FPn registers are used and their
12 // lifetimes.
13 //
14 // The x87 hardware tracks liveness of the stack registers, so it is necessary
15 // to implement exact liveness tracking between basic blocks. The CFG edges are
16 // partitioned into bundles where the same FP registers must be live in
17 // identical stack positions. Instructions are inserted at the end of each basic
18 // block to rearrange the live registers to match the outgoing bundle.
19 //
20 // This approach avoids splitting critical edges at the potential cost of more
21 // live register shuffling instructions when critical edges are present.
22 //
23 //===----------------------------------------------------------------------===//
24 
25 #include "X86.h"
26 #include "X86InstrInfo.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/Statistic.h"
38 #include "llvm/CodeGen/Passes.h"
41 #include "llvm/Config/llvm-config.h"
42 #include "llvm/IR/InlineAsm.h"
43 #include "llvm/InitializePasses.h"
44 #include "llvm/Support/Debug.h"
48 #include <algorithm>
49 #include <bitset>
50 using namespace llvm;
51 
52 #define DEBUG_TYPE "x86-codegen"
53 
54 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
55 STATISTIC(NumFP , "Number of floating point instructions");
56 
57 namespace {
58  const unsigned ScratchFPReg = 7;
59 
60  struct FPS : public MachineFunctionPass {
61  static char ID;
62  FPS() : MachineFunctionPass(ID) {
63  // This is really only to keep valgrind quiet.
64  // The logic in isLive() is too much for it.
65  memset(Stack, 0, sizeof(Stack));
66  memset(RegMap, 0, sizeof(RegMap));
67  }
68 
69  void getAnalysisUsage(AnalysisUsage &AU) const override {
70  AU.setPreservesCFG();
75  }
76 
77  bool runOnMachineFunction(MachineFunction &MF) override;
78 
79  MachineFunctionProperties getRequiredProperties() const override {
82  }
83 
84  StringRef getPassName() const override { return "X86 FP Stackifier"; }
85 
86  private:
87  const TargetInstrInfo *TII = nullptr; // Machine instruction info.
88 
89  // Two CFG edges are related if they leave the same block, or enter the same
90  // block. The transitive closure of an edge under this relation is a
91  // LiveBundle. It represents a set of CFG edges where the live FP stack
92  // registers must be allocated identically in the x87 stack.
93  //
94  // A LiveBundle is usually all the edges leaving a block, or all the edges
95  // entering a block, but it can contain more edges if critical edges are
96  // present.
97  //
98  // The set of live FP registers in a LiveBundle is calculated by bundleCFG,
99  // but the exact mapping of FP registers to stack slots is fixed later.
100  struct LiveBundle {
101  // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c.
102  unsigned Mask;
103 
104  // Number of pre-assigned live registers in FixStack. This is 0 when the
105  // stack order has not yet been fixed.
106  unsigned FixCount;
107 
108  // Assigned stack order for live-in registers.
109  // FixStack[i] == getStackEntry(i) for all i < FixCount.
110  unsigned char FixStack[8];
111 
112  LiveBundle() : Mask(0), FixCount(0) {}
113 
114  // Have the live registers been assigned a stack order yet?
115  bool isFixed() const { return !Mask || FixCount; }
116  };
117 
118  // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges
119  // with no live FP registers.
120  SmallVector<LiveBundle, 8> LiveBundles;
121 
122  // The edge bundle analysis provides indices into the LiveBundles vector.
123  EdgeBundles *Bundles = nullptr;
124 
125  // Return a bitmask of FP registers in block's live-in list.
126  static unsigned calcLiveInMask(MachineBasicBlock *MBB, bool RemoveFPs) {
127  unsigned Mask = 0;
129  I != MBB->livein_end(); ) {
130  MCPhysReg Reg = I->PhysReg;
131  static_assert(X86::FP6 - X86::FP0 == 6, "sequential regnums");
132  if (Reg >= X86::FP0 && Reg <= X86::FP6) {
133  Mask |= 1 << (Reg - X86::FP0);
134  if (RemoveFPs) {
135  I = MBB->removeLiveIn(I);
136  continue;
137  }
138  }
139  ++I;
140  }
141  return Mask;
142  }
143 
144  // Partition all the CFG edges into LiveBundles.
145  void bundleCFGRecomputeKillFlags(MachineFunction &MF);
146 
147  MachineBasicBlock *MBB = nullptr; // Current basic block
148 
149  // The hardware keeps track of how many FP registers are live, so we have
150  // to model that exactly. Usually, each live register corresponds to an
151  // FP<n> register, but when dealing with calls, returns, and inline
152  // assembly, it is sometimes necessary to have live scratch registers.
153  unsigned Stack[8]; // FP<n> Registers in each stack slot...
154  unsigned StackTop = 0; // The current top of the FP stack.
155 
156  enum {
157  NumFPRegs = 8 // Including scratch pseudo-registers.
158  };
159 
160  // For each live FP<n> register, point to its Stack[] entry.
161  // The first entries correspond to FP0-FP6, the rest are scratch registers
162  // used when we need slightly different live registers than what the
163  // register allocator thinks.
164  unsigned RegMap[NumFPRegs];
165 
166  // Set up our stack model to match the incoming registers to MBB.
167  void setupBlockStack();
168 
169  // Shuffle live registers to match the expectations of successor blocks.
170  void finishBlockStack();
171 
172 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
173  void dumpStack() const {
174  dbgs() << "Stack contents:";
175  for (unsigned i = 0; i != StackTop; ++i) {
176  dbgs() << " FP" << Stack[i];
177  assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
178  }
179  }
180 #endif
181 
182  /// getSlot - Return the stack slot number a particular register number is
183  /// in.
184  unsigned getSlot(unsigned RegNo) const {
185  assert(RegNo < NumFPRegs && "Regno out of range!");
186  return RegMap[RegNo];
187  }
188 
189  /// isLive - Is RegNo currently live in the stack?
190  bool isLive(unsigned RegNo) const {
191  unsigned Slot = getSlot(RegNo);
192  return Slot < StackTop && Stack[Slot] == RegNo;
193  }
194 
195  /// getStackEntry - Return the X86::FP<n> register in register ST(i).
196  unsigned getStackEntry(unsigned STi) const {
197  if (STi >= StackTop)
198  report_fatal_error("Access past stack top!");
199  return Stack[StackTop-1-STi];
200  }
201 
202  /// getSTReg - Return the X86::ST(i) register which contains the specified
203  /// FP<RegNo> register.
204  unsigned getSTReg(unsigned RegNo) const {
205  return StackTop - 1 - getSlot(RegNo) + X86::ST0;
206  }
207 
208  // pushReg - Push the specified FP<n> register onto the stack.
209  void pushReg(unsigned Reg) {
210  assert(Reg < NumFPRegs && "Register number out of range!");
211  if (StackTop >= 8)
212  report_fatal_error("Stack overflow!");
213  Stack[StackTop] = Reg;
214  RegMap[Reg] = StackTop++;
215  }
216 
217  // popReg - Pop a register from the stack.
218  void popReg() {
219  if (StackTop == 0)
220  report_fatal_error("Cannot pop empty stack!");
221  RegMap[Stack[--StackTop]] = ~0; // Update state
222  }
223 
224  bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
225  void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
226  DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
227  if (isAtTop(RegNo)) return;
228 
229  unsigned STReg = getSTReg(RegNo);
230  unsigned RegOnTop = getStackEntry(0);
231 
232  // Swap the slots the regs are in.
233  std::swap(RegMap[RegNo], RegMap[RegOnTop]);
234 
235  // Swap stack slot contents.
236  if (RegMap[RegOnTop] >= StackTop)
237  report_fatal_error("Access past stack top!");
238  std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
239 
240  // Emit an fxch to update the runtime processors version of the state.
241  BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
242  ++NumFXCH;
243  }
244 
245  void duplicateToTop(unsigned RegNo, unsigned AsReg,
247  DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
248  unsigned STReg = getSTReg(RegNo);
249  pushReg(AsReg); // New register on top of stack
250 
251  BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
252  }
253 
254  /// popStackAfter - Pop the current value off of the top of the FP stack
255  /// after the specified instruction.
256  void popStackAfter(MachineBasicBlock::iterator &I);
257 
258  /// freeStackSlotAfter - Free the specified register from the register
259  /// stack, so that it is no longer in a register. If the register is
260  /// currently at the top of the stack, we just pop the current instruction,
261  /// otherwise we store the current top-of-stack into the specified slot,
262  /// then pop the top of stack.
263  void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
264 
265  /// freeStackSlotBefore - Just the pop, no folding. Return the inserted
266  /// instruction.
268  freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo);
269 
270  /// Adjust the live registers to be the set in Mask.
271  void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I);
272 
273  /// Shuffle the top FixCount stack entries such that FP reg FixStack[0] is
274  /// st(0), FP reg FixStack[1] is st(1) etc.
275  void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount,
277 
278  bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
279 
280  void handleCall(MachineBasicBlock::iterator &I);
281  void handleReturn(MachineBasicBlock::iterator &I);
282  void handleZeroArgFP(MachineBasicBlock::iterator &I);
283  void handleOneArgFP(MachineBasicBlock::iterator &I);
284  void handleOneArgFPRW(MachineBasicBlock::iterator &I);
285  void handleTwoArgFP(MachineBasicBlock::iterator &I);
286  void handleCompareFP(MachineBasicBlock::iterator &I);
287  void handleCondMovFP(MachineBasicBlock::iterator &I);
288  void handleSpecialFP(MachineBasicBlock::iterator &I);
289 
290  // Check if a COPY instruction is using FP registers.
291  static bool isFPCopy(MachineInstr &MI) {
292  Register DstReg = MI.getOperand(0).getReg();
293  Register SrcReg = MI.getOperand(1).getReg();
294 
295  return X86::RFP80RegClass.contains(DstReg) ||
296  X86::RFP80RegClass.contains(SrcReg);
297  }
298 
299  void setKillFlags(MachineBasicBlock &MBB) const;
300  };
301 }
302 
303 char FPS::ID = 0;
304 
305 INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier",
306  false, false)
310 
312 
313 /// getFPReg - Return the X86::FPx register number for the specified operand.
314 /// For example, this returns 3 for X86::FP3.
315 static unsigned getFPReg(const MachineOperand &MO) {
316  assert(MO.isReg() && "Expected an FP register!");
317  Register Reg = MO.getReg();
318  assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
319  return Reg - X86::FP0;
320 }
321 
322 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
323 /// register references into FP stack references.
324 ///
325 bool FPS::runOnMachineFunction(MachineFunction &MF) {
326  // We only need to run this pass if there are any FP registers used in this
327  // function. If it is all integer, there is nothing for us to do!
328  bool FPIsUsed = false;
329 
330  static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");
331  const MachineRegisterInfo &MRI = MF.getRegInfo();
332  for (unsigned i = 0; i <= 6; ++i)
333  if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {
334  FPIsUsed = true;
335  break;
336  }
337 
338  // Early exit.
339  if (!FPIsUsed) return false;
340 
341  Bundles = &getAnalysis<EdgeBundles>();
342  TII = MF.getSubtarget().getInstrInfo();
343 
344  // Prepare cross-MBB liveness.
345  bundleCFGRecomputeKillFlags(MF);
346 
347  StackTop = 0;
348 
349  // Process the function in depth first order so that we process at least one
350  // of the predecessors for every reachable block in the function.
352  MachineBasicBlock *Entry = &MF.front();
353 
354  LiveBundle &Bundle =
355  LiveBundles[Bundles->getBundle(Entry->getNumber(), false)];
356 
357  // In regcall convention, some FP registers may not be passed through
358  // the stack, so they will need to be assigned to the stack first
359  if ((Entry->getParent()->getFunction().getCallingConv() ==
360  CallingConv::X86_RegCall) && (Bundle.Mask && !Bundle.FixCount)) {
361  // In the register calling convention, up to one FP argument could be
362  // saved in the first FP register.
363  // If bundle.mask is non-zero and Bundle.FixCount is zero, it means
364  // that the FP registers contain arguments.
365  // The actual value is passed in FP0.
366  // Here we fix the stack and mark FP0 as pre-assigned register.
367  assert((Bundle.Mask & 0xFE) == 0 &&
368  "Only FP0 could be passed as an argument");
369  Bundle.FixCount = 1;
370  Bundle.FixStack[0] = 0;
371  }
372 
373  bool Changed = false;
374  for (MachineBasicBlock *BB : depth_first_ext(Entry, Processed))
375  Changed |= processBasicBlock(MF, *BB);
376 
377  // Process any unreachable blocks in arbitrary order now.
378  if (MF.size() != Processed.size())
379  for (MachineBasicBlock &BB : MF)
380  if (Processed.insert(&BB).second)
381  Changed |= processBasicBlock(MF, BB);
382 
383  LiveBundles.clear();
384 
385  return Changed;
386 }
387 
388 /// bundleCFG - Scan all the basic blocks to determine consistent live-in and
389 /// live-out sets for the FP registers. Consistent means that the set of
390 /// registers live-out from a block is identical to the live-in set of all
391 /// successors. This is not enforced by the normal live-in lists since
392 /// registers may be implicitly defined, or not used by all successors.
393 void FPS::bundleCFGRecomputeKillFlags(MachineFunction &MF) {
394  assert(LiveBundles.empty() && "Stale data in LiveBundles");
395  LiveBundles.resize(Bundles->getNumBundles());
396 
397  // Gather the actual live-in masks for all MBBs.
398  for (MachineBasicBlock &MBB : MF) {
399  setKillFlags(MBB);
400 
401  const unsigned Mask = calcLiveInMask(&MBB, false);
402  if (!Mask)
403  continue;
404  // Update MBB ingoing bundle mask.
405  LiveBundles[Bundles->getBundle(MBB.getNumber(), false)].Mask |= Mask;
406  }
407 }
408 
409 /// processBasicBlock - Loop over all of the instructions in the basic block,
410 /// transforming FP instructions into their stack form.
411 ///
412 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
413  bool Changed = false;
414  MBB = &BB;
415 
416  setupBlockStack();
417 
418  for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
419  MachineInstr &MI = *I;
420  uint64_t Flags = MI.getDesc().TSFlags;
421 
422  unsigned FPInstClass = Flags & X86II::FPTypeMask;
423  if (MI.isInlineAsm())
424  FPInstClass = X86II::SpecialFP;
425 
426  if (MI.isCopy() && isFPCopy(MI))
427  FPInstClass = X86II::SpecialFP;
428 
429  if (MI.isImplicitDef() &&
430  X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
431  FPInstClass = X86II::SpecialFP;
432 
433  if (MI.isCall())
434  FPInstClass = X86II::SpecialFP;
435 
436  if (FPInstClass == X86II::NotFP)
437  continue; // Efficiently ignore non-fp insts!
438 
439  MachineInstr *PrevMI = nullptr;
440  if (I != BB.begin())
441  PrevMI = &*std::prev(I);
442 
443  ++NumFP; // Keep track of # of pseudo instrs
444  LLVM_DEBUG(dbgs() << "\nFPInst:\t" << MI);
445 
446  // Get dead variables list now because the MI pointer may be deleted as part
447  // of processing!
448  SmallVector<unsigned, 8> DeadRegs;
449  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
450  const MachineOperand &MO = MI.getOperand(i);
451  if (MO.isReg() && MO.isDead())
452  DeadRegs.push_back(MO.getReg());
453  }
454 
455  switch (FPInstClass) {
456  case X86II::ZeroArgFP: handleZeroArgFP(I); break;
457  case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
458  case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
459  case X86II::TwoArgFP: handleTwoArgFP(I); break;
460  case X86II::CompareFP: handleCompareFP(I); break;
461  case X86II::CondMovFP: handleCondMovFP(I); break;
462  case X86II::SpecialFP: handleSpecialFP(I); break;
463  default: llvm_unreachable("Unknown FP Type!");
464  }
465 
466  // Check to see if any of the values defined by this instruction are dead
467  // after definition. If so, pop them.
468  for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
469  unsigned Reg = DeadRegs[i];
470  // Check if Reg is live on the stack. An inline-asm register operand that
471  // is in the clobber list and marked dead might not be live on the stack.
472  static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
473  if (Reg >= X86::FP0 && Reg <= X86::FP6 && isLive(Reg-X86::FP0)) {
474  LLVM_DEBUG(dbgs() << "Register FP#" << Reg - X86::FP0 << " is dead!\n");
475  freeStackSlotAfter(I, Reg-X86::FP0);
476  }
477  }
478 
479  // Print out all of the instructions expanded to if -debug
480  LLVM_DEBUG({
481  MachineBasicBlock::iterator PrevI = PrevMI;
482  if (I == PrevI) {
483  dbgs() << "Just deleted pseudo instruction\n";
484  } else {
486  // Rewind to first instruction newly inserted.
487  while (Start != BB.begin() && std::prev(Start) != PrevI)
488  --Start;
489  dbgs() << "Inserted instructions:\n\t";
490  Start->print(dbgs());
491  while (++Start != std::next(I)) {
492  }
493  }
494  dumpStack();
495  });
496  (void)PrevMI;
497 
498  Changed = true;
499  }
500 
501  finishBlockStack();
502 
503  return Changed;
504 }
505 
506 /// setupBlockStack - Use the live bundles to set up our model of the stack
507 /// to match predecessors' live out stack.
508 void FPS::setupBlockStack() {
509  LLVM_DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB)
510  << " derived from " << MBB->getName() << ".\n");
511  StackTop = 0;
512  // Get the live-in bundle for MBB.
513  const LiveBundle &Bundle =
514  LiveBundles[Bundles->getBundle(MBB->getNumber(), false)];
515 
516  if (!Bundle.Mask) {
517  LLVM_DEBUG(dbgs() << "Block has no FP live-ins.\n");
518  return;
519  }
520 
521  // Depth-first iteration should ensure that we always have an assigned stack.
522  assert(Bundle.isFixed() && "Reached block before any predecessors");
523 
524  // Push the fixed live-in registers.
525  for (unsigned i = Bundle.FixCount; i > 0; --i) {
526  LLVM_DEBUG(dbgs() << "Live-in st(" << (i - 1) << "): %fp"
527  << unsigned(Bundle.FixStack[i - 1]) << '\n');
528  pushReg(Bundle.FixStack[i-1]);
529  }
530 
531  // Kill off unwanted live-ins. This can happen with a critical edge.
532  // FIXME: We could keep these live registers around as zombies. They may need
533  // to be revived at the end of a short block. It might save a few instrs.
534  unsigned Mask = calcLiveInMask(MBB, /*RemoveFPs=*/true);
535  adjustLiveRegs(Mask, MBB->begin());
536  LLVM_DEBUG(MBB->dump());
537 }
538 
539 /// finishBlockStack - Revive live-outs that are implicitly defined out of
540 /// MBB. Shuffle live registers to match the expected fixed stack of any
541 /// predecessors, and ensure that all predecessors are expecting the same
542 /// stack.
543 void FPS::finishBlockStack() {
544  // The RET handling below takes care of return blocks for us.
545  if (MBB->succ_empty())
546  return;
547 
548  LLVM_DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB)
549  << " derived from " << MBB->getName() << ".\n");
550 
551  // Get MBB's live-out bundle.
552  unsigned BundleIdx = Bundles->getBundle(MBB->getNumber(), true);
553  LiveBundle &Bundle = LiveBundles[BundleIdx];
554 
555  // We may need to kill and define some registers to match successors.
556  // FIXME: This can probably be combined with the shuffle below.
558  adjustLiveRegs(Bundle.Mask, Term);
559 
560  if (!Bundle.Mask) {
561  LLVM_DEBUG(dbgs() << "No live-outs.\n");
562  return;
563  }
564 
565  // Has the stack order been fixed yet?
566  LLVM_DEBUG(dbgs() << "LB#" << BundleIdx << ": ");
567  if (Bundle.isFixed()) {
568  LLVM_DEBUG(dbgs() << "Shuffling stack to match.\n");
569  shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term);
570  } else {
571  // Not fixed yet, we get to choose.
572  LLVM_DEBUG(dbgs() << "Fixing stack order now.\n");
573  Bundle.FixCount = StackTop;
574  for (unsigned i = 0; i < StackTop; ++i)
575  Bundle.FixStack[i] = getStackEntry(i);
576  }
577 }
578 
579 
580 //===----------------------------------------------------------------------===//
581 // Efficient Lookup Table Support
582 //===----------------------------------------------------------------------===//
583 
584 namespace {
585  struct TableEntry {
586  uint16_t from;
587  uint16_t to;
588  bool operator<(const TableEntry &TE) const { return from < TE.from; }
589  friend bool operator<(const TableEntry &TE, unsigned V) {
590  return TE.from < V;
591  }
592  friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned V,
593  const TableEntry &TE) {
594  return V < TE.from;
595  }
596  };
597 }
598 
599 static int Lookup(ArrayRef<TableEntry> Table, unsigned Opcode) {
600  const TableEntry *I = llvm::lower_bound(Table, Opcode);
601  if (I != Table.end() && I->from == Opcode)
602  return I->to;
603  return -1;
604 }
605 
606 #ifdef NDEBUG
607 #define ASSERT_SORTED(TABLE)
608 #else
609 #define ASSERT_SORTED(TABLE) \
610  { \
611  static std::atomic<bool> TABLE##Checked(false); \
612  if (!TABLE##Checked.load(std::memory_order_relaxed)) { \
613  assert(is_sorted(TABLE) && \
614  "All lookup tables must be sorted for efficient access!"); \
615  TABLE##Checked.store(true, std::memory_order_relaxed); \
616  } \
617  }
618 #endif
619 
620 //===----------------------------------------------------------------------===//
621 // Register File -> Register Stack Mapping Methods
622 //===----------------------------------------------------------------------===//
623 
624 // OpcodeTable - Sorted map of register instructions to their stack version.
625 // The first element is an register file pseudo instruction, the second is the
626 // concrete X86 instruction which uses the register stack.
627 //
628 static const TableEntry OpcodeTable[] = {
629  { X86::ABS_Fp32 , X86::ABS_F },
630  { X86::ABS_Fp64 , X86::ABS_F },
631  { X86::ABS_Fp80 , X86::ABS_F },
632  { X86::ADD_Fp32m , X86::ADD_F32m },
633  { X86::ADD_Fp64m , X86::ADD_F64m },
634  { X86::ADD_Fp64m32 , X86::ADD_F32m },
635  { X86::ADD_Fp80m32 , X86::ADD_F32m },
636  { X86::ADD_Fp80m64 , X86::ADD_F64m },
637  { X86::ADD_FpI16m32 , X86::ADD_FI16m },
638  { X86::ADD_FpI16m64 , X86::ADD_FI16m },
639  { X86::ADD_FpI16m80 , X86::ADD_FI16m },
640  { X86::ADD_FpI32m32 , X86::ADD_FI32m },
641  { X86::ADD_FpI32m64 , X86::ADD_FI32m },
642  { X86::ADD_FpI32m80 , X86::ADD_FI32m },
643  { X86::CHS_Fp32 , X86::CHS_F },
644  { X86::CHS_Fp64 , X86::CHS_F },
645  { X86::CHS_Fp80 , X86::CHS_F },
646  { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
647  { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
648  { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
649  { X86::CMOVB_Fp32 , X86::CMOVB_F },
650  { X86::CMOVB_Fp64 , X86::CMOVB_F },
651  { X86::CMOVB_Fp80 , X86::CMOVB_F },
652  { X86::CMOVE_Fp32 , X86::CMOVE_F },
653  { X86::CMOVE_Fp64 , X86::CMOVE_F },
654  { X86::CMOVE_Fp80 , X86::CMOVE_F },
655  { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
656  { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
657  { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
658  { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
659  { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
660  { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
661  { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
662  { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
663  { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
664  { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
665  { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
666  { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
667  { X86::CMOVP_Fp32 , X86::CMOVP_F },
668  { X86::CMOVP_Fp64 , X86::CMOVP_F },
669  { X86::CMOVP_Fp80 , X86::CMOVP_F },
670  { X86::COM_FpIr32 , X86::COM_FIr },
671  { X86::COM_FpIr64 , X86::COM_FIr },
672  { X86::COM_FpIr80 , X86::COM_FIr },
673  { X86::COM_Fpr32 , X86::COM_FST0r },
674  { X86::COM_Fpr64 , X86::COM_FST0r },
675  { X86::COM_Fpr80 , X86::COM_FST0r },
676  { X86::DIVR_Fp32m , X86::DIVR_F32m },
677  { X86::DIVR_Fp64m , X86::DIVR_F64m },
678  { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
679  { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
680  { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
681  { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
682  { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
683  { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
684  { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
685  { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
686  { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
687  { X86::DIV_Fp32m , X86::DIV_F32m },
688  { X86::DIV_Fp64m , X86::DIV_F64m },
689  { X86::DIV_Fp64m32 , X86::DIV_F32m },
690  { X86::DIV_Fp80m32 , X86::DIV_F32m },
691  { X86::DIV_Fp80m64 , X86::DIV_F64m },
692  { X86::DIV_FpI16m32 , X86::DIV_FI16m },
693  { X86::DIV_FpI16m64 , X86::DIV_FI16m },
694  { X86::DIV_FpI16m80 , X86::DIV_FI16m },
695  { X86::DIV_FpI32m32 , X86::DIV_FI32m },
696  { X86::DIV_FpI32m64 , X86::DIV_FI32m },
697  { X86::DIV_FpI32m80 , X86::DIV_FI32m },
698  { X86::ILD_Fp16m32 , X86::ILD_F16m },
699  { X86::ILD_Fp16m64 , X86::ILD_F16m },
700  { X86::ILD_Fp16m80 , X86::ILD_F16m },
701  { X86::ILD_Fp32m32 , X86::ILD_F32m },
702  { X86::ILD_Fp32m64 , X86::ILD_F32m },
703  { X86::ILD_Fp32m80 , X86::ILD_F32m },
704  { X86::ILD_Fp64m32 , X86::ILD_F64m },
705  { X86::ILD_Fp64m64 , X86::ILD_F64m },
706  { X86::ILD_Fp64m80 , X86::ILD_F64m },
707  { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
708  { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
709  { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
710  { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
711  { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
712  { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
713  { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
714  { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
715  { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
716  { X86::IST_Fp16m32 , X86::IST_F16m },
717  { X86::IST_Fp16m64 , X86::IST_F16m },
718  { X86::IST_Fp16m80 , X86::IST_F16m },
719  { X86::IST_Fp32m32 , X86::IST_F32m },
720  { X86::IST_Fp32m64 , X86::IST_F32m },
721  { X86::IST_Fp32m80 , X86::IST_F32m },
722  { X86::IST_Fp64m32 , X86::IST_FP64m },
723  { X86::IST_Fp64m64 , X86::IST_FP64m },
724  { X86::IST_Fp64m80 , X86::IST_FP64m },
725  { X86::LD_Fp032 , X86::LD_F0 },
726  { X86::LD_Fp064 , X86::LD_F0 },
727  { X86::LD_Fp080 , X86::LD_F0 },
728  { X86::LD_Fp132 , X86::LD_F1 },
729  { X86::LD_Fp164 , X86::LD_F1 },
730  { X86::LD_Fp180 , X86::LD_F1 },
731  { X86::LD_Fp32m , X86::LD_F32m },
732  { X86::LD_Fp32m64 , X86::LD_F32m },
733  { X86::LD_Fp32m80 , X86::LD_F32m },
734  { X86::LD_Fp64m , X86::LD_F64m },
735  { X86::LD_Fp64m80 , X86::LD_F64m },
736  { X86::LD_Fp80m , X86::LD_F80m },
737  { X86::MUL_Fp32m , X86::MUL_F32m },
738  { X86::MUL_Fp64m , X86::MUL_F64m },
739  { X86::MUL_Fp64m32 , X86::MUL_F32m },
740  { X86::MUL_Fp80m32 , X86::MUL_F32m },
741  { X86::MUL_Fp80m64 , X86::MUL_F64m },
742  { X86::MUL_FpI16m32 , X86::MUL_FI16m },
743  { X86::MUL_FpI16m64 , X86::MUL_FI16m },
744  { X86::MUL_FpI16m80 , X86::MUL_FI16m },
745  { X86::MUL_FpI32m32 , X86::MUL_FI32m },
746  { X86::MUL_FpI32m64 , X86::MUL_FI32m },
747  { X86::MUL_FpI32m80 , X86::MUL_FI32m },
748  { X86::SQRT_Fp32 , X86::SQRT_F },
749  { X86::SQRT_Fp64 , X86::SQRT_F },
750  { X86::SQRT_Fp80 , X86::SQRT_F },
751  { X86::ST_Fp32m , X86::ST_F32m },
752  { X86::ST_Fp64m , X86::ST_F64m },
753  { X86::ST_Fp64m32 , X86::ST_F32m },
754  { X86::ST_Fp80m32 , X86::ST_F32m },
755  { X86::ST_Fp80m64 , X86::ST_F64m },
756  { X86::ST_FpP80m , X86::ST_FP80m },
757  { X86::SUBR_Fp32m , X86::SUBR_F32m },
758  { X86::SUBR_Fp64m , X86::SUBR_F64m },
759  { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
760  { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
761  { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
762  { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
763  { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
764  { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
765  { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
766  { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
767  { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
768  { X86::SUB_Fp32m , X86::SUB_F32m },
769  { X86::SUB_Fp64m , X86::SUB_F64m },
770  { X86::SUB_Fp64m32 , X86::SUB_F32m },
771  { X86::SUB_Fp80m32 , X86::SUB_F32m },
772  { X86::SUB_Fp80m64 , X86::SUB_F64m },
773  { X86::SUB_FpI16m32 , X86::SUB_FI16m },
774  { X86::SUB_FpI16m64 , X86::SUB_FI16m },
775  { X86::SUB_FpI16m80 , X86::SUB_FI16m },
776  { X86::SUB_FpI32m32 , X86::SUB_FI32m },
777  { X86::SUB_FpI32m64 , X86::SUB_FI32m },
778  { X86::SUB_FpI32m80 , X86::SUB_FI32m },
779  { X86::TST_Fp32 , X86::TST_F },
780  { X86::TST_Fp64 , X86::TST_F },
781  { X86::TST_Fp80 , X86::TST_F },
782  { X86::UCOM_FpIr32 , X86::UCOM_FIr },
783  { X86::UCOM_FpIr64 , X86::UCOM_FIr },
784  { X86::UCOM_FpIr80 , X86::UCOM_FIr },
785  { X86::UCOM_Fpr32 , X86::UCOM_Fr },
786  { X86::UCOM_Fpr64 , X86::UCOM_Fr },
787  { X86::UCOM_Fpr80 , X86::UCOM_Fr },
788  { X86::XAM_Fp32 , X86::XAM_F },
789  { X86::XAM_Fp64 , X86::XAM_F },
790  { X86::XAM_Fp80 , X86::XAM_F },
791 };
792 
793 static unsigned getConcreteOpcode(unsigned Opcode) {
795  int Opc = Lookup(OpcodeTable, Opcode);
796  assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
797  return Opc;
798 }
799 
800 //===----------------------------------------------------------------------===//
801 // Helper Methods
802 //===----------------------------------------------------------------------===//
803 
804 // PopTable - Sorted map of instructions to their popping version. The first
805 // element is an instruction, the second is the version which pops.
806 //
807 static const TableEntry PopTable[] = {
808  { X86::ADD_FrST0 , X86::ADD_FPrST0 },
809 
810  { X86::COMP_FST0r, X86::FCOMPP },
811  { X86::COM_FIr , X86::COM_FIPr },
812  { X86::COM_FST0r , X86::COMP_FST0r },
813 
814  { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
815  { X86::DIV_FrST0 , X86::DIV_FPrST0 },
816 
817  { X86::IST_F16m , X86::IST_FP16m },
818  { X86::IST_F32m , X86::IST_FP32m },
819 
820  { X86::MUL_FrST0 , X86::MUL_FPrST0 },
821 
822  { X86::ST_F32m , X86::ST_FP32m },
823  { X86::ST_F64m , X86::ST_FP64m },
824  { X86::ST_Frr , X86::ST_FPrr },
825 
826  { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
827  { X86::SUB_FrST0 , X86::SUB_FPrST0 },
828 
829  { X86::UCOM_FIr , X86::UCOM_FIPr },
830 
831  { X86::UCOM_FPr , X86::UCOM_FPPr },
832  { X86::UCOM_Fr , X86::UCOM_FPr },
833 };
834 
835 /// popStackAfter - Pop the current value off of the top of the FP stack after
836 /// the specified instruction. This attempts to be sneaky and combine the pop
837 /// into the instruction itself if possible. The iterator is left pointing to
838 /// the last instruction, be it a new pop instruction inserted, or the old
839 /// instruction if it was modified in place.
840 ///
841 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
842  MachineInstr &MI = *I;
843  const DebugLoc &dl = MI.getDebugLoc();
845 
846  popReg();
847 
848  // Check to see if there is a popping version of this instruction...
849  int Opcode = Lookup(PopTable, I->getOpcode());
850  if (Opcode != -1) {
851  I->setDesc(TII->get(Opcode));
852  if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
853  I->RemoveOperand(0);
854  MI.dropDebugNumber();
855  } else { // Insert an explicit pop
856  I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
857  }
858 }
859 
860 /// freeStackSlotAfter - Free the specified register from the register stack, so
861 /// that it is no longer in a register. If the register is currently at the top
862 /// of the stack, we just pop the current instruction, otherwise we store the
863 /// current top-of-stack into the specified slot, then pop the top of stack.
864 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
865  if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
866  popStackAfter(I);
867  return;
868  }
869 
870  // Otherwise, store the top of stack into the dead slot, killing the operand
871  // without having to add in an explicit xchg then pop.
872  //
873  I = freeStackSlotBefore(++I, FPRegNo);
874 }
875 
876 /// freeStackSlotBefore - Free the specified register without trying any
877 /// folding.
879 FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) {
880  unsigned STReg = getSTReg(FPRegNo);
881  unsigned OldSlot = getSlot(FPRegNo);
882  unsigned TopReg = Stack[StackTop-1];
883  Stack[OldSlot] = TopReg;
884  RegMap[TopReg] = OldSlot;
885  RegMap[FPRegNo] = ~0;
886  Stack[--StackTop] = ~0;
887  return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
888  .addReg(STReg)
889  .getInstr();
890 }
891 
892 /// adjustLiveRegs - Kill and revive registers such that exactly the FP
893 /// registers with a bit in Mask are live.
894 void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) {
895  unsigned Defs = Mask;
896  unsigned Kills = 0;
897  for (unsigned i = 0; i < StackTop; ++i) {
898  unsigned RegNo = Stack[i];
899  if (!(Defs & (1 << RegNo)))
900  // This register is live, but we don't want it.
901  Kills |= (1 << RegNo);
902  else
903  // We don't need to imp-def this live register.
904  Defs &= ~(1 << RegNo);
905  }
906  assert((Kills & Defs) == 0 && "Register needs killing and def'ing?");
907 
908  // Produce implicit-defs for free by using killed registers.
909  while (Kills && Defs) {
910  unsigned KReg = countTrailingZeros(Kills);
911  unsigned DReg = countTrailingZeros(Defs);
912  LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg
913  << "\n");
914  std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]);
915  std::swap(RegMap[KReg], RegMap[DReg]);
916  Kills &= ~(1 << KReg);
917  Defs &= ~(1 << DReg);
918  }
919 
920  // Kill registers by popping.
921  if (Kills && I != MBB->begin()) {
922  MachineBasicBlock::iterator I2 = std::prev(I);
923  while (StackTop) {
924  unsigned KReg = getStackEntry(0);
925  if (!(Kills & (1 << KReg)))
926  break;
927  LLVM_DEBUG(dbgs() << "Popping %fp" << KReg << "\n");
928  popStackAfter(I2);
929  Kills &= ~(1 << KReg);
930  }
931  }
932 
933  // Manually kill the rest.
934  while (Kills) {
935  unsigned KReg = countTrailingZeros(Kills);
936  LLVM_DEBUG(dbgs() << "Killing %fp" << KReg << "\n");
937  freeStackSlotBefore(I, KReg);
938  Kills &= ~(1 << KReg);
939  }
940 
941  // Load zeros for all the imp-defs.
942  while(Defs) {
943  unsigned DReg = countTrailingZeros(Defs);
944  LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n");
945  BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
946  pushReg(DReg);
947  Defs &= ~(1 << DReg);
948  }
949 
950  // Now we should have the correct registers live.
951  LLVM_DEBUG(dumpStack());
952  assert(StackTop == countPopulation(Mask) && "Live count mismatch");
953 }
954 
955 /// shuffleStackTop - emit fxch instructions before I to shuffle the top
956 /// FixCount entries into the order given by FixStack.
957 /// FIXME: Is there a better algorithm than insertion sort?
958 void FPS::shuffleStackTop(const unsigned char *FixStack,
959  unsigned FixCount,
961  // Move items into place, starting from the desired stack bottom.
962  while (FixCount--) {
963  // Old register at position FixCount.
964  unsigned OldReg = getStackEntry(FixCount);
965  // Desired register at position FixCount.
966  unsigned Reg = FixStack[FixCount];
967  if (Reg == OldReg)
968  continue;
969  // (Reg st0) (OldReg st0) = (Reg OldReg st0)
970  moveToTop(Reg, I);
971  if (FixCount > 0)
972  moveToTop(OldReg, I);
973  }
974  LLVM_DEBUG(dumpStack());
975 }
976 
977 
978 //===----------------------------------------------------------------------===//
979 // Instruction transformation implementation
980 //===----------------------------------------------------------------------===//
981 
982 void FPS::handleCall(MachineBasicBlock::iterator &I) {
983  MachineInstr &MI = *I;
984  unsigned STReturns = 0;
985 
986  bool ClobbersFPStack = false;
987  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
988  MachineOperand &Op = MI.getOperand(i);
989  // Check if this call clobbers the FP stack.
990  // is sufficient.
991  if (Op.isRegMask()) {
992  bool ClobbersFP0 = Op.clobbersPhysReg(X86::FP0);
993 #ifndef NDEBUG
994  static_assert(X86::FP7 - X86::FP0 == 7, "sequential FP regnumbers");
995  for (unsigned i = 1; i != 8; ++i)
996  assert(Op.clobbersPhysReg(X86::FP0 + i) == ClobbersFP0 &&
997  "Inconsistent FP register clobber");
998 #endif
999 
1000  if (ClobbersFP0)
1001  ClobbersFPStack = true;
1002  }
1003 
1004  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1005  continue;
1006 
1007  assert(Op.isImplicit() && "Expected implicit def/use");
1008 
1009  if (Op.isDef())
1010  STReturns |= 1 << getFPReg(Op);
1011 
1012  // Remove the operand so that later passes don't see it.
1013  MI.RemoveOperand(i);
1014  --i;
1015  --e;
1016  }
1017 
1018  // Most calls should have a regmask that clobbers the FP registers. If it
1019  // isn't present then the register allocator didn't spill the FP registers
1020  // so they are still on the stack.
1021  assert((ClobbersFPStack || STReturns == 0) &&
1022  "ST returns without FP stack clobber");
1023  if (!ClobbersFPStack)
1024  return;
1025 
1026  unsigned N = countTrailingOnes(STReturns);
1027 
1028  // FP registers used for function return must be consecutive starting at
1029  // FP0
1030  assert(STReturns == 0 || (isMask_32(STReturns) && N <= 2));
1031 
1032  // Reset the FP Stack - It is required because of possible leftovers from
1033  // passed arguments. The caller should assume that the FP stack is
1034  // returned empty (unless the callee returns values on FP stack).
1035  while (StackTop > 0)
1036  popReg();
1037 
1038  for (unsigned I = 0; I < N; ++I)
1039  pushReg(N - I - 1);
1040 
1041  // If this call has been modified, drop all variable values defined by it.
1042  // We can't track them once they've been stackified.
1043  if (STReturns)
1044  I->dropDebugNumber();
1045 }
1046 
1047 /// If RET has an FP register use operand, pass the first one in ST(0) and
1048 /// the second one in ST(1).
1049 void FPS::handleReturn(MachineBasicBlock::iterator &I) {
1050  MachineInstr &MI = *I;
1051 
1052  // Find the register operands.
1053  unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1054  unsigned LiveMask = 0;
1055 
1056  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1057  MachineOperand &Op = MI.getOperand(i);
1058  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1059  continue;
1060  // FP Register uses must be kills unless there are two uses of the same
1061  // register, in which case only one will be a kill.
1062  assert(Op.isUse() &&
1063  (Op.isKill() || // Marked kill.
1064  getFPReg(Op) == FirstFPRegOp || // Second instance.
1065  MI.killsRegister(Op.getReg())) && // Later use is marked kill.
1066  "Ret only defs operands, and values aren't live beyond it");
1067 
1068  if (FirstFPRegOp == ~0U)
1069  FirstFPRegOp = getFPReg(Op);
1070  else {
1071  assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1072  SecondFPRegOp = getFPReg(Op);
1073  }
1074  LiveMask |= (1 << getFPReg(Op));
1075 
1076  // Remove the operand so that later passes don't see it.
1077  MI.RemoveOperand(i);
1078  --i;
1079  --e;
1080  }
1081 
1082  // We may have been carrying spurious live-ins, so make sure only the
1083  // returned registers are left live.
1084  adjustLiveRegs(LiveMask, MI);
1085  if (!LiveMask) return; // Quick check to see if any are possible.
1086 
1087  // There are only four possibilities here:
1088  // 1) we are returning a single FP value. In this case, it has to be in
1089  // ST(0) already, so just declare success by removing the value from the
1090  // FP Stack.
1091  if (SecondFPRegOp == ~0U) {
1092  // Assert that the top of stack contains the right FP register.
1093  assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1094  "Top of stack not the right register for RET!");
1095 
1096  // Ok, everything is good, mark the value as not being on the stack
1097  // anymore so that our assertion about the stack being empty at end of
1098  // block doesn't fire.
1099  StackTop = 0;
1100  return;
1101  }
1102 
1103  // Otherwise, we are returning two values:
1104  // 2) If returning the same value for both, we only have one thing in the FP
1105  // stack. Consider: RET FP1, FP1
1106  if (StackTop == 1) {
1107  assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1108  "Stack misconfiguration for RET!");
1109 
1110  // Duplicate the TOS so that we return it twice. Just pick some other FPx
1111  // register to hold it.
1112  unsigned NewReg = ScratchFPReg;
1113  duplicateToTop(FirstFPRegOp, NewReg, MI);
1114  FirstFPRegOp = NewReg;
1115  }
1116 
1117  /// Okay we know we have two different FPx operands now:
1118  assert(StackTop == 2 && "Must have two values live!");
1119 
1120  /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1121  /// in ST(1). In this case, emit an fxch.
1122  if (getStackEntry(0) == SecondFPRegOp) {
1123  assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1124  moveToTop(FirstFPRegOp, MI);
1125  }
1126 
1127  /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1128  /// ST(1). Just remove both from our understanding of the stack and return.
1129  assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1130  assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1131  StackTop = 0;
1132 }
1133 
1134 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
1135 ///
1136 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
1137  MachineInstr &MI = *I;
1138  unsigned DestReg = getFPReg(MI.getOperand(0));
1139 
1140  // Change from the pseudo instruction to the concrete instruction.
1141  MI.RemoveOperand(0); // Remove the explicit ST(0) operand
1142  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1143  MI.addOperand(
1144  MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1145 
1146  // Result gets pushed on the stack.
1147  pushReg(DestReg);
1148 
1149  MI.dropDebugNumber();
1150 }
1151 
1152 /// handleOneArgFP - fst <mem>, ST(0)
1153 ///
1154 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
1155  MachineInstr &MI = *I;
1156  unsigned NumOps = MI.getDesc().getNumOperands();
1157  assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
1158  "Can only handle fst* & ftst instructions!");
1159 
1160  // Is this the last use of the source register?
1161  unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1162  bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1163 
1164  // FISTP64m is strange because there isn't a non-popping versions.
1165  // If we have one _and_ we don't want to pop the operand, duplicate the value
1166  // on the stack instead of moving it. This ensure that popping the value is
1167  // always ok.
1168  // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
1169  //
1170  if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1171  MI.getOpcode() == X86::ISTT_Fp16m32 ||
1172  MI.getOpcode() == X86::ISTT_Fp32m32 ||
1173  MI.getOpcode() == X86::ISTT_Fp64m32 ||
1174  MI.getOpcode() == X86::IST_Fp64m64 ||
1175  MI.getOpcode() == X86::ISTT_Fp16m64 ||
1176  MI.getOpcode() == X86::ISTT_Fp32m64 ||
1177  MI.getOpcode() == X86::ISTT_Fp64m64 ||
1178  MI.getOpcode() == X86::IST_Fp64m80 ||
1179  MI.getOpcode() == X86::ISTT_Fp16m80 ||
1180  MI.getOpcode() == X86::ISTT_Fp32m80 ||
1181  MI.getOpcode() == X86::ISTT_Fp64m80 ||
1182  MI.getOpcode() == X86::ST_FpP80m)) {
1183  duplicateToTop(Reg, ScratchFPReg, I);
1184  } else {
1185  moveToTop(Reg, I); // Move to the top of the stack...
1186  }
1187 
1188  // Convert from the pseudo instruction to the concrete instruction.
1189  MI.RemoveOperand(NumOps - 1); // Remove explicit ST(0) operand
1190  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1191  MI.addOperand(
1192  MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1193 
1194  if (MI.getOpcode() == X86::IST_FP64m || MI.getOpcode() == X86::ISTT_FP16m ||
1195  MI.getOpcode() == X86::ISTT_FP32m || MI.getOpcode() == X86::ISTT_FP64m ||
1196  MI.getOpcode() == X86::ST_FP80m) {
1197  if (StackTop == 0)
1198  report_fatal_error("Stack empty??");
1199  --StackTop;
1200  } else if (KillsSrc) { // Last use of operand?
1201  popStackAfter(I);
1202  }
1203 
1204  MI.dropDebugNumber();
1205 }
1206 
1207 
1208 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
1209 /// replace the value with a newly computed value. These instructions may have
1210 /// non-fp operands after their FP operands.
1211 ///
1212 /// Examples:
1213 /// R1 = fchs R2
1214 /// R1 = fadd R2, [mem]
1215 ///
1216 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
1217  MachineInstr &MI = *I;
1218 #ifndef NDEBUG
1219  unsigned NumOps = MI.getDesc().getNumOperands();
1220  assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1221 #endif
1222 
1223  // Is this the last use of the source register?
1224  unsigned Reg = getFPReg(MI.getOperand(1));
1225  bool KillsSrc = MI.killsRegister(X86::FP0 + Reg);
1226 
1227  if (KillsSrc) {
1228  // If this is the last use of the source register, just make sure it's on
1229  // the top of the stack.
1230  moveToTop(Reg, I);
1231  if (StackTop == 0)
1232  report_fatal_error("Stack cannot be empty!");
1233  --StackTop;
1234  pushReg(getFPReg(MI.getOperand(0)));
1235  } else {
1236  // If this is not the last use of the source register, _copy_ it to the top
1237  // of the stack.
1238  duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1239  }
1240 
1241  // Change from the pseudo instruction to the concrete instruction.
1242  MI.RemoveOperand(1); // Drop the source operand.
1243  MI.RemoveOperand(0); // Drop the destination operand.
1244  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1245  MI.dropDebugNumber();
1246 }
1247 
1248 
1249 //===----------------------------------------------------------------------===//
1250 // Define tables of various ways to map pseudo instructions
1251 //
1252 
1253 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
1254 static const TableEntry ForwardST0Table[] = {
1255  { X86::ADD_Fp32 , X86::ADD_FST0r },
1256  { X86::ADD_Fp64 , X86::ADD_FST0r },
1257  { X86::ADD_Fp80 , X86::ADD_FST0r },
1258  { X86::DIV_Fp32 , X86::DIV_FST0r },
1259  { X86::DIV_Fp64 , X86::DIV_FST0r },
1260  { X86::DIV_Fp80 , X86::DIV_FST0r },
1261  { X86::MUL_Fp32 , X86::MUL_FST0r },
1262  { X86::MUL_Fp64 , X86::MUL_FST0r },
1263  { X86::MUL_Fp80 , X86::MUL_FST0r },
1264  { X86::SUB_Fp32 , X86::SUB_FST0r },
1265  { X86::SUB_Fp64 , X86::SUB_FST0r },
1266  { X86::SUB_Fp80 , X86::SUB_FST0r },
1267 };
1268 
1269 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
1270 static const TableEntry ReverseST0Table[] = {
1271  { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
1272  { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
1273  { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
1274  { X86::DIV_Fp32 , X86::DIVR_FST0r },
1275  { X86::DIV_Fp64 , X86::DIVR_FST0r },
1276  { X86::DIV_Fp80 , X86::DIVR_FST0r },
1277  { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
1278  { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
1279  { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
1280  { X86::SUB_Fp32 , X86::SUBR_FST0r },
1281  { X86::SUB_Fp64 , X86::SUBR_FST0r },
1282  { X86::SUB_Fp80 , X86::SUBR_FST0r },
1283 };
1284 
1285 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
1286 static const TableEntry ForwardSTiTable[] = {
1287  { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
1288  { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
1289  { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
1290  { X86::DIV_Fp32 , X86::DIVR_FrST0 },
1291  { X86::DIV_Fp64 , X86::DIVR_FrST0 },
1292  { X86::DIV_Fp80 , X86::DIVR_FrST0 },
1293  { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
1294  { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
1295  { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
1296  { X86::SUB_Fp32 , X86::SUBR_FrST0 },
1297  { X86::SUB_Fp64 , X86::SUBR_FrST0 },
1298  { X86::SUB_Fp80 , X86::SUBR_FrST0 },
1299 };
1300 
1301 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
1302 static const TableEntry ReverseSTiTable[] = {
1303  { X86::ADD_Fp32 , X86::ADD_FrST0 },
1304  { X86::ADD_Fp64 , X86::ADD_FrST0 },
1305  { X86::ADD_Fp80 , X86::ADD_FrST0 },
1306  { X86::DIV_Fp32 , X86::DIV_FrST0 },
1307  { X86::DIV_Fp64 , X86::DIV_FrST0 },
1308  { X86::DIV_Fp80 , X86::DIV_FrST0 },
1309  { X86::MUL_Fp32 , X86::MUL_FrST0 },
1310  { X86::MUL_Fp64 , X86::MUL_FrST0 },
1311  { X86::MUL_Fp80 , X86::MUL_FrST0 },
1312  { X86::SUB_Fp32 , X86::SUB_FrST0 },
1313  { X86::SUB_Fp64 , X86::SUB_FrST0 },
1314  { X86::SUB_Fp80 , X86::SUB_FrST0 },
1315 };
1316 
1317 
1318 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
1319 /// instructions which need to be simplified and possibly transformed.
1320 ///
1321 /// Result: ST(0) = fsub ST(0), ST(i)
1322 /// ST(i) = fsub ST(0), ST(i)
1323 /// ST(0) = fsubr ST(0), ST(i)
1324 /// ST(i) = fsubr ST(0), ST(i)
1325 ///
1326 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
1329  MachineInstr &MI = *I;
1330 
1331  unsigned NumOperands = MI.getDesc().getNumOperands();
1332  assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
1333  unsigned Dest = getFPReg(MI.getOperand(0));
1334  unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1335  unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1336  bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1337  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1338  const DebugLoc &dl = MI.getDebugLoc();
1339 
1340  unsigned TOS = getStackEntry(0);
1341 
1342  // One of our operands must be on the top of the stack. If neither is yet, we
1343  // need to move one.
1344  if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
1345  // We can choose to move either operand to the top of the stack. If one of
1346  // the operands is killed by this instruction, we want that one so that we
1347  // can update right on top of the old version.
1348  if (KillsOp0) {
1349  moveToTop(Op0, I); // Move dead operand to TOS.
1350  TOS = Op0;
1351  } else if (KillsOp1) {
1352  moveToTop(Op1, I);
1353  TOS = Op1;
1354  } else {
1355  // All of the operands are live after this instruction executes, so we
1356  // cannot update on top of any operand. Because of this, we must
1357  // duplicate one of the stack elements to the top. It doesn't matter
1358  // which one we pick.
1359  //
1360  duplicateToTop(Op0, Dest, I);
1361  Op0 = TOS = Dest;
1362  KillsOp0 = true;
1363  }
1364  } else if (!KillsOp0 && !KillsOp1) {
1365  // If we DO have one of our operands at the top of the stack, but we don't
1366  // have a dead operand, we must duplicate one of the operands to a new slot
1367  // on the stack.
1368  duplicateToTop(Op0, Dest, I);
1369  Op0 = TOS = Dest;
1370  KillsOp0 = true;
1371  }
1372 
1373  // Now we know that one of our operands is on the top of the stack, and at
1374  // least one of our operands is killed by this instruction.
1375  assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
1376  "Stack conditions not set up right!");
1377 
1378  // We decide which form to use based on what is on the top of the stack, and
1379  // which operand is killed by this instruction.
1380  ArrayRef<TableEntry> InstTable;
1381  bool isForward = TOS == Op0;
1382  bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
1383  if (updateST0) {
1384  if (isForward)
1385  InstTable = ForwardST0Table;
1386  else
1387  InstTable = ReverseST0Table;
1388  } else {
1389  if (isForward)
1390  InstTable = ForwardSTiTable;
1391  else
1392  InstTable = ReverseSTiTable;
1393  }
1394 
1395  int Opcode = Lookup(InstTable, MI.getOpcode());
1396  assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
1397 
1398  // NotTOS - The register which is not on the top of stack...
1399  unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
1400 
1401  // Replace the old instruction with a new instruction
1402  MBB->remove(&*I++);
1403  I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1404 
1405  if (!MI.mayRaiseFPException())
1406  I->setFlag(MachineInstr::MIFlag::NoFPExcept);
1407 
1408  // If both operands are killed, pop one off of the stack in addition to
1409  // overwriting the other one.
1410  if (KillsOp0 && KillsOp1 && Op0 != Op1) {
1411  assert(!updateST0 && "Should have updated other operand!");
1412  popStackAfter(I); // Pop the top of stack
1413  }
1414 
1415  // Update stack information so that we know the destination register is now on
1416  // the stack.
1417  unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
1418  assert(UpdatedSlot < StackTop && Dest < 7);
1419  Stack[UpdatedSlot] = Dest;
1420  RegMap[Dest] = UpdatedSlot;
1421  MBB->getParent()->DeleteMachineInstr(&MI); // Remove the old instruction
1422 }
1423 
1424 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
1425 /// register arguments and no explicit destinations.
1426 ///
1427 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
1428  MachineInstr &MI = *I;
1429 
1430  unsigned NumOperands = MI.getDesc().getNumOperands();
1431  assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
1432  unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1433  unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1434  bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0);
1435  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1436 
1437  // Make sure the first operand is on the top of stack, the other one can be
1438  // anywhere.
1439  moveToTop(Op0, I);
1440 
1441  // Change from the pseudo instruction to the concrete instruction.
1442  MI.getOperand(0).setReg(getSTReg(Op1));
1443  MI.RemoveOperand(1);
1444  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1445  MI.dropDebugNumber();
1446 
1447  // If any of the operands are killed by this instruction, free them.
1448  if (KillsOp0) freeStackSlotAfter(I, Op0);
1449  if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
1450 }
1451 
1452 /// handleCondMovFP - Handle two address conditional move instructions. These
1453 /// instructions move a st(i) register to st(0) iff a condition is true. These
1454 /// instructions require that the first operand is at the top of the stack, but
1455 /// otherwise don't modify the stack at all.
1456 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
1457  MachineInstr &MI = *I;
1458 
1459  unsigned Op0 = getFPReg(MI.getOperand(0));
1460  unsigned Op1 = getFPReg(MI.getOperand(2));
1461  bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1);
1462 
1463  // The first operand *must* be on the top of the stack.
1464  moveToTop(Op0, I);
1465 
1466  // Change the second operand to the stack register that the operand is in.
1467  // Change from the pseudo instruction to the concrete instruction.
1468  MI.RemoveOperand(0);
1469  MI.RemoveOperand(1);
1470  MI.getOperand(0).setReg(getSTReg(Op1));
1471  MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1472  MI.dropDebugNumber();
1473 
1474  // If we kill the second operand, make sure to pop it from the stack.
1475  if (Op0 != Op1 && KillsOp1) {
1476  // Get this value off of the register stack.
1477  freeStackSlotAfter(I, Op1);
1478  }
1479 }
1480 
1481 
1482 /// handleSpecialFP - Handle special instructions which behave unlike other
1483 /// floating point instructions. This is primarily intended for use by pseudo
1484 /// instructions.
1485 ///
1486 void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
1487  MachineInstr &MI = *Inst;
1488 
1489  if (MI.isCall()) {
1490  handleCall(Inst);
1491  return;
1492  }
1493 
1494  if (MI.isReturn()) {
1495  handleReturn(Inst);
1496  return;
1497  }
1498 
1499  switch (MI.getOpcode()) {
1500  default: llvm_unreachable("Unknown SpecialFP instruction!");
1501  case TargetOpcode::COPY: {
1502  // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
1503  const MachineOperand &MO1 = MI.getOperand(1);
1504  const MachineOperand &MO0 = MI.getOperand(0);
1505  bool KillsSrc = MI.killsRegister(MO1.getReg());
1506 
1507  // FP <- FP copy.
1508  unsigned DstFP = getFPReg(MO0);
1509  unsigned SrcFP = getFPReg(MO1);
1510  assert(isLive(SrcFP) && "Cannot copy dead register");
1511  if (KillsSrc) {
1512  // If the input operand is killed, we can just change the owner of the
1513  // incoming stack slot into the result.
1514  unsigned Slot = getSlot(SrcFP);
1515  Stack[Slot] = DstFP;
1516  RegMap[DstFP] = Slot;
1517  } else {
1518  // For COPY we just duplicate the specified value to a new stack slot.
1519  // This could be made better, but would require substantial changes.
1520  duplicateToTop(SrcFP, DstFP, Inst);
1521  }
1522  break;
1523  }
1524 
1525  case TargetOpcode::IMPLICIT_DEF: {
1526  // All FP registers must be explicitly defined, so load a 0 instead.
1527  unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1528  LLVM_DEBUG(dbgs() << "Emitting LD_F0 for implicit FP" << Reg << '\n');
1529  BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1530  pushReg(Reg);
1531  break;
1532  }
1533 
1536  // The inline asm MachineInstr currently only *uses* FP registers for the
1537  // 'f' constraint. These should be turned into the current ST(x) register
1538  // in the machine instr.
1539  //
1540  // There are special rules for x87 inline assembly. The compiler must know
1541  // exactly how many registers are popped and pushed implicitly by the asm.
1542  // Otherwise it is not possible to restore the stack state after the inline
1543  // asm.
1544  //
1545  // There are 3 kinds of input operands:
1546  //
1547  // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
1548  // popped input operand must be in a fixed stack slot, and it is either
1549  // tied to an output operand, or in the clobber list. The MI has ST use
1550  // and def operands for these inputs.
1551  //
1552  // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
1553  // preserved by the inline asm. The fixed stack slots must be STn-STm
1554  // following the popped inputs. A fixed input operand cannot be tied to
1555  // an output or appear in the clobber list. The MI has ST use operands
1556  // and no defs for these inputs.
1557  //
1558  // 3. Preserved inputs. These inputs use the "f" constraint which is
1559  // represented as an FP register. The inline asm won't change these
1560  // stack slots.
1561  //
1562  // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
1563  // registers do not count as output operands. The inline asm changes the
1564  // stack as if it popped all the popped inputs and then pushed all the
1565  // output operands.
1566 
1567  // Scan the assembly for ST registers used, defined and clobbered. We can
1568  // only tell clobbers from defs by looking at the asm descriptor.
1569  unsigned STUses = 0, STDefs = 0, STClobbers = 0;
1570  unsigned NumOps = 0;
1571  SmallSet<unsigned, 1> FRegIdx;
1572  unsigned RCID;
1573 
1574  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI.getNumOperands();
1575  i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1576  unsigned Flags = MI.getOperand(i).getImm();
1577 
1578  NumOps = InlineAsm::getNumOperandRegisters(Flags);
1579  if (NumOps != 1)
1580  continue;
1581  const MachineOperand &MO = MI.getOperand(i + 1);
1582  if (!MO.isReg())
1583  continue;
1584  unsigned STReg = MO.getReg() - X86::FP0;
1585  if (STReg >= 8)
1586  continue;
1587 
1588  // If the flag has a register class constraint, this must be an operand
1589  // with constraint "f". Record its index and continue.
1590  if (InlineAsm::hasRegClassConstraint(Flags, RCID)) {
1591  FRegIdx.insert(i + 1);
1592  continue;
1593  }
1594 
1595  switch (InlineAsm::getKind(Flags)) {
1597  STUses |= (1u << STReg);
1598  break;
1601  STDefs |= (1u << STReg);
1602  break;
1604  STClobbers |= (1u << STReg);
1605  break;
1606  default:
1607  break;
1608  }
1609  }
1610 
1611  if (STUses && !isMask_32(STUses))
1612  MI.emitError("fixed input regs must be last on the x87 stack");
1613  unsigned NumSTUses = countTrailingOnes(STUses);
1614 
1615  // Defs must be contiguous from the stack top. ST0-STn.
1616  if (STDefs && !isMask_32(STDefs)) {
1617  MI.emitError("output regs must be last on the x87 stack");
1618  STDefs = NextPowerOf2(STDefs) - 1;
1619  }
1620  unsigned NumSTDefs = countTrailingOnes(STDefs);
1621 
1622  // So must the clobbered stack slots. ST0-STm, m >= n.
1623  if (STClobbers && !isMask_32(STDefs | STClobbers))
1624  MI.emitError("clobbers must be last on the x87 stack");
1625 
1626  // Popped inputs are the ones that are also clobbered or defined.
1627  unsigned STPopped = STUses & (STDefs | STClobbers);
1628  if (STPopped && !isMask_32(STPopped))
1629  MI.emitError("implicitly popped regs must be last on the x87 stack");
1630  unsigned NumSTPopped = countTrailingOnes(STPopped);
1631 
1632  LLVM_DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
1633  << NumSTPopped << ", and defines " << NumSTDefs
1634  << " regs.\n");
1635 
1636 #ifndef NDEBUG
1637  // If any input operand uses constraint "f", all output register
1638  // constraints must be early-clobber defs.
1639  for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I)
1640  if (FRegIdx.count(I)) {
1641  assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1642  "Operands with constraint \"f\" cannot overlap with defs");
1643  }
1644 #endif
1645 
1646  // Collect all FP registers (register operands with constraints "t", "u",
1647  // and "f") to kill afer the instruction.
1648  unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
1649  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1650  MachineOperand &Op = MI.getOperand(i);
1651  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1652  continue;
1653  unsigned FPReg = getFPReg(Op);
1654 
1655  // If we kill this operand, make sure to pop it from the stack after the
1656  // asm. We just remember it for now, and pop them all off at the end in
1657  // a batch.
1658  if (Op.isUse() && Op.isKill())
1659  FPKills |= 1U << FPReg;
1660  }
1661 
1662  // Do not include registers that are implicitly popped by defs/clobbers.
1663  FPKills &= ~(STDefs | STClobbers);
1664 
1665  // Now we can rearrange the live registers to match what was requested.
1666  unsigned char STUsesArray[8];
1667 
1668  for (unsigned I = 0; I < NumSTUses; ++I)
1669  STUsesArray[I] = I;
1670 
1671  shuffleStackTop(STUsesArray, NumSTUses, Inst);
1672  LLVM_DEBUG({
1673  dbgs() << "Before asm: ";
1674  dumpStack();
1675  });
1676 
1677  // With the stack layout fixed, rewrite the FP registers.
1678  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1679  MachineOperand &Op = MI.getOperand(i);
1680  if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1681  continue;
1682 
1683  unsigned FPReg = getFPReg(Op);
1684 
1685  if (FRegIdx.count(i))
1686  // Operand with constraint "f".
1687  Op.setReg(getSTReg(FPReg));
1688  else
1689  // Operand with a single register class constraint ("t" or "u").
1690  Op.setReg(X86::ST0 + FPReg);
1691  }
1692 
1693  // Simulate the inline asm popping its inputs and pushing its outputs.
1694  StackTop -= NumSTPopped;
1695 
1696  for (unsigned i = 0; i < NumSTDefs; ++i)
1697  pushReg(NumSTDefs - i - 1);
1698 
1699  // If this asm kills any FP registers (is the last use of them) we must
1700  // explicitly emit pop instructions for them. Do this now after the asm has
1701  // executed so that the ST(x) numbers are not off (which would happen if we
1702  // did this inline with operand rewriting).
1703  //
1704  // Note: this might be a non-optimal pop sequence. We might be able to do
1705  // better by trying to pop in stack order or something.
1706  while (FPKills) {
1707  unsigned FPReg = countTrailingZeros(FPKills);
1708  if (isLive(FPReg))
1709  freeStackSlotAfter(Inst, FPReg);
1710  FPKills &= ~(1U << FPReg);
1711  }
1712 
1713  // Don't delete the inline asm!
1714  return;
1715  }
1716  }
1717 
1718  Inst = MBB->erase(Inst); // Remove the pseudo instruction
1719 
1720  // We want to leave I pointing to the previous instruction, but what if we
1721  // just erased the first instruction?
1722  if (Inst == MBB->begin()) {
1723  LLVM_DEBUG(dbgs() << "Inserting dummy KILL\n");
1724  Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
1725  } else
1726  --Inst;
1727 }
1728 
1729 void FPS::setKillFlags(MachineBasicBlock &MBB) const {
1730  const TargetRegisterInfo &TRI =
1732  LivePhysRegs LPR(TRI);
1733 
1734  LPR.addLiveOuts(MBB);
1735 
1737  I != E; ++I) {
1738  if (I->isDebugInstr())
1739  continue;
1740 
1741  std::bitset<8> Defs;
1743  MachineInstr &MI = *I;
1744 
1745  for (auto &MO : I->operands()) {
1746  if (!MO.isReg())
1747  continue;
1748 
1749  unsigned Reg = MO.getReg() - X86::FP0;
1750 
1751  if (Reg >= 8)
1752  continue;
1753 
1754  if (MO.isDef()) {
1755  Defs.set(Reg);
1756  if (!LPR.contains(MO.getReg()))
1757  MO.setIsDead();
1758  } else
1759  Uses.push_back(&MO);
1760  }
1761 
1762  for (auto *MO : Uses)
1763  if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
1764  MO->setIsKill();
1765 
1766  LPR.stepBackward(MI);
1767  }
1768 }
i
i
Definition: README.txt:29
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:683
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(FPS, DEBUG_TYPE, "X86 FP Stackifier", false, false) INITIALIZE_PASS_END(FPS
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::X86II::OneArgFPRW
@ OneArgFPRW
Definition: X86BaseInfo.h:869
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::InlineAsm::Kind_RegDefEarlyClobber
@ Kind_RegDefEarlyClobber
Definition: InlineAsm.h:235
llvm::X86II::CondMovFP
@ CondMovFP
Definition: X86BaseInfo.h:881
llvm::lower_bound
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1661
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::MachineOperand::setIsKill
void setIsKill(bool Val=true)
Definition: MachineOperand.h:500
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
InlineAsm.h
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
llvm::InlineAsm::Kind_RegUse
@ Kind_RegUse
Definition: InlineAsm.h:233
ErrorHandling.h
llvm::X86II::OneArgFP
@ OneArgFP
Definition: X86BaseInfo.h:864
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
to
Should compile to
Definition: README.txt:449
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MachineBasicBlock::livein_iterator
LiveInVector::const_iterator livein_iterator
Definition: MachineBasicBlock.h:398
TargetInstrInfo.h
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::M68kBeads::DReg
@ DReg
Definition: M68kBaseInfo.h:61
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
STLExtras.h
llvm::ARM::PredBlockMask::TE
@ TE
LLVM_ATTRIBUTE_UNUSED
#define LLVM_ATTRIBUTE_UNUSED
Definition: Compiler.h:188
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::InlineAsm::Kind_Clobber
@ Kind_Clobber
Definition: InlineAsm.h:236
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
ReverseST0Table
static const TableEntry ReverseST0Table[]
Definition: X86FloatingPoint.cpp:1270
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
DepthFirstIterator.h
MachineRegisterInfo.h
Uses
SmallPtrSet< MachineInstr *, 2 > Uses
Definition: ARMLowOverheadLoops.cpp:589
llvm::EdgeBundles
Definition: EdgeBundles.h:24
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:980
llvm::MachineBasicBlock::dump
void dump() const
Definition: MachineBasicBlock.cpp:295
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1304
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:824
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
X86.h
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
TargetMachine.h
llvm::MachineBasicBlock::remove
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
Definition: MachineBasicBlock.h:930
llvm::createX86FloatingPointStackifierPass
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Definition: X86FloatingPoint.cpp:311
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineFunction::DeleteMachineInstr
void DeleteMachineInstr(MachineInstr *MI)
DeleteMachineInstr - Delete the given MachineInstr.
Definition: MachineFunction.cpp:394
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineFunction::size
unsigned size() const
Definition: MachineFunction.h:822
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::depth_first_ext
iterator_range< df_ext_iterator< T, SetTy > > depth_first_ext(const T &G, SetTy &S)
Definition: DepthFirstIterator.h:251
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:173
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:278
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::SmallVectorImpl::resize
void resize(size_type N)
Definition: SmallVector.h:606
SmallPtrSet.h
llvm::EdgeBundles::getNumBundles
unsigned getNumBundles() const
getNumBundles - Return the total number of bundles in the CFG.
Definition: EdgeBundles.h:44
EdgeBundles.h
llvm::InlineAsm::getKind
static unsigned getKind(unsigned Flags)
Definition: InlineAsm.h:328
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
ASSERT_SORTED
#define ASSERT_SORTED(TABLE)
Definition: X86FloatingPoint.cpp:609
llvm::MachineFunctionProperties::Property::NoVRegs
@ NoVRegs
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:44
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
getConcreteOpcode
static unsigned getConcreteOpcode(unsigned Opcode)
Definition: X86FloatingPoint.cpp:793
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::operator<
bool operator<(int64_t V1, const APSInt &V2)
Definition: APSInt.h:338
OpcodeTable
static const TableEntry OpcodeTable[]
Definition: X86FloatingPoint.cpp:628
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::countTrailingOnes
unsigned countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
Definition: MathExtras.h:525
DEBUG_TYPE
#define DEBUG_TYPE
Definition: X86FloatingPoint.cpp:52
MachineFunctionPass.h
llvm::pdb::PDB_MemoryType::Stack
@ Stack
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:220
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineBasicBlock::livein_end
livein_iterator livein_end() const
Definition: MachineBasicBlock.h:410
llvm::df_iterator_default_set::insert
std::pair< iterator, bool > insert(NodeRef N)
Definition: DepthFirstIterator.h:73
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::isMask_32
constexpr bool isMask_32(uint32_t Value)
Return true if the argument is a non-empty sequence of ones starting at the least significant bit wit...
Definition: MathExtras.h:467
llvm::X86II::TwoArgFP
@ TwoArgFP
Definition: X86BaseInfo.h:874
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::df_iterator_default_set
Definition: DepthFirstIterator.h:69
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:347
getDebugLoc
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
Definition: MachineInstrBundle.cpp:109
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::X86II::NotFP
@ NotFP
Definition: X86BaseInfo.h:858
llvm::MachineBasicBlock::getNumber
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
Definition: MachineBasicBlock.h:1056
llvm::X86II::SpecialFP
@ SpecialFP
Definition: X86BaseInfo.h:884
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm::InlineAsm::Kind_RegDef
@ Kind_RegDef
Definition: InlineAsm.h:234
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineBasicBlock::removeLiveIn
void removeLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Remove the specified register from the live in set.
Definition: MachineBasicBlock.cpp:562
TargetSubtargetInfo.h
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
Stackifier
X86 FP Stackifier
Definition: X86FloatingPoint.cpp:308
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
ReverseSTiTable
static const TableEntry ReverseSTiTable[]
Definition: X86FloatingPoint.cpp:1302
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SmallPtrSetImplBase::size
size_type size() const
Definition: SmallPtrSet.h:92
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
ForwardST0Table
static const TableEntry ForwardST0Table[]
Definition: X86FloatingPoint.cpp:1254
llvm::X86II::CompareFP
@ CompareFP
Definition: X86BaseInfo.h:878
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:354
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:983
llvm::pdb::PDB_LocType::Slot
@ Slot
llvm::MachineBasicBlock::livein_begin
livein_iterator livein_begin() const
Definition: MachineBasicBlock.cpp:1605
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
Lookup
static int Lookup(ArrayRef< TableEntry > Table, unsigned Opcode)
Definition: X86FloatingPoint.cpp:599
llvm::X86II::FPTypeMask
@ FPTypeMask
Definition: X86BaseInfo.h:855
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:339
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
getFPReg
static unsigned getFPReg(const MachineOperand &MO)
getFPReg - Return the X86::FPx register number for the specified operand.
Definition: X86FloatingPoint.cpp:315
llvm::CallingConv::X86_RegCall
@ X86_RegCall
Register calling convention used for parameters transfer optimization.
Definition: CallingConv.h:219
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
ForwardSTiTable
static const TableEntry ForwardSTiTable[]
Definition: X86FloatingPoint.cpp:1286
llvm::MachineRegisterInfo::reg_nodbg_empty
bool reg_nodbg_empty(Register RegNo) const
reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.
Definition: MachineRegisterInfo.h:377
raw_ostream.h
X86InstrInfo.h
llvm::MachineInstrBundleIterator< MachineInstr >
InitializePasses.h
llvm::MachineBasicBlock::getName
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
Definition: MachineBasicBlock.cpp:314
Debug.h
PopTable
static const TableEntry PopTable[]
Definition: X86FloatingPoint.cpp:807
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::ArrayRef::end
iterator end() const
Definition: ArrayRef.h:154
llvm::EdgeBundles::getBundle
unsigned getBundle(unsigned N, bool Out) const
getBundle - Return the ingoing (Out = false) or outgoing (Out = true) bundle number for basic block N
Definition: EdgeBundles.h:41
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
LivePhysRegs.h
llvm::X86II::ZeroArgFP
@ ZeroArgFP
Definition: X86BaseInfo.h:861