108void X86AsmPrinter::StackMapShadowTracker::count(
MCInst &Inst,
115 CurrentShadowSize +=
Code.size();
116 if (CurrentShadowSize >= RequiredShadowSize)
121void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
123 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
125 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
130void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
137 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
153 "Isn't a symbol reference");
169 Suffix =
"$non_lazy_ptr";
174 Name +=
DL.getPrivateGlobalPrefix();
181 }
else if (MO.
isMBB()) {
188 Sym = Ctx.getOrCreateSymbol(
Name);
199 if (!StubSym.getPointer()) {
209 getMachOMMI().getGVStubEntry(
Sym);
227 const MCExpr *Expr =
nullptr;
304 assert(MAI.doesSetDirectiveSuppressReloc());
326 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
366 Opcode = X86::JMP32r;
369 Opcode = X86::JMP32m;
371 case X86::TAILJMPr64:
372 Opcode = X86::JMP64r;
374 case X86::TAILJMPm64:
375 Opcode = X86::JMP64m;
377 case X86::TAILJMPr64_REX:
378 Opcode = X86::JMP64r_REX;
380 case X86::TAILJMPm64_REX:
381 Opcode = X86::JMP64m_REX;
384 case X86::TAILJMPd64:
387 case X86::TAILJMPd_CC:
388 case X86::TAILJMPd64_CC:
400 if (
auto Op = LowerMachineOperand(
MI, MO);
Op.isValid())
403 bool In64BitMode =
AsmPrinter.getSubtarget().is64Bit();
420 "Unexpected # of LEA operands");
422 "LEA has segment specified!");
427 case X86::MULX64Hrm: {
432 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
433 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
434 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
435 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
448 case X86::CALL64pcrel32:
452 case X86::EH_RETURN64: {
457 case X86::CLEANUPRET: {
463 case X86::CATCHRET: {
466 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
475 case X86::TAILJMPr64:
476 case X86::TAILJMPr64_REX:
478 case X86::TAILJMPd64:
482 case X86::TAILJMPd_CC:
483 case X86::TAILJMPd64_CC:
488 case X86::TAILJMPm64:
489 case X86::TAILJMPm64_REX:
491 "Unexpected number of operands!");
494 case X86::MASKMOVDQU:
495 case X86::VMASKMOVDQU:
510 MI->findRegisterDefOperand(X86::EFLAGS,
nullptr);
511 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->
isDead())
520void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
528 switch (
MI.getOpcode()) {
529 case X86::TLS_addr32:
530 case X86::TLS_addr64:
531 case X86::TLS_addrX32:
534 case X86::TLS_base_addr32:
537 case X86::TLS_base_addr64:
538 case X86::TLS_base_addrX32:
541 case X86::TLS_desc32:
542 case X86::TLS_desc64:
550 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
562 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)),
564 EmitAndCountInstruction(
566 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
567 .addReg(Is64Bits ? X86::RIP : X86::EBX)
572 EmitAndCountInstruction(
574 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX)
579 }
else if (Is64Bits) {
581 if (NeedsPadding && Is64BitsLP64)
607 EmitAndCountInstruction(
642 EmitAndCountInstruction(
657 unsigned MaxNopLength = 1;
658 if (Subtarget->is64Bit()) {
661 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
663 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
665 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
669 }
if (Subtarget->is32Bit())
673 NumBytes = std::min(NumBytes, MaxNopLength);
676 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
677 IndexReg = Displacement = SegmentReg = 0;
735 SegmentReg = X86::CS;
739 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
740 NopSize += NumPrefixes;
741 for (
unsigned i = 0; i != NumPrefixes; ++i)
742 OS.emitBytes(
"\x66");
759 .addImm(Displacement)
764 assert(NopSize <= NumBytes &&
"We overemitted?");
771 unsigned NopsToEmit = NumBytes;
774 NumBytes -=
emitNop(
OS, NumBytes, Subtarget);
775 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
780 X86MCInstLower &MCIL) {
781 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
786 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
793 switch (CallTarget.
getType()) {
796 CallTargetMCOp = MCIL.LowerSymbolOperand(
797 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
798 CallOpcode = X86::CALL64pcrel32;
806 CallOpcode = X86::CALL64pcrel32;
818 CallOpcode = X86::CALL64r;
828 CallInst.addOperand(CallTargetMCOp);
840void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
841 X86MCInstLower &MCIL) {
852 unsigned OperandsBeginIdx = 4;
862 MI.setOpcode(Opcode);
864 if (DefRegister != X86::NoRegister)
869 if (
auto Op = MCIL.LowerMachineOperand(&FaultingMI, MO);
Op.isValid())
877 X86MCInstLower &MCIL) {
878 bool Is64Bits = Subtarget->is64Bit();
884 EmitAndCountInstruction(
885 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
890 assert(std::next(
MI.getIterator())->isCall() &&
891 "KCFI_CHECK not followed by a call instruction");
898 int64_t PrefixNops = 0;
909 const Register AddrReg =
MI.getOperand(0).getReg();
913 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
914 EmitAndCountInstruction(
917 .addReg(X86::NoRegister)
921 .addReg(X86::NoRegister)
922 .addImm(-(PrefixNops + 4))
923 .addReg(X86::NoRegister));
926 EmitAndCountInstruction(
938void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
945 const auto &
Reg =
MI.getOperand(0).getReg();
952 AccessInfo.CompileKernel, &ShadowBase,
953 &MappingScale, &OrShadowOffset);
957 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
958 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
963 "OrShadowOffset is not supported with optimized callbacks");
965 EmitAndCountInstruction(
972 X86MCInstLower &MCIL) {
977 auto NextMI = std::find_if(std::next(
MI.getIterator()),
978 MI.getParent()->end().getInstrIterator(),
979 [](
auto &
II) { return !II.isMetaInstruction(); });
982 unsigned MinSize =
MI.getOperand(0).getImm();
984 if (NextMI !=
MI.getParent()->end() && !NextMI->isInlineAsm()) {
989 MCIL.Lower(&*NextMI, MCI);
995 if (
Code.size() < MinSize) {
996 if (MinSize == 2 && Subtarget->is32Bit() &&
998 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
1004 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1008 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1024 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1025 SMShadowTracker.reset(NumShadowBytes);
1031 X86MCInstLower &MCIL) {
1032 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1044 unsigned ScratchIdx = opers.getNextScratchIdx();
1045 unsigned EncodedBytes = 0;
1062 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1063 MCIL.GetSymbolFromOperand(CalleeMO));
1069 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1075 EmitAndCountInstruction(
1080 "Lowering patchpoint with thunks not yet implemented.");
1081 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1085 unsigned NumBytes = opers.getNumPatchBytes();
1086 assert(NumBytes >= EncodedBytes &&
1087 "Patchpoint can't request size less than the length of a call.");
1092void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1093 X86MCInstLower &MCIL) {
1094 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1119 OutStreamer->AddComment(
"# XRay Custom Event Log");
1130 const Register DestRegs[] = {X86::RDI, X86::RSI};
1131 bool UsedMask[] = {
false,
false};
1140 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1141 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I));
1143 assert(
Op.isReg() &&
"Only support arguments in registers");
1146 if (SrcRegs[
I] != DestRegs[
I]) {
1148 EmitAndCountInstruction(
1159 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1160 if (SrcRegs[
I] != DestRegs[
I])
1161 EmitAndCountInstruction(
1173 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1176 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1178 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1182 OutStreamer->AddComment(
"xray custom event end.");
1190void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1191 X86MCInstLower &MCIL) {
1192 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1217 OutStreamer->AddComment(
"# XRay Typed Event Log");
1229 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1230 bool UsedMask[] = {
false,
false,
false};
1239 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1240 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I));
1243 assert(
Op.isReg() &&
"Only supports arguments in registers");
1246 if (SrcRegs[
I] != DestRegs[
I]) {
1248 EmitAndCountInstruction(
1264 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1266 EmitAndCountInstruction(
1278 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1281 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1283 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1293void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1294 X86MCInstLower &MCIL) {
1299 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1301 if (
F.getFnAttribute(
"patchable-function-entry")
1303 .getAsInteger(10, Num))
1334 X86MCInstLower &MCIL) {
1354 unsigned OpCode =
MI.getOperand(0).getImm();
1356 Ret.setOpcode(OpCode);
1358 if (
auto Op = MCIL.LowerMachineOperand(&
MI, MO);
Op.isValid())
1365void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1366 X86MCInstLower &MCIL) {
1371 bool IsConditional = TC.
getOpcode() == X86::JCC_1;
1373 if (IsConditional) {
1420 for (
auto &MO : TCOperands)
1421 if (
auto Op = MCIL.LowerMachineOperand(&
MI, MO);
Op.isValid())
1457 unsigned SrcOpIdx) {
1467 CS <<
" {%" << Mask <<
"}";
1478 if (Src1Name == Src2Name)
1479 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i)
1480 if (ShuffleMask[i] >= e)
1481 ShuffleMask[i] -= e;
1483 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1493 bool isSrc1 = ShuffleMask[i] < (int)e;
1494 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1496 bool IsFirst =
true;
1498 (ShuffleMask[i] < (
int)e) == isSrc1) {
1506 CS << ShuffleMask[i] % (int)e;
1516 std::string Comment;
1537 bool PrintZero =
false) {
1546 CS << (PrintZero ? 0ULL : Val.
getRawData()[i]);
1553 bool PrintZero =
false) {
1559 Flt.toString(Str, 0, 0);
1565 if (isa<UndefValue>(COp)) {
1567 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1569 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1571 }
else if (
auto *CDS = dyn_cast<ConstantDataSequential>(COp)) {
1572 Type *EltTy = CDS->getElementType();
1576 unsigned E = std::min(
BitWidth / EltBits, CDS->getNumElements());
1578 for (
unsigned I = 0;
I != E; ++
I) {
1588 }
else if (
auto *CV = dyn_cast<ConstantVector>(COp)) {
1589 unsigned EltBits = CV->getType()->getScalarSizeInBits();
1590 unsigned E = std::min(
BitWidth / EltBits, CV->getNumOperands());
1592 for (
unsigned I = 0;
I != E; ++
I) {
1603 int SclWidth,
int VecWidth,
1604 const char *ShuffleComment) {
1607 std::string Comment;
1615 for (
int I = 1, E = VecWidth / SclWidth;
I < E; ++
I) {
1625 CS << ShuffleComment;
1633 std::string Comment;
1637 for (
int l = 0; l != Repeats; ++l) {
1648 int SrcEltBits,
int DstEltBits,
bool IsSext) {
1651 if (
C &&
C->getType()->getScalarSizeInBits() ==
unsigned(SrcEltBits)) {
1652 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
1653 int NumElts = CDS->getNumElements();
1654 std::string Comment;
1658 for (
int i = 0; i != NumElts; ++i) {
1661 if (CDS->getElementType()->isIntegerTy()) {
1662 APInt Elt = CDS->getElementAsAPInt(i);
1663 Elt = IsSext ? Elt.
sext(DstEltBits) : Elt.
zext(DstEltBits);
1677 int SrcEltBits,
int DstEltBits) {
1681 int SrcEltBits,
int DstEltBits) {
1682 if (
printExtend(
MI, OutStreamer, SrcEltBits, DstEltBits,
false))
1686 std::string Comment;
1693 assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
1694 "Illegal extension ratio");
1704 "SEH_ instruction Windows and UEFI only");
1710 switch (
MI->getOpcode()) {
1711 case X86::SEH_PushReg:
1714 case X86::SEH_StackAlloc:
1717 case X86::SEH_StackAlign:
1720 case X86::SEH_SetFrame:
1721 assert(
MI->getOperand(1).getImm() == 0 &&
1722 ".cv_fpo_setframe takes no offset");
1725 case X86::SEH_EndPrologue:
1728 case X86::SEH_SaveReg:
1729 case X86::SEH_SaveXMM:
1730 case X86::SEH_PushFrame:
1740 switch (
MI->getOpcode()) {
1741 case X86::SEH_PushReg:
1745 case X86::SEH_SaveReg:
1747 MI->getOperand(1).getImm());
1750 case X86::SEH_SaveXMM:
1752 MI->getOperand(1).getImm());
1755 case X86::SEH_StackAlloc:
1756 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
1759 case X86::SEH_SetFrame:
1761 MI->getOperand(1).getImm());
1764 case X86::SEH_PushFrame:
1765 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
1768 case X86::SEH_EndPrologue:
1779 switch (
MI->getOpcode()) {
1784 case X86::VPSHUFBrm:
1785 case X86::VPSHUFBYrm:
1786 case X86::VPSHUFBZ128rm:
1787 case X86::VPSHUFBZ128rmk:
1788 case X86::VPSHUFBZ128rmkz:
1789 case X86::VPSHUFBZ256rm:
1790 case X86::VPSHUFBZ256rmk:
1791 case X86::VPSHUFBZ256rmkz:
1792 case X86::VPSHUFBZrm:
1793 case X86::VPSHUFBZrmk:
1794 case X86::VPSHUFBZrmkz: {
1806 case X86::VPERMILPSrm:
1807 case X86::VPERMILPSYrm:
1808 case X86::VPERMILPSZ128rm:
1809 case X86::VPERMILPSZ128rmk:
1810 case X86::VPERMILPSZ128rmkz:
1811 case X86::VPERMILPSZ256rm:
1812 case X86::VPERMILPSZ256rmk:
1813 case X86::VPERMILPSZ256rmkz:
1814 case X86::VPERMILPSZrm:
1815 case X86::VPERMILPSZrmk:
1816 case X86::VPERMILPSZrmkz: {
1827 case X86::VPERMILPDrm:
1828 case X86::VPERMILPDYrm:
1829 case X86::VPERMILPDZ128rm:
1830 case X86::VPERMILPDZ128rmk:
1831 case X86::VPERMILPDZ128rmkz:
1832 case X86::VPERMILPDZ256rm:
1833 case X86::VPERMILPDZ256rmk:
1834 case X86::VPERMILPDZ256rmkz:
1835 case X86::VPERMILPDZrm:
1836 case X86::VPERMILPDZrmk:
1837 case X86::VPERMILPDZrmkz: {
1849 case X86::VPERMIL2PDrm:
1850 case X86::VPERMIL2PSrm:
1851 case X86::VPERMIL2PDYrm:
1852 case X86::VPERMIL2PSYrm: {
1854 "Unexpected number of operands!");
1857 if (!CtrlOp.
isImm())
1861 switch (
MI->getOpcode()) {
1863 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
1864 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
1877 case X86::VPPERMrrm: {
1888 case X86::MMX_MOVQ64rm: {
1890 std::string Comment;
1894 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
1895 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
1902#define INSTR_CASE(Prefix, Instr, Suffix, Postfix) \
1903 case X86::Prefix##Instr##Suffix##rm##Postfix:
1905#define CASE_ARITH_RM(Instr) \
1906 INSTR_CASE(, Instr, , ) \
1907 INSTR_CASE(V, Instr, , ) \
1908 INSTR_CASE(V, Instr, Y, ) \
1909 INSTR_CASE(V, Instr, Z128, ) \
1910 INSTR_CASE(V, Instr, Z128, k) \
1911 INSTR_CASE(V, Instr, Z128, kz) \
1912 INSTR_CASE(V, Instr, Z256, ) \
1913 INSTR_CASE(V, Instr, Z256, k) \
1914 INSTR_CASE(V, Instr, Z256, kz) \
1915 INSTR_CASE(V, Instr, Z, ) \
1916 INSTR_CASE(V, Instr, Z, k) \
1917 INSTR_CASE(V, Instr, Z, kz)
1923 if (
C->getType()->getScalarSizeInBits() == 8) {
1924 std::string Comment;
1926 unsigned VectorWidth =
1944 if (
C->getType()->getScalarSizeInBits() == 16) {
1945 std::string Comment;
1947 unsigned VectorWidth =
1958#define MASK_AVX512_CASE(Instr) \
1966 case X86::MOVSDrm_alt:
1967 case X86::VMOVSDrm_alt:
1968 case X86::VMOVSDZrm_alt:
1969 case X86::MOVQI2PQIrm:
1970 case X86::VMOVQI2PQIrm:
1971 case X86::VMOVQI2PQIZrm:
1976 case X86::VMOVSHZrm_alt:
1978 "mem[0],zero,zero,zero,zero,zero,zero,zero");
1984 case X86::MOVSSrm_alt:
1985 case X86::VMOVSSrm_alt:
1986 case X86::VMOVSSZrm_alt:
1987 case X86::MOVDI2PDIrm:
1988 case X86::VMOVDI2PDIrm:
1989 case X86::VMOVDI2PDIZrm:
1993#define MOV_CASE(Prefix, Suffix) \
1994 case X86::Prefix##MOVAPD##Suffix##rm: \
1995 case X86::Prefix##MOVAPS##Suffix##rm: \
1996 case X86::Prefix##MOVUPD##Suffix##rm: \
1997 case X86::Prefix##MOVUPS##Suffix##rm: \
1998 case X86::Prefix##MOVDQA##Suffix##rm: \
1999 case X86::Prefix##MOVDQU##Suffix##rm:
2001#define MOV_AVX512_CASE(Suffix, Postfix) \
2002 case X86::VMOVDQA64##Suffix##rm##Postfix: \
2003 case X86::VMOVDQA32##Suffix##rm##Postfix: \
2004 case X86::VMOVDQU64##Suffix##rm##Postfix: \
2005 case X86::VMOVDQU32##Suffix##rm##Postfix: \
2006 case X86::VMOVDQU16##Suffix##rm##Postfix: \
2007 case X86::VMOVDQU8##Suffix##rm##Postfix: \
2008 case X86::VMOVAPS##Suffix##rm##Postfix: \
2009 case X86::VMOVAPD##Suffix##rm##Postfix: \
2010 case X86::VMOVUPS##Suffix##rm##Postfix: \
2011 case X86::VMOVUPD##Suffix##rm##Postfix:
2013#define CASE_128_MOV_RM() \
2016 MOV_AVX512_CASE(Z128, ) \
2017 MOV_AVX512_CASE(Z128, k) \
2018 MOV_AVX512_CASE(Z128, kz)
2020#define CASE_256_MOV_RM() \
2022 MOV_AVX512_CASE(Z256, ) \
2023 MOV_AVX512_CASE(Z256, k) \
2024 MOV_AVX512_CASE(Z256, kz) \
2026#define CASE_512_MOV_RM() \
2027 MOV_AVX512_CASE(Z, ) \
2028 MOV_AVX512_CASE(Z, k) \
2029 MOV_AVX512_CASE(Z, kz) \
2042 case X86::VBROADCASTF128rm:
2043 case X86::VBROADCASTI128rm:
2065 case X86::MOVDDUPrm:
2066 case X86::VMOVDDUPrm:
2068 case X86::VPBROADCASTQrm:
2072 case X86::VBROADCASTSDYrm:
2074 case X86::VPBROADCASTQYrm:
2082 case X86::VBROADCASTSSrm:
2084 case X86::VPBROADCASTDrm:
2088 case X86::VBROADCASTSSYrm:
2090 case X86::VPBROADCASTDYrm:
2098 case X86::VPBROADCASTWrm:
2102 case X86::VPBROADCASTWYrm:
2109 case X86::VPBROADCASTBrm:
2113 case X86::VPBROADCASTBYrm:
2121#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2122 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
2124#define CASE_MOVX_RM(Ext, Type) \
2125 MOVX_CASE(, Ext, Type, , ) \
2126 MOVX_CASE(V, Ext, Type, , ) \
2127 MOVX_CASE(V, Ext, Type, Y, ) \
2128 MOVX_CASE(V, Ext, Type, Z128, ) \
2129 MOVX_CASE(V, Ext, Type, Z128, k ) \
2130 MOVX_CASE(V, Ext, Type, Z128, kz ) \
2131 MOVX_CASE(V, Ext, Type, Z256, ) \
2132 MOVX_CASE(V, Ext, Type, Z256, k ) \
2133 MOVX_CASE(V, Ext, Type, Z256, kz ) \
2134 MOVX_CASE(V, Ext, Type, Z, ) \
2135 MOVX_CASE(V, Ext, Type, Z, k ) \
2136 MOVX_CASE(V, Ext, Type, Z, kz )
2183 X86MCInstLower MCInstLowering(*
MF, *
this);
2187 if (
MI->getOpcode() == X86::OR64rm) {
2188 for (
auto &Opd :
MI->operands()) {
2189 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2190 "swift_async_extendedFramePointerFlags") {
2191 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2203 OutStreamer->AddComment(
"EVEX TO LEGACY Compression ",
false);
2205 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2207 OutStreamer->AddComment(
"EVEX TO EVEX Compression ",
false);
2210 switch (
MI->getOpcode()) {
2211 case TargetOpcode::DBG_VALUE:
2214 case X86::EH_RETURN:
2215 case X86::EH_RETURN64: {
2222 case X86::CLEANUPRET: {
2228 case X86::CATCHRET: {
2235 case X86::ENDBR64: {
2244 MCInstLowering.Lower(
MI, Inst);
2245 EmitAndCountInstruction(Inst);
2253 case X86::TAILJMPd64:
2254 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2260 case X86::TAILJMPd_CC:
2261 case X86::TAILJMPr64:
2262 case X86::TAILJMPm64:
2263 case X86::TAILJMPd64_CC:
2264 case X86::TAILJMPr64_REX:
2265 case X86::TAILJMPm64_REX:
2270 case X86::TLS_addr32:
2271 case X86::TLS_addr64:
2272 case X86::TLS_addrX32:
2273 case X86::TLS_base_addr32:
2274 case X86::TLS_base_addr64:
2275 case X86::TLS_base_addrX32:
2276 case X86::TLS_desc32:
2277 case X86::TLS_desc64:
2278 return LowerTlsAddr(MCInstLowering, *
MI);
2280 case X86::MOVPC32r: {
2291 EmitAndCountInstruction(
2297 bool hasFP = FrameLowering->
hasFP(*
MF);
2300 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2305 if (HasActiveDwarfFrame && !hasFP) {
2306 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2314 EmitAndCountInstruction(
2317 if (HasActiveDwarfFrame && !hasFP) {
2323 case X86::ADD32ri: {
2339 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2350 .addReg(
MI->getOperand(0).getReg())
2351 .
addReg(
MI->getOperand(1).getReg())
2355 case TargetOpcode::STATEPOINT:
2356 return LowerSTATEPOINT(*
MI, MCInstLowering);
2358 case TargetOpcode::FAULTING_OP:
2359 return LowerFAULTING_OP(*
MI, MCInstLowering);
2361 case TargetOpcode::FENTRY_CALL:
2362 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2364 case TargetOpcode::PATCHABLE_OP:
2365 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2367 case TargetOpcode::STACKMAP:
2368 return LowerSTACKMAP(*
MI);
2370 case TargetOpcode::PATCHPOINT:
2371 return LowerPATCHPOINT(*
MI, MCInstLowering);
2373 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2374 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2376 case TargetOpcode::PATCHABLE_RET:
2377 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2379 case TargetOpcode::PATCHABLE_TAIL_CALL:
2380 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2382 case TargetOpcode::PATCHABLE_EVENT_CALL:
2383 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2385 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2386 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2388 case X86::MORESTACK_RET:
2392 case X86::KCFI_CHECK:
2393 return LowerKCFI_CHECK(*
MI);
2395 case X86::ASAN_CHECK_MEMACCESS:
2396 return LowerASAN_CHECK_MEMACCESS(*
MI);
2398 case X86::MORESTACK_RET_RESTORE_R10:
2401 EmitAndCountInstruction(
2402 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2405 case X86::SEH_PushReg:
2406 case X86::SEH_SaveReg:
2407 case X86::SEH_SaveXMM:
2408 case X86::SEH_StackAlloc:
2409 case X86::SEH_StackAlign:
2410 case X86::SEH_SetFrame:
2411 case X86::SEH_PushFrame:
2412 case X86::SEH_EndPrologue:
2413 EmitSEHInstruction(
MI);
2416 case X86::SEH_Epilogue: {
2426 if (
MBBI->isCall() || !
MBBI->isPseudo()) {
2434 case X86::UBSAN_UD1:
2439 .addReg(X86::NoRegister)
2440 .addImm(
MI->getOperand(0).getImm())
2441 .
addReg(X86::NoRegister));
2443 case X86::CALL64pcrel32:
2444 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2450 MCInstLowering.Lower(
MI, TmpInst);
2467 EmitAndCountInstruction(TmpInst);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
uint64_t IntrinsicInst * II
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
static void printShuffleMask(raw_ostream &CS, StringRef Src1Name, StringRef Src2Name, ArrayRef< int > Mask)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static unsigned getSrcIdx(const MachineInstr *MI, unsigned SrcIdx)
static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer, int Repeats, int BitWidth)
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits, bool IsSext)
static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer, int SclWidth, int VecWidth, const char *ShuffleComment)
#define MASK_AVX512_CASE(Instr)
#define CASE_ARITH_RM(Instr)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
#define CASE_256_MOV_RM()
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI, unsigned SrcOpIdx)
#define CASE_MOVX_RM(Ext, Type)
static void printConstant(const APInt &Val, raw_ostream &CS, bool PrintZero=false)
static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer, int SrcEltBits, int DstEltBits)
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
#define CASE_512_MOV_RM()
#define CASE_128_MOV_RM()
void toString(SmallVectorImpl< char > &Str, unsigned FormatPrecision=0, unsigned FormatMaxPadding=3, bool TruncateZero=true) const
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Zero.
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumWords() const
Get the number of words.
APInt sext(unsigned width) const
Sign extend to a new width.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
MCSymbol * CurrentFnBegin
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
TargetMachine & TM
Target machine description.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
StringRef getValueAsString() const
Return the attribute's value as a string.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasInternalLinkage() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
const MCTargetOptions * getTargetOptions() const
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
iterator insert(iterator I, const MCOperand &Op)
void setFlags(unsigned F)
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Streaming machine code generation interface.
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
void setAllowAutoPadding(bool v)
bool getAllowAutoPadding() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
const MachineOperand & getOperand(unsigned i) const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
MI-level patchpoint operands.
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
bool useIndirectThunkCalls() const
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
bool isX86_64ExtendedReg(unsigned RegNo)
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_NO_FLAG
MO_NO_FLAG - No flag for the operand.
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool isKMasked(uint64_t TSFlags)
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
void DecodeZeroExtendMask(unsigned SrcScalarBits, unsigned DstScalarBits, unsigned NumDstElts, bool IsAnyExtend, SmallVectorImpl< int > &ShuffleMask)
Decode a zero extension instruction as a shuffle mask.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
auto drop_end(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the last N elements excluded.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
constexpr unsigned BitWidth
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.