58 class X86MCInstLower {
87 : OS(OS), OldAllowAutoPadding(OS.getAllowAutoPadding()) {
88 changeAndComment(
false);
114 CurrentShadowSize +=
Code.size();
115 if (CurrentShadowSize >= RequiredShadowSize)
120 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
122 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
124 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
129 void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
136 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
152 "Isn't a symbol reference");
168 Suffix =
"$non_lazy_ptr";
173 Name +=
DL.getPrivateGlobalPrefix();
180 }
else if (MO.
isMBB()) {
187 Sym = Ctx.getOrCreateSymbol(
Name);
198 if (!StubSym.getPointer()) {
208 getMachOMMI().getGVStubEntry(Sym);
226 const MCExpr *Expr =
nullptr;
240 RefKind = MCSymbolRefExpr::VK_TLVP;
243 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
245 Expr = MCBinaryExpr::createSub(
246 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
249 RefKind = MCSymbolRefExpr::VK_SECREL;
252 RefKind = MCSymbolRefExpr::VK_TLSGD;
255 RefKind = MCSymbolRefExpr::VK_TLSLD;
258 RefKind = MCSymbolRefExpr::VK_TLSLDM;
261 RefKind = MCSymbolRefExpr::VK_GOTTPOFF;
264 RefKind = MCSymbolRefExpr::VK_INDNTPOFF;
267 RefKind = MCSymbolRefExpr::VK_TPOFF;
270 RefKind = MCSymbolRefExpr::VK_DTPOFF;
273 RefKind = MCSymbolRefExpr::VK_NTPOFF;
276 RefKind = MCSymbolRefExpr::VK_GOTNTPOFF;
279 RefKind = MCSymbolRefExpr::VK_GOTPCREL;
282 RefKind = MCSymbolRefExpr::VK_GOTPCREL_NORELAX;
285 RefKind = MCSymbolRefExpr::VK_GOT;
288 RefKind = MCSymbolRefExpr::VK_GOTOFF;
291 RefKind = MCSymbolRefExpr::VK_PLT;
294 RefKind = MCSymbolRefExpr::VK_X86_ABS8;
298 Expr = MCSymbolRefExpr::create(Sym, Ctx);
300 Expr = MCBinaryExpr::createSub(
301 Expr, MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx), Ctx);
303 assert(MAI.doesSetDirectiveSuppressReloc());
310 Expr = MCSymbolRefExpr::create(Label, Ctx);
316 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
319 Expr = MCBinaryExpr::createAdd(
320 Expr, MCConstantExpr::create(MO.
getOffset(), Ctx), Ctx);
321 return MCOperand::createExpr(Expr);
333 "Unexpected instruction!");
350 unsigned NewOpcode = 0;
355 case X86::MOVSX16rr8:
356 if (Op0 == X86::AX && Op1 ==
X86::AL)
357 NewOpcode = X86::CBW;
359 case X86::MOVSX32rr16:
360 if (Op0 ==
X86::EAX && Op1 == X86::AX)
361 NewOpcode = X86::CWDE;
363 case X86::MOVSX64rr32:
364 if (Op0 == X86::RAX && Op1 ==
X86::EAX)
365 NewOpcode = X86::CDQE;
369 if (NewOpcode != 0) {
380 if (
Printer.getSubtarget().is64Bit())
384 unsigned AddrBase = IsStore;
385 unsigned RegOp = IsStore ? 0 : 5;
386 unsigned AddrOp = AddrBase + 3;
394 "Unexpected instruction!");
408 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
428 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
438 case MachineOperand::MO_Register:
442 return MCOperand::createReg(MO.
getReg());
443 case MachineOperand::MO_Immediate:
444 return MCOperand::createImm(MO.
getImm());
445 case MachineOperand::MO_MachineBasicBlock:
446 case MachineOperand::MO_GlobalAddress:
447 case MachineOperand::MO_ExternalSymbol:
449 case MachineOperand::MO_MCSymbol:
451 case MachineOperand::MO_JumpTableIndex:
453 case MachineOperand::MO_ConstantPoolIndex:
455 case MachineOperand::MO_BlockAddress:
458 case MachineOperand::MO_RegisterMask:
469 Opcode = X86::JMP32r;
472 Opcode = X86::JMP32m;
474 case X86::TAILJMPr64:
475 Opcode = X86::JMP64r;
477 case X86::TAILJMPm64:
478 Opcode = X86::JMP64m;
480 case X86::TAILJMPr64_REX:
481 Opcode = X86::JMP64r_REX;
483 case X86::TAILJMPm64_REX:
484 Opcode = X86::JMP64m_REX;
487 case X86::TAILJMPd64:
490 case X86::TAILJMPd_CC:
491 case X86::TAILJMPd64_CC:
503 if (
auto MaybeMCOp = LowerMachineOperand(
MI, MO))
514 "Unexpected # of LEA operands");
516 "LEA has segment specified!");
522 case X86::MULX64Hrm: {
527 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
528 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
529 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
530 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
535 OutMI.
insert(OutMI.
begin(), MCOperand::createReg(DestReg));
541 case X86::VMOVZPQILo2PQIrr:
543 case X86::VMOVAPDYrr:
545 case X86::VMOVAPSYrr:
547 case X86::VMOVDQAYrr:
549 case X86::VMOVDQUYrr:
551 case X86::VMOVUPDYrr:
553 case X86::VMOVUPSYrr: {
559 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;
break;
560 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV;
break;
561 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV;
break;
562 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV;
break;
563 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV;
break;
564 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV;
break;
565 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV;
break;
566 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV;
break;
567 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV;
break;
568 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV;
break;
569 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV;
break;
570 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV;
break;
571 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV;
break;
578 case X86::VMOVSSrr: {
584 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV;
break;
585 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV;
break;
592 case X86::VPCMPBZ128rmi:
case X86::VPCMPBZ128rmik:
593 case X86::VPCMPBZ128rri:
case X86::VPCMPBZ128rrik:
594 case X86::VPCMPBZ256rmi:
case X86::VPCMPBZ256rmik:
595 case X86::VPCMPBZ256rri:
case X86::VPCMPBZ256rrik:
596 case X86::VPCMPBZrmi:
case X86::VPCMPBZrmik:
597 case X86::VPCMPBZrri:
case X86::VPCMPBZrrik:
598 case X86::VPCMPDZ128rmi:
case X86::VPCMPDZ128rmik:
599 case X86::VPCMPDZ128rmib:
case X86::VPCMPDZ128rmibk:
600 case X86::VPCMPDZ128rri:
case X86::VPCMPDZ128rrik:
601 case X86::VPCMPDZ256rmi:
case X86::VPCMPDZ256rmik:
602 case X86::VPCMPDZ256rmib:
case X86::VPCMPDZ256rmibk:
603 case X86::VPCMPDZ256rri:
case X86::VPCMPDZ256rrik:
604 case X86::VPCMPDZrmi:
case X86::VPCMPDZrmik:
605 case X86::VPCMPDZrmib:
case X86::VPCMPDZrmibk:
606 case X86::VPCMPDZrri:
case X86::VPCMPDZrrik:
607 case X86::VPCMPQZ128rmi:
case X86::VPCMPQZ128rmik:
608 case X86::VPCMPQZ128rmib:
case X86::VPCMPQZ128rmibk:
609 case X86::VPCMPQZ128rri:
case X86::VPCMPQZ128rrik:
610 case X86::VPCMPQZ256rmi:
case X86::VPCMPQZ256rmik:
611 case X86::VPCMPQZ256rmib:
case X86::VPCMPQZ256rmibk:
612 case X86::VPCMPQZ256rri:
case X86::VPCMPQZ256rrik:
613 case X86::VPCMPQZrmi:
case X86::VPCMPQZrmik:
614 case X86::VPCMPQZrmib:
case X86::VPCMPQZrmibk:
615 case X86::VPCMPQZrri:
case X86::VPCMPQZrrik:
616 case X86::VPCMPWZ128rmi:
case X86::VPCMPWZ128rmik:
617 case X86::VPCMPWZ128rri:
case X86::VPCMPWZ128rrik:
618 case X86::VPCMPWZ256rmi:
case X86::VPCMPWZ256rmik:
619 case X86::VPCMPWZ256rri:
case X86::VPCMPWZ256rrik:
620 case X86::VPCMPWZrmi:
case X86::VPCMPWZrmik:
621 case X86::VPCMPWZrri:
case X86::VPCMPWZrrik: {
627 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPEQBZ128rm;
break;
628 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPEQBZ128rmk;
break;
629 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPEQBZ128rr;
break;
630 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPEQBZ128rrk;
break;
631 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPEQBZ256rm;
break;
632 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPEQBZ256rmk;
break;
633 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPEQBZ256rr;
break;
634 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPEQBZ256rrk;
break;
635 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPEQBZrm;
break;
636 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPEQBZrmk;
break;
637 case X86::VPCMPBZrri: NewOpc = X86::VPCMPEQBZrr;
break;
638 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPEQBZrrk;
break;
639 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPEQDZ128rm;
break;
640 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPEQDZ128rmb;
break;
641 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPEQDZ128rmbk;
break;
642 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPEQDZ128rmk;
break;
643 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPEQDZ128rr;
break;
644 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPEQDZ128rrk;
break;
645 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPEQDZ256rm;
break;
646 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPEQDZ256rmb;
break;
647 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPEQDZ256rmbk;
break;
648 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPEQDZ256rmk;
break;
649 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPEQDZ256rr;
break;
650 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPEQDZ256rrk;
break;
651 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPEQDZrm;
break;
652 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPEQDZrmb;
break;
653 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPEQDZrmbk;
break;
654 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPEQDZrmk;
break;
655 case X86::VPCMPDZrri: NewOpc = X86::VPCMPEQDZrr;
break;
656 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPEQDZrrk;
break;
657 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPEQQZ128rm;
break;
658 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPEQQZ128rmb;
break;
659 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPEQQZ128rmbk;
break;
660 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPEQQZ128rmk;
break;
661 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPEQQZ128rr;
break;
662 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPEQQZ128rrk;
break;
663 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPEQQZ256rm;
break;
664 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPEQQZ256rmb;
break;
665 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPEQQZ256rmbk;
break;
666 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPEQQZ256rmk;
break;
667 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPEQQZ256rr;
break;
668 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPEQQZ256rrk;
break;
669 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPEQQZrm;
break;
670 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPEQQZrmb;
break;
671 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPEQQZrmbk;
break;
672 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPEQQZrmk;
break;
673 case X86::VPCMPQZrri: NewOpc = X86::VPCMPEQQZrr;
break;
674 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPEQQZrrk;
break;
675 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPEQWZ128rm;
break;
676 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPEQWZ128rmk;
break;
677 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPEQWZ128rr;
break;
678 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPEQWZ128rrk;
break;
679 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPEQWZ256rm;
break;
680 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPEQWZ256rmk;
break;
681 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPEQWZ256rr;
break;
682 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPEQWZ256rrk;
break;
683 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPEQWZrm;
break;
684 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPEQWZrmk;
break;
685 case X86::VPCMPWZrri: NewOpc = X86::VPCMPEQWZrr;
break;
686 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPEQWZrrk;
break;
699 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPGTBZ128rm;
break;
700 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPGTBZ128rmk;
break;
701 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPGTBZ128rr;
break;
702 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPGTBZ128rrk;
break;
703 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPGTBZ256rm;
break;
704 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPGTBZ256rmk;
break;
705 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPGTBZ256rr;
break;
706 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPGTBZ256rrk;
break;
707 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPGTBZrm;
break;
708 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPGTBZrmk;
break;
709 case X86::VPCMPBZrri: NewOpc = X86::VPCMPGTBZrr;
break;
710 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPGTBZrrk;
break;
711 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPGTDZ128rm;
break;
712 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPGTDZ128rmb;
break;
713 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPGTDZ128rmbk;
break;
714 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPGTDZ128rmk;
break;
715 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPGTDZ128rr;
break;
716 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPGTDZ128rrk;
break;
717 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPGTDZ256rm;
break;
718 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPGTDZ256rmb;
break;
719 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPGTDZ256rmbk;
break;
720 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPGTDZ256rmk;
break;
721 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPGTDZ256rr;
break;
722 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPGTDZ256rrk;
break;
723 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPGTDZrm;
break;
724 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPGTDZrmb;
break;
725 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPGTDZrmbk;
break;
726 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPGTDZrmk;
break;
727 case X86::VPCMPDZrri: NewOpc = X86::VPCMPGTDZrr;
break;
728 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPGTDZrrk;
break;
729 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPGTQZ128rm;
break;
730 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPGTQZ128rmb;
break;
731 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPGTQZ128rmbk;
break;
732 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPGTQZ128rmk;
break;
733 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPGTQZ128rr;
break;
734 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPGTQZ128rrk;
break;
735 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPGTQZ256rm;
break;
736 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPGTQZ256rmb;
break;
737 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPGTQZ256rmbk;
break;
738 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPGTQZ256rmk;
break;
739 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPGTQZ256rr;
break;
740 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPGTQZ256rrk;
break;
741 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPGTQZrm;
break;
742 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPGTQZrmb;
break;
743 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPGTQZrmbk;
break;
744 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPGTQZrmk;
break;
745 case X86::VPCMPQZrri: NewOpc = X86::VPCMPGTQZrr;
break;
746 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPGTQZrrk;
break;
747 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPGTWZ128rm;
break;
748 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPGTWZ128rmk;
break;
749 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPGTWZ128rr;
break;
750 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPGTWZ128rrk;
break;
751 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPGTWZ256rm;
break;
752 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPGTWZ256rmk;
break;
753 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPGTWZ256rr;
break;
754 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPGTWZ256rrk;
break;
755 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPGTWZrm;
break;
756 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPGTWZrmk;
break;
757 case X86::VPCMPWZrri: NewOpc = X86::VPCMPGTWZrr;
break;
758 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPGTWZrrk;
break;
774 case X86::CALL64pcrel32:
779 case X86::EH_RETURN64: {
795 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX :
X86::EAX;
798 OutMI.
addOperand(MCOperand::createReg(ReturnReg));
805 case X86::TAILJMPr64:
806 case X86::TAILJMPr64_REX:
808 case X86::TAILJMPd64:
813 case X86::TAILJMPd_CC:
814 case X86::TAILJMPd64_CC:
820 case X86::TAILJMPm64:
821 case X86::TAILJMPm64_REX:
823 "Unexpected number of operands!");
836 case X86::DEC16r: Opcode = X86::DEC16r_alt;
break;
837 case X86::DEC32r: Opcode = X86::DEC32r_alt;
break;
838 case X86::INC16r: Opcode = X86::INC16r_alt;
break;
839 case X86::INC32r: Opcode = X86::INC32r_alt;
break;
852 case X86::MOV8mr_NOREX:
854 case X86::MOV8rm_NOREX:
863 case X86::MOV8mr_NOREX:
864 case X86::MOV8mr: NewOpc = X86::MOV8o32a;
break;
865 case X86::MOV8rm_NOREX:
866 case X86::MOV8rm: NewOpc = X86::MOV8ao32;
break;
867 case X86::MOV16mr: NewOpc = X86::MOV16o32a;
break;
868 case X86::MOV16rm: NewOpc = X86::MOV16ao32;
break;
869 case X86::MOV32mr: NewOpc = X86::MOV32o32a;
break;
870 case X86::MOV32rm: NewOpc = X86::MOV32ao32;
break;
876 case X86::ADC8ri:
case X86::ADC16ri:
case X86::ADC32ri:
case X86::ADC64ri32:
877 case X86::ADD8ri:
case X86::ADD16ri:
case X86::ADD32ri:
case X86::ADD64ri32:
878 case X86::AND8ri:
case X86::AND16ri:
case X86::AND32ri:
case X86::AND64ri32:
879 case X86::CMP8ri:
case X86::CMP16ri:
case X86::CMP32ri:
case X86::CMP64ri32:
880 case X86::OR8ri:
case X86::OR16ri:
case X86::OR32ri:
case X86::OR64ri32:
881 case X86::SBB8ri:
case X86::SBB16ri:
case X86::SBB32ri:
case X86::SBB64ri32:
882 case X86::SUB8ri:
case X86::SUB16ri:
case X86::SUB32ri:
case X86::SUB64ri32:
883 case X86::TEST8ri:
case X86::TEST16ri:
case X86::TEST32ri:
case X86::TEST64ri32:
884 case X86::XOR8ri:
case X86::XOR16ri:
case X86::XOR32ri:
case X86::XOR64ri32: {
888 case X86::ADC8ri: NewOpc = X86::ADC8i8;
break;
889 case X86::ADC16ri: NewOpc = X86::ADC16i16;
break;
890 case X86::ADC32ri: NewOpc = X86::ADC32i32;
break;
891 case X86::ADC64ri32: NewOpc = X86::ADC64i32;
break;
892 case X86::ADD8ri: NewOpc = X86::ADD8i8;
break;
893 case X86::ADD16ri: NewOpc = X86::ADD16i16;
break;
894 case X86::ADD32ri: NewOpc = X86::ADD32i32;
break;
895 case X86::ADD64ri32: NewOpc = X86::ADD64i32;
break;
896 case X86::AND8ri: NewOpc = X86::AND8i8;
break;
897 case X86::AND16ri: NewOpc = X86::AND16i16;
break;
898 case X86::AND32ri: NewOpc = X86::AND32i32;
break;
899 case X86::AND64ri32: NewOpc = X86::AND64i32;
break;
900 case X86::CMP8ri: NewOpc = X86::CMP8i8;
break;
901 case X86::CMP16ri: NewOpc = X86::CMP16i16;
break;
902 case X86::CMP32ri: NewOpc = X86::CMP32i32;
break;
903 case X86::CMP64ri32: NewOpc = X86::CMP64i32;
break;
904 case X86::OR8ri: NewOpc = X86::OR8i8;
break;
905 case X86::OR16ri: NewOpc = X86::OR16i16;
break;
906 case X86::OR32ri: NewOpc = X86::OR32i32;
break;
907 case X86::OR64ri32: NewOpc = X86::OR64i32;
break;
908 case X86::SBB8ri: NewOpc = X86::SBB8i8;
break;
909 case X86::SBB16ri: NewOpc = X86::SBB16i16;
break;
910 case X86::SBB32ri: NewOpc = X86::SBB32i32;
break;
911 case X86::SBB64ri32: NewOpc = X86::SBB64i32;
break;
912 case X86::SUB8ri: NewOpc = X86::SUB8i8;
break;
913 case X86::SUB16ri: NewOpc = X86::SUB16i16;
break;
914 case X86::SUB32ri: NewOpc = X86::SUB32i32;
break;
915 case X86::SUB64ri32: NewOpc = X86::SUB64i32;
break;
916 case X86::TEST8ri: NewOpc = X86::TEST8i8;
break;
917 case X86::TEST16ri: NewOpc = X86::TEST16i16;
break;
918 case X86::TEST32ri: NewOpc = X86::TEST32i32;
break;
919 case X86::TEST64ri32: NewOpc = X86::TEST64i32;
break;
920 case X86::XOR8ri: NewOpc = X86::XOR8i8;
break;
921 case X86::XOR16ri: NewOpc = X86::XOR16i16;
break;
922 case X86::XOR32ri: NewOpc = X86::XOR32i32;
break;
923 case X86::XOR64ri32: NewOpc = X86::XOR64i32;
break;
930 case X86::MOVSX16rr8:
931 case X86::MOVSX32rr16:
932 case X86::MOVSX64rr32:
937 case X86::VCMPPDYrri:
939 case X86::VCMPPSYrri:
941 case X86::VCMPSSrr: {
946 unsigned Imm =
MI->getOperand(3).getImm() & 0x7;
960 case X86::VMOVHLPSrr:
961 case X86::VUNPCKHPDrr:
965 case X86::MASKMOVDQU:
966 case X86::VMASKMOVDQU:
975 if (
MI->getDesc().isCommutable() &&
990 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
993 bool Is64Bits =
MI.getOpcode() != X86::TLS_addr32 &&
994 MI.getOpcode() != X86::TLS_base_addr32;
995 bool Is64BitsLP64 =
MI.getOpcode() == X86::TLS_addr64 ||
996 MI.getOpcode() == X86::TLS_base_addr64;
1000 switch (
MI.getOpcode()) {
1001 case X86::TLS_addr32:
1002 case X86::TLS_addr64:
1003 case X86::TLS_addrX32:
1006 case X86::TLS_base_addr32:
1009 case X86::TLS_base_addr64:
1010 case X86::TLS_base_addrX32:
1018 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
1030 if (NeedsPadding && Is64BitsLP64)
1056 EmitAndCountInstruction(
1091 EmitAndCountInstruction(
1106 unsigned MaxNopLength = 1;
1107 if (Subtarget->is64Bit()) {
1110 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
1112 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
1114 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
1118 }
if (Subtarget->is32Bit())
1122 NumBytes =
std::min(NumBytes, MaxNopLength);
1125 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
1126 IndexReg = Displacement = SegmentReg = 0;
1139 Opc = X86::XCHG16ar;
1154 IndexReg = X86::RAX;
1160 IndexReg = X86::RAX;
1171 IndexReg = X86::RAX;
1177 IndexReg = X86::RAX;
1183 IndexReg = X86::RAX;
1184 SegmentReg = X86::CS;
1188 unsigned NumPrefixes =
std::min(NumBytes - NopSize, 5U);
1189 NopSize += NumPrefixes;
1190 for (
unsigned i = 0;
i != NumPrefixes; ++
i)
1208 .addImm(Displacement)
1209 .addReg(SegmentReg),
1213 assert(NopSize <= NumBytes &&
"We overemitted?");
1220 unsigned NopsToEmit = NumBytes;
1223 NumBytes -=
emitNop(OS, NumBytes, Subtarget);
1224 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
1229 X86MCInstLower &MCIL) {
1230 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
1235 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1241 unsigned CallOpcode;
1242 switch (CallTarget.
getType()) {
1245 CallTargetMCOp = MCIL.LowerSymbolOperand(
1246 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
1247 CallOpcode = X86::CALL64pcrel32;
1255 CallOpcode = X86::CALL64pcrel32;
1265 "yet implemented.");
1267 CallOpcode = X86::CALL64r;
1277 CallInst.addOperand(CallTargetMCOp);
1289 void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
1290 X86MCInstLower &MCIL) {
1301 unsigned OperandsBeginIdx = 4;
1311 MI.setOpcode(Opcode);
1313 if (DefRegister != X86::NoRegister)
1319 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, *
I))
1320 MI.addOperand(*MaybeOperand);
1327 X86MCInstLower &MCIL) {
1328 bool Is64Bits = Subtarget->is64Bit();
1334 EmitAndCountInstruction(
1335 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1339 void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
1346 const auto &
Reg =
MI.getOperand(0).getReg();
1351 bool OrShadowOffset;
1353 AccessInfo.CompileKernel, &ShadowBase,
1354 &MappingScale, &OrShadowOffset);
1358 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
1359 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
1364 "OrShadowOffset is not supported with optimized callbacks");
1366 EmitAndCountInstruction(
1373 X86MCInstLower &MCIL) {
1378 unsigned MinSize =
MI.getOperand(0).getImm();
1379 unsigned Opcode =
MI.getOperand(1).getImm();
1384 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1392 if (
Code.size() < MinSize) {
1393 if (MinSize == 2 && Subtarget->is32Bit() &&
1395 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
1403 }
else if (MinSize == 2 && Opcode == X86::PUSH64r) {
1412 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1430 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1431 SMShadowTracker.reset(NumShadowBytes);
1437 X86MCInstLower &MCIL) {
1438 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1450 unsigned ScratchIdx = opers.getNextScratchIdx();
1451 unsigned EncodedBytes = 0;
1468 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1469 MCIL.GetSymbolFromOperand(CalleeMO));
1475 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1481 EmitAndCountInstruction(
1486 "Lowering patchpoint with thunks not yet implemented.");
1487 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1491 unsigned NumBytes = opers.getNumPatchBytes();
1492 assert(NumBytes >= EncodedBytes &&
1493 "Patchpoint can't request size less than the length of a call.");
1498 void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1499 X86MCInstLower &MCIL) {
1500 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1525 OutStreamer->AddComment(
"# XRay Custom Event Log");
1536 const Register DestRegs[] = {X86::RDI, X86::RSI};
1537 bool UsedMask[] = {
false,
false};
1546 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1547 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1548 assert(
Op->isReg() &&
"Only support arguments in registers");
1550 if (SrcRegs[
I] != DestRegs[
I]) {
1552 EmitAndCountInstruction(
1563 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1564 if (SrcRegs[
I] != DestRegs[
I])
1565 EmitAndCountInstruction(
1577 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1580 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1582 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1586 OutStreamer->AddComment(
"xray custom event end.");
1594 void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1595 X86MCInstLower &MCIL) {
1596 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1621 OutStreamer->AddComment(
"# XRay Typed Event Log");
1633 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1634 bool UsedMask[] = {
false,
false,
false};
1643 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1644 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1646 assert(
Op->isReg() &&
"Only supports arguments in registers");
1648 if (SrcRegs[
I] != DestRegs[
I]) {
1650 EmitAndCountInstruction(
1666 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1668 EmitAndCountInstruction(
1680 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1683 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1685 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1695 void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1696 X86MCInstLower &MCIL) {
1701 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1703 if (
F.getFnAttribute(
"patchable-function-entry")
1705 .getAsInteger(10, Num))
1736 X86MCInstLower &MCIL) {
1756 unsigned OpCode =
MI.getOperand(0).getImm();
1758 Ret.setOpcode(OpCode);
1760 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1761 Ret.addOperand(*MaybeOperand);
1767 void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1768 X86MCInstLower &MCIL) {
1790 unsigned OpCode =
MI.getOperand(0).getImm();
1799 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1821 if (!
Op.isCPI() ||
Op.getOffset() != 0)
1825 MI.getParent()->getParent()->getConstantPool()->getConstants();
1838 std::string Comment;
1845 auto GetRegisterName = [](
unsigned RegNum) ->
StringRef {
1855 SrcOp1.
isReg() ? GetRegisterName(SrcOp1.
getReg()) :
"mem";
1857 SrcOp2.
isReg() ? GetRegisterName(SrcOp2.
getReg()) :
"mem";
1861 if (Src1Name == Src2Name)
1862 for (
int i = 0,
e = ShuffleMask.size();
i !=
e; ++
i)
1863 if (ShuffleMask[
i] >=
e)
1864 ShuffleMask[
i] -=
e;
1872 if (SrcOp1Idx > 1) {
1873 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) &&
"Unexpected writemask");
1876 if (WriteMaskOp.
isReg()) {
1877 CS <<
" {%" << GetRegisterName(WriteMaskOp.
getReg()) <<
"}";
1879 if (SrcOp1Idx == 2) {
1887 for (
int i = 0,
e = ShuffleMask.size();
i !=
e; ++
i) {
1897 bool isSrc1 = ShuffleMask[
i] < (
int)
e;
1898 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1900 bool IsFirst =
true;
1902 (ShuffleMask[
i] < (
int)
e) == isSrc1) {
1910 CS << ShuffleMask[
i] % (
int)
e;
1944 if (isa<UndefValue>(COp)) {
1946 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1948 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1963 switch (
MI->getOpcode()) {
1964 case X86::SEH_PushReg:
1967 case X86::SEH_StackAlloc:
1970 case X86::SEH_StackAlign:
1973 case X86::SEH_SetFrame:
1974 assert(
MI->getOperand(1).getImm() == 0 &&
1975 ".cv_fpo_setframe takes no offset");
1978 case X86::SEH_EndPrologue:
1981 case X86::SEH_SaveReg:
1982 case X86::SEH_SaveXMM:
1983 case X86::SEH_PushFrame:
1993 switch (
MI->getOpcode()) {
1994 case X86::SEH_PushReg:
1998 case X86::SEH_SaveReg:
2000 MI->getOperand(1).getImm());
2003 case X86::SEH_SaveXMM:
2005 MI->getOperand(1).getImm());
2008 case X86::SEH_StackAlloc:
2009 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
2012 case X86::SEH_SetFrame:
2014 MI->getOperand(1).getImm());
2017 case X86::SEH_PushFrame:
2018 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
2021 case X86::SEH_EndPrologue:
2031 if (
Info.RegClass == X86::VR128RegClassID ||
2032 Info.RegClass == X86::VR128XRegClassID)
2034 if (
Info.RegClass == X86::VR256RegClassID ||
2035 Info.RegClass == X86::VR256XRegClassID)
2037 if (
Info.RegClass == X86::VR512RegClassID)
2044 switch (
MI->getOpcode()) {
2049 case X86::VPSHUFBrm:
2050 case X86::VPSHUFBYrm:
2051 case X86::VPSHUFBZ128rm:
2052 case X86::VPSHUFBZ128rmk:
2053 case X86::VPSHUFBZ128rmkz:
2054 case X86::VPSHUFBZ256rm:
2055 case X86::VPSHUFBZ256rmk:
2056 case X86::VPSHUFBZ256rmkz:
2057 case X86::VPSHUFBZrm:
2058 case X86::VPSHUFBZrmk:
2059 case X86::VPSHUFBZrmkz: {
2060 unsigned SrcIdx = 1;
2072 "Unexpected number of operands!");
2085 case X86::VPERMILPSrm:
2086 case X86::VPERMILPSYrm:
2087 case X86::VPERMILPSZ128rm:
2088 case X86::VPERMILPSZ128rmk:
2089 case X86::VPERMILPSZ128rmkz:
2090 case X86::VPERMILPSZ256rm:
2091 case X86::VPERMILPSZ256rmk:
2092 case X86::VPERMILPSZ256rmkz:
2093 case X86::VPERMILPSZrm:
2094 case X86::VPERMILPSZrmk:
2095 case X86::VPERMILPSZrmkz:
2096 case X86::VPERMILPDrm:
2097 case X86::VPERMILPDYrm:
2098 case X86::VPERMILPDZ128rm:
2099 case X86::VPERMILPDZ128rmk:
2100 case X86::VPERMILPDZ128rmkz:
2101 case X86::VPERMILPDZ256rm:
2102 case X86::VPERMILPDZ256rmk:
2103 case X86::VPERMILPDZ256rmkz:
2104 case X86::VPERMILPDZrm:
2105 case X86::VPERMILPDZrmk:
2106 case X86::VPERMILPDZrmkz: {
2108 switch (
MI->getOpcode()) {
2110 case X86::VPERMILPSrm:
2111 case X86::VPERMILPSYrm:
2112 case X86::VPERMILPSZ128rm:
2113 case X86::VPERMILPSZ256rm:
2114 case X86::VPERMILPSZrm:
2115 case X86::VPERMILPSZ128rmkz:
2116 case X86::VPERMILPSZ256rmkz:
2117 case X86::VPERMILPSZrmkz:
2118 case X86::VPERMILPSZ128rmk:
2119 case X86::VPERMILPSZ256rmk:
2120 case X86::VPERMILPSZrmk:
2123 case X86::VPERMILPDrm:
2124 case X86::VPERMILPDYrm:
2125 case X86::VPERMILPDZ128rm:
2126 case X86::VPERMILPDZ256rm:
2127 case X86::VPERMILPDZrm:
2128 case X86::VPERMILPDZ128rmkz:
2129 case X86::VPERMILPDZ256rmkz:
2130 case X86::VPERMILPDZrmkz:
2131 case X86::VPERMILPDZ128rmk:
2132 case X86::VPERMILPDZ256rmk:
2133 case X86::VPERMILPDZrmk:
2138 unsigned SrcIdx = 1;
2150 "Unexpected number of operands!");
2163 case X86::VPERMIL2PDrm:
2164 case X86::VPERMIL2PSrm:
2165 case X86::VPERMIL2PDYrm:
2166 case X86::VPERMIL2PSYrm: {
2168 "Unexpected number of operands!");
2171 if (!CtrlOp.
isImm())
2175 switch (
MI->getOpcode()) {
2177 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
2178 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
2192 case X86::VPPERMrrm: {
2194 "Unexpected number of operands!");
2207 case X86::MMX_MOVQ64rm: {
2209 "Unexpected number of operands!");
2211 std::string Comment;
2215 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
2216 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
2223 #define MOV_CASE(Prefix, Suffix) \
2224 case X86::Prefix##MOVAPD##Suffix##rm: \
2225 case X86::Prefix##MOVAPS##Suffix##rm: \
2226 case X86::Prefix##MOVUPD##Suffix##rm: \
2227 case X86::Prefix##MOVUPS##Suffix##rm: \
2228 case X86::Prefix##MOVDQA##Suffix##rm: \
2229 case X86::Prefix##MOVDQU##Suffix##rm:
2231 #define MOV_AVX512_CASE(Suffix) \
2232 case X86::VMOVDQA64##Suffix##rm: \
2233 case X86::VMOVDQA32##Suffix##rm: \
2234 case X86::VMOVDQU64##Suffix##rm: \
2235 case X86::VMOVDQU32##Suffix##rm: \
2236 case X86::VMOVDQU16##Suffix##rm: \
2237 case X86::VMOVDQU8##Suffix##rm: \
2238 case X86::VMOVAPS##Suffix##rm: \
2239 case X86::VMOVAPD##Suffix##rm: \
2240 case X86::VMOVUPS##Suffix##rm: \
2241 case X86::VMOVUPD##Suffix##rm:
2243 #define CASE_ALL_MOV_RM() \
2247 MOV_AVX512_CASE(Z) \
2248 MOV_AVX512_CASE(Z256) \
2249 MOV_AVX512_CASE(Z128)
2254 case X86::VBROADCASTF128:
2255 case X86::VBROADCASTI128:
2256 case X86::VBROADCASTF32X4Z256rm:
2257 case X86::VBROADCASTF32X4rm:
2258 case X86::VBROADCASTF32X8rm:
2259 case X86::VBROADCASTF64X2Z128rm:
2260 case X86::VBROADCASTF64X2rm:
2261 case X86::VBROADCASTF64X4rm:
2262 case X86::VBROADCASTI32X4Z256rm:
2263 case X86::VBROADCASTI32X4rm:
2264 case X86::VBROADCASTI32X8rm:
2265 case X86::VBROADCASTI64X2Z128rm:
2266 case X86::VBROADCASTI64X2rm:
2267 case X86::VBROADCASTI64X4rm:
2269 "Unexpected number of operands!");
2273 switch (
MI->getOpcode()) {
2274 case X86::VBROADCASTF128: NumLanes = 2;
break;
2275 case X86::VBROADCASTI128: NumLanes = 2;
break;
2276 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2;
break;
2277 case X86::VBROADCASTF32X4rm: NumLanes = 4;
break;
2278 case X86::VBROADCASTF32X8rm: NumLanes = 2;
break;
2279 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2;
break;
2280 case X86::VBROADCASTF64X2rm: NumLanes = 4;
break;
2281 case X86::VBROADCASTF64X4rm: NumLanes = 2;
break;
2282 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2;
break;
2283 case X86::VBROADCASTI32X4rm: NumLanes = 4;
break;
2284 case X86::VBROADCASTI32X8rm: NumLanes = 2;
break;
2285 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2;
break;
2286 case X86::VBROADCASTI64X2rm: NumLanes = 4;
break;
2287 case X86::VBROADCASTI64X4rm: NumLanes = 2;
break;
2290 std::string Comment;
2294 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
2296 for (
int l = 0;
l != NumLanes; ++
l) {
2297 for (
int i = 0, NumElements = CDS->getNumElements();
i < NumElements;
2299 if (
i != 0 ||
l != 0)
2301 if (CDS->getElementType()->isIntegerTy())
2303 else if (CDS->getElementType()->isHalfTy() ||
2304 CDS->getElementType()->isFloatTy() ||
2305 CDS->getElementType()->isDoubleTy())
2313 }
else if (
auto *CV = dyn_cast<ConstantVector>(
C)) {
2315 for (
int l = 0;
l != NumLanes; ++
l) {
2316 for (
int i = 0, NumOperands = CV->getNumOperands();
i < NumOperands;
2318 if (
i != 0 ||
l != 0)
2329 case X86::MOVDDUPrm:
2330 case X86::VMOVDDUPrm:
2331 case X86::VMOVDDUPZ128rm:
2332 case X86::VBROADCASTSSrm:
2333 case X86::VBROADCASTSSYrm:
2334 case X86::VBROADCASTSSZ128rm:
2335 case X86::VBROADCASTSSZ256rm:
2336 case X86::VBROADCASTSSZrm:
2337 case X86::VBROADCASTSDYrm:
2338 case X86::VBROADCASTSDZ256rm:
2339 case X86::VBROADCASTSDZrm:
2340 case X86::VPBROADCASTBrm:
2341 case X86::VPBROADCASTBYrm:
2342 case X86::VPBROADCASTBZ128rm:
2343 case X86::VPBROADCASTBZ256rm:
2344 case X86::VPBROADCASTBZrm:
2345 case X86::VPBROADCASTDrm:
2346 case X86::VPBROADCASTDYrm:
2347 case X86::VPBROADCASTDZ128rm:
2348 case X86::VPBROADCASTDZ256rm:
2349 case X86::VPBROADCASTDZrm:
2350 case X86::VPBROADCASTQrm:
2351 case X86::VPBROADCASTQYrm:
2352 case X86::VPBROADCASTQZ128rm:
2353 case X86::VPBROADCASTQZ256rm:
2354 case X86::VPBROADCASTQZrm:
2355 case X86::VPBROADCASTWrm:
2356 case X86::VPBROADCASTWYrm:
2357 case X86::VPBROADCASTWZ128rm:
2358 case X86::VPBROADCASTWZ256rm:
2359 case X86::VPBROADCASTWZrm:
2361 "Unexpected number of operands!");
2364 switch (
MI->getOpcode()) {
2366 case X86::MOVDDUPrm: NumElts = 2;
break;
2367 case X86::VMOVDDUPrm: NumElts = 2;
break;
2368 case X86::VMOVDDUPZ128rm: NumElts = 2;
break;
2369 case X86::VBROADCASTSSrm: NumElts = 4;
break;
2370 case X86::VBROADCASTSSYrm: NumElts = 8;
break;
2371 case X86::VBROADCASTSSZ128rm: NumElts = 4;
break;
2372 case X86::VBROADCASTSSZ256rm: NumElts = 8;
break;
2373 case X86::VBROADCASTSSZrm: NumElts = 16;
break;
2374 case X86::VBROADCASTSDYrm: NumElts = 4;
break;
2375 case X86::VBROADCASTSDZ256rm: NumElts = 4;
break;
2376 case X86::VBROADCASTSDZrm: NumElts = 8;
break;
2377 case X86::VPBROADCASTBrm: NumElts = 16;
break;
2378 case X86::VPBROADCASTBYrm: NumElts = 32;
break;
2379 case X86::VPBROADCASTBZ128rm: NumElts = 16;
break;
2380 case X86::VPBROADCASTBZ256rm: NumElts = 32;
break;
2381 case X86::VPBROADCASTBZrm: NumElts = 64;
break;
2382 case X86::VPBROADCASTDrm: NumElts = 4;
break;
2383 case X86::VPBROADCASTDYrm: NumElts = 8;
break;
2384 case X86::VPBROADCASTDZ128rm: NumElts = 4;
break;
2385 case X86::VPBROADCASTDZ256rm: NumElts = 8;
break;
2386 case X86::VPBROADCASTDZrm: NumElts = 16;
break;
2387 case X86::VPBROADCASTQrm: NumElts = 2;
break;
2388 case X86::VPBROADCASTQYrm: NumElts = 4;
break;
2389 case X86::VPBROADCASTQZ128rm: NumElts = 2;
break;
2390 case X86::VPBROADCASTQZ256rm: NumElts = 4;
break;
2391 case X86::VPBROADCASTQZrm: NumElts = 8;
break;
2392 case X86::VPBROADCASTWrm: NumElts = 8;
break;
2393 case X86::VPBROADCASTWYrm: NumElts = 16;
break;
2394 case X86::VPBROADCASTWZ128rm: NumElts = 8;
break;
2395 case X86::VPBROADCASTWZ256rm: NumElts = 16;
break;
2396 case X86::VPBROADCASTWZrm: NumElts = 32;
break;
2399 std::string Comment;
2404 for (
int i = 0;
i != NumElts; ++
i) {
2420 X86MCInstLower MCInstLowering(*
MF, *
this);
2424 if (
MI->getOpcode() == X86::OR64rm) {
2425 for (
auto &Opd :
MI->operands()) {
2426 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2427 "swift_async_extendedFramePointerFlags") {
2428 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2437 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2444 switch (
MI->getOpcode()) {
2445 case TargetOpcode::DBG_VALUE:
2449 case X86::Int_MemBarrier:
2454 case X86::EH_RETURN64: {
2474 case X86::ENDBR64: {
2483 MCInstLowering.Lower(
MI, Inst);
2484 EmitAndCountInstruction(Inst);
2495 case X86::TAILJMPd_CC:
2496 case X86::TAILJMPr64:
2497 case X86::TAILJMPm64:
2498 case X86::TAILJMPd64:
2499 case X86::TAILJMPd64_CC:
2500 case X86::TAILJMPr64_REX:
2501 case X86::TAILJMPm64_REX:
2506 case X86::TLS_addr32:
2507 case X86::TLS_addr64:
2508 case X86::TLS_addrX32:
2509 case X86::TLS_base_addr32:
2510 case X86::TLS_base_addr64:
2511 case X86::TLS_base_addrX32:
2512 return LowerTlsAddr(MCInstLowering, *
MI);
2514 case X86::MOVPC32r: {
2525 EmitAndCountInstruction(
2531 bool hasFP = FrameLowering->
hasFP(*
MF);
2534 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2539 if (HasActiveDwarfFrame && !hasFP) {
2540 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2547 EmitAndCountInstruction(
2550 if (HasActiveDwarfFrame && !hasFP) {
2556 case X86::ADD32ri: {
2572 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2583 .addReg(
MI->getOperand(0).getReg())
2584 .
addReg(
MI->getOperand(1).getReg())
2588 case TargetOpcode::STATEPOINT:
2589 return LowerSTATEPOINT(*
MI, MCInstLowering);
2591 case TargetOpcode::FAULTING_OP:
2592 return LowerFAULTING_OP(*
MI, MCInstLowering);
2594 case TargetOpcode::FENTRY_CALL:
2595 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2597 case TargetOpcode::PATCHABLE_OP:
2598 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2601 return LowerSTACKMAP(*
MI);
2604 return LowerPATCHPOINT(*
MI, MCInstLowering);
2606 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2607 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2609 case TargetOpcode::PATCHABLE_RET:
2610 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2612 case TargetOpcode::PATCHABLE_TAIL_CALL:
2613 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2615 case TargetOpcode::PATCHABLE_EVENT_CALL:
2616 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2618 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2619 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2621 case X86::MORESTACK_RET:
2625 case X86::ASAN_CHECK_MEMACCESS:
2626 return LowerASAN_CHECK_MEMACCESS(*
MI);
2628 case X86::MORESTACK_RET_RESTORE_R10:
2631 EmitAndCountInstruction(
2632 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2635 case X86::SEH_PushReg:
2636 case X86::SEH_SaveReg:
2637 case X86::SEH_SaveXMM:
2638 case X86::SEH_StackAlloc:
2639 case X86::SEH_StackAlign:
2640 case X86::SEH_SetFrame:
2641 case X86::SEH_PushFrame:
2642 case X86::SEH_EndPrologue:
2643 EmitSEHInstruction(
MI);
2646 case X86::SEH_Epilogue: {
2655 if (!
MBBI->isPseudo()) {
2663 case X86::UBSAN_UD1:
2668 .addReg(X86::NoRegister)
2669 .addImm(
MI->getOperand(0).getImm())
2670 .
addReg(X86::NoRegister));
2675 MCInstLowering.Lower(
MI, TmpInst);
2692 EmitAndCountInstruction(TmpInst);