70 std::optional<MCOperand> LowerMachineOperand(
const MachineInstr *
MI,
108void X86AsmPrinter::StackMapShadowTracker::count(
MCInst &Inst,
115 CurrentShadowSize +=
Code.size();
116 if (CurrentShadowSize >= RequiredShadowSize)
121void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
123 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
125 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
130void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
137 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
153 "Isn't a symbol reference");
169 Suffix =
"$non_lazy_ptr";
174 Name +=
DL.getPrivateGlobalPrefix();
181 }
else if (MO.
isMBB()) {
188 Sym = Ctx.getOrCreateSymbol(
Name);
199 if (!StubSym.getPointer()) {
209 getMachOMMI().getGVStubEntry(
Sym);
227 const MCExpr *Expr =
nullptr;
304 assert(MAI.doesSetDirectiveSuppressReloc());
326 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
329std::optional<MCOperand>
367 Opcode = X86::JMP32r;
370 Opcode = X86::JMP32m;
372 case X86::TAILJMPr64:
373 Opcode = X86::JMP64r;
375 case X86::TAILJMPm64:
376 Opcode = X86::JMP64m;
378 case X86::TAILJMPr64_REX:
379 Opcode = X86::JMP64r_REX;
381 case X86::TAILJMPm64_REX:
382 Opcode = X86::JMP64m_REX;
385 case X86::TAILJMPd64:
388 case X86::TAILJMPd_CC:
389 case X86::TAILJMPd64_CC:
401 if (
auto MaybeMCOp = LowerMachineOperand(
MI, MO))
404 bool In64BitMode =
AsmPrinter.getSubtarget().is64Bit();
421 "Unexpected # of LEA operands");
423 "LEA has segment specified!");
428 case X86::MULX64Hrm: {
433 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
434 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
435 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
436 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
449 case X86::CALL64pcrel32:
453 case X86::EH_RETURN64: {
458 case X86::CLEANUPRET: {
464 case X86::CATCHRET: {
467 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
476 case X86::TAILJMPr64:
477 case X86::TAILJMPr64_REX:
479 case X86::TAILJMPd64:
483 case X86::TAILJMPd_CC:
484 case X86::TAILJMPd64_CC:
489 case X86::TAILJMPm64:
490 case X86::TAILJMPm64_REX:
492 "Unexpected number of operands!");
495 case X86::MASKMOVDQU:
496 case X86::VMASKMOVDQU:
511 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->
isDead())
520void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
523 bool Is64Bits =
MI.getOpcode() != X86::TLS_addr32 &&
524 MI.getOpcode() != X86::TLS_base_addr32;
525 bool Is64BitsLP64 =
MI.getOpcode() == X86::TLS_addr64 ||
526 MI.getOpcode() == X86::TLS_base_addr64;
530 switch (
MI.getOpcode()) {
531 case X86::TLS_addr32:
532 case X86::TLS_addr64:
533 case X86::TLS_addrX32:
536 case X86::TLS_base_addr32:
539 case X86::TLS_base_addr64:
540 case X86::TLS_base_addrX32:
548 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
560 if (NeedsPadding && Is64BitsLP64)
586 EmitAndCountInstruction(
621 EmitAndCountInstruction(
636 unsigned MaxNopLength = 1;
637 if (Subtarget->is64Bit()) {
640 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
642 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
644 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
648 }
if (Subtarget->is32Bit())
652 NumBytes = std::min(NumBytes, MaxNopLength);
655 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
656 IndexReg = Displacement = SegmentReg = 0;
714 SegmentReg = X86::CS;
718 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
719 NopSize += NumPrefixes;
720 for (
unsigned i = 0; i != NumPrefixes; ++i)
721 OS.emitBytes(
"\x66");
738 .addImm(Displacement)
743 assert(NopSize <= NumBytes &&
"We overemitted?");
750 unsigned NopsToEmit = NumBytes;
753 NumBytes -=
emitNop(
OS, NumBytes, Subtarget);
754 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
759 X86MCInstLower &MCIL) {
760 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
765 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
772 switch (CallTarget.
getType()) {
775 CallTargetMCOp = MCIL.LowerSymbolOperand(
776 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
777 CallOpcode = X86::CALL64pcrel32;
785 CallOpcode = X86::CALL64pcrel32;
797 CallOpcode = X86::CALL64r;
807 CallInst.addOperand(CallTargetMCOp);
819void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
820 X86MCInstLower &MCIL) {
831 unsigned OperandsBeginIdx = 4;
841 MI.setOpcode(Opcode);
843 if (DefRegister != X86::NoRegister)
848 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, MO))
849 MI.addOperand(*MaybeOperand);
856 X86MCInstLower &MCIL) {
857 bool Is64Bits = Subtarget->is64Bit();
863 EmitAndCountInstruction(
864 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
869 assert(std::next(
MI.getIterator())->isCall() &&
870 "KCFI_CHECK not followed by a call instruction");
877 int64_t PrefixNops = 0;
888 const Register AddrReg =
MI.getOperand(0).getReg();
892 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
893 EmitAndCountInstruction(
896 .addReg(X86::NoRegister)
900 .addReg(X86::NoRegister)
901 .addImm(-(PrefixNops + 4))
902 .addReg(X86::NoRegister));
905 EmitAndCountInstruction(
917void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
924 const auto &
Reg =
MI.getOperand(0).getReg();
931 AccessInfo.CompileKernel, &ShadowBase,
932 &MappingScale, &OrShadowOffset);
936 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
937 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
942 "OrShadowOffset is not supported with optimized callbacks");
944 EmitAndCountInstruction(
951 X86MCInstLower &MCIL) {
956 unsigned MinSize =
MI.getOperand(0).getImm();
957 unsigned Opcode =
MI.getOperand(1).getImm();
960 bool EmptyInst = (Opcode == TargetOpcode::PATCHABLE_OP);
965 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
974 if (
Code.size() < MinSize) {
975 if (MinSize == 2 && Subtarget->is32Bit() &&
977 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
985 }
else if (MinSize == 2 && Opcode == X86::PUSH64r) {
994 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1012 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1013 SMShadowTracker.reset(NumShadowBytes);
1019 X86MCInstLower &MCIL) {
1020 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1032 unsigned ScratchIdx = opers.getNextScratchIdx();
1033 unsigned EncodedBytes = 0;
1050 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1051 MCIL.GetSymbolFromOperand(CalleeMO));
1057 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1063 EmitAndCountInstruction(
1068 "Lowering patchpoint with thunks not yet implemented.");
1069 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1073 unsigned NumBytes = opers.getNumPatchBytes();
1074 assert(NumBytes >= EncodedBytes &&
1075 "Patchpoint can't request size less than the length of a call.");
1080void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1081 X86MCInstLower &MCIL) {
1082 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1107 OutStreamer->AddComment(
"# XRay Custom Event Log");
1118 const Register DestRegs[] = {X86::RDI, X86::RSI};
1119 bool UsedMask[] = {
false,
false};
1128 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1129 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1130 assert(
Op->isReg() &&
"Only support arguments in registers");
1133 if (SrcRegs[
I] != DestRegs[
I]) {
1135 EmitAndCountInstruction(
1146 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1147 if (SrcRegs[
I] != DestRegs[
I])
1148 EmitAndCountInstruction(
1160 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1163 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1165 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1169 OutStreamer->AddComment(
"xray custom event end.");
1177void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1178 X86MCInstLower &MCIL) {
1179 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1204 OutStreamer->AddComment(
"# XRay Typed Event Log");
1216 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1217 bool UsedMask[] = {
false,
false,
false};
1226 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1227 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1229 assert(
Op->isReg() &&
"Only supports arguments in registers");
1232 if (SrcRegs[
I] != DestRegs[
I]) {
1234 EmitAndCountInstruction(
1250 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1252 EmitAndCountInstruction(
1264 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1267 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1269 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1279void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1280 X86MCInstLower &MCIL) {
1285 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1287 if (
F.getFnAttribute(
"patchable-function-entry")
1289 .getAsInteger(10, Num))
1320 X86MCInstLower &MCIL) {
1340 unsigned OpCode =
MI.getOperand(0).getImm();
1342 Ret.setOpcode(OpCode);
1344 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1345 Ret.addOperand(*MaybeOperand);
1351void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1352 X86MCInstLower &MCIL) {
1374 unsigned OpCode =
MI.getOperand(0).getImm();
1383 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1405 if (!
Op.isCPI() ||
Op.getOffset() != 0)
1409 MI.getParent()->getParent()->getConstantPool()->getConstants();
1422 std::string Comment;
1439 SrcOp1.
isReg() ? GetRegisterName(SrcOp1.
getReg()) :
"mem";
1441 SrcOp2.
isReg() ? GetRegisterName(SrcOp2.
getReg()) :
"mem";
1445 if (Src1Name == Src2Name)
1446 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i)
1447 if (ShuffleMask[i] >= e)
1448 ShuffleMask[i] -= e;
1456 if (SrcOp1Idx > 1) {
1457 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) &&
"Unexpected writemask");
1460 if (WriteMaskOp.
isReg()) {
1461 CS <<
" {%" << GetRegisterName(WriteMaskOp.
getReg()) <<
"}";
1463 if (SrcOp1Idx == 2) {
1471 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1481 bool isSrc1 = ShuffleMask[i] < (int)e;
1482 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1484 bool IsFirst =
true;
1486 (ShuffleMask[i] < (
int)e) == isSrc1) {
1494 CS << ShuffleMask[i] % (int)e;
1523 Flt.toString(Str, 0, 0);
1529 if (isa<UndefValue>(COp)) {
1531 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
1533 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
1535 }
else if (
auto *CDS = dyn_cast<ConstantDataSequential>(COp)) {
1536 Type *EltTy = CDS->getElementType();
1540 unsigned E = std::min(
BitWidth / EltBits, CDS->getNumElements());
1541 assert((
BitWidth % EltBits) == 0 &&
"Broadcast element size mismatch");
1542 for (
unsigned I = 0;
I !=
E; ++
I) {
1560 "SEH_ instruction Windows and UEFI only");
1566 switch (
MI->getOpcode()) {
1567 case X86::SEH_PushReg:
1570 case X86::SEH_StackAlloc:
1573 case X86::SEH_StackAlign:
1576 case X86::SEH_SetFrame:
1577 assert(
MI->getOperand(1).getImm() == 0 &&
1578 ".cv_fpo_setframe takes no offset");
1581 case X86::SEH_EndPrologue:
1584 case X86::SEH_SaveReg:
1585 case X86::SEH_SaveXMM:
1586 case X86::SEH_PushFrame:
1596 switch (
MI->getOpcode()) {
1597 case X86::SEH_PushReg:
1601 case X86::SEH_SaveReg:
1603 MI->getOperand(1).getImm());
1606 case X86::SEH_SaveXMM:
1608 MI->getOperand(1).getImm());
1611 case X86::SEH_StackAlloc:
1612 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
1615 case X86::SEH_SetFrame:
1617 MI->getOperand(1).getImm());
1620 case X86::SEH_PushFrame:
1621 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
1624 case X86::SEH_EndPrologue:
1634 if (
Info.RegClass == X86::VR128RegClassID ||
1635 Info.RegClass == X86::VR128XRegClassID)
1637 if (
Info.RegClass == X86::VR256RegClassID ||
1638 Info.RegClass == X86::VR256XRegClassID)
1640 if (
Info.RegClass == X86::VR512RegClassID)
1647 switch (
MI->getOpcode()) {
1652 case X86::VPSHUFBrm:
1653 case X86::VPSHUFBYrm:
1654 case X86::VPSHUFBZ128rm:
1655 case X86::VPSHUFBZ128rmk:
1656 case X86::VPSHUFBZ128rmkz:
1657 case X86::VPSHUFBZ256rm:
1658 case X86::VPSHUFBZ256rmk:
1659 case X86::VPSHUFBZ256rmkz:
1660 case X86::VPSHUFBZrm:
1661 case X86::VPSHUFBZrmk:
1662 case X86::VPSHUFBZrmkz: {
1663 unsigned SrcIdx = 1;
1675 "Unexpected number of operands!");
1688 case X86::VPERMILPSrm:
1689 case X86::VPERMILPSYrm:
1690 case X86::VPERMILPSZ128rm:
1691 case X86::VPERMILPSZ128rmk:
1692 case X86::VPERMILPSZ128rmkz:
1693 case X86::VPERMILPSZ256rm:
1694 case X86::VPERMILPSZ256rmk:
1695 case X86::VPERMILPSZ256rmkz:
1696 case X86::VPERMILPSZrm:
1697 case X86::VPERMILPSZrmk:
1698 case X86::VPERMILPSZrmkz:
1699 case X86::VPERMILPDrm:
1700 case X86::VPERMILPDYrm:
1701 case X86::VPERMILPDZ128rm:
1702 case X86::VPERMILPDZ128rmk:
1703 case X86::VPERMILPDZ128rmkz:
1704 case X86::VPERMILPDZ256rm:
1705 case X86::VPERMILPDZ256rmk:
1706 case X86::VPERMILPDZ256rmkz:
1707 case X86::VPERMILPDZrm:
1708 case X86::VPERMILPDZrmk:
1709 case X86::VPERMILPDZrmkz: {
1711 switch (
MI->getOpcode()) {
1713 case X86::VPERMILPSrm:
1714 case X86::VPERMILPSYrm:
1715 case X86::VPERMILPSZ128rm:
1716 case X86::VPERMILPSZ256rm:
1717 case X86::VPERMILPSZrm:
1718 case X86::VPERMILPSZ128rmkz:
1719 case X86::VPERMILPSZ256rmkz:
1720 case X86::VPERMILPSZrmkz:
1721 case X86::VPERMILPSZ128rmk:
1722 case X86::VPERMILPSZ256rmk:
1723 case X86::VPERMILPSZrmk:
1726 case X86::VPERMILPDrm:
1727 case X86::VPERMILPDYrm:
1728 case X86::VPERMILPDZ128rm:
1729 case X86::VPERMILPDZ256rm:
1730 case X86::VPERMILPDZrm:
1731 case X86::VPERMILPDZ128rmkz:
1732 case X86::VPERMILPDZ256rmkz:
1733 case X86::VPERMILPDZrmkz:
1734 case X86::VPERMILPDZ128rmk:
1735 case X86::VPERMILPDZ256rmk:
1736 case X86::VPERMILPDZrmk:
1741 unsigned SrcIdx = 1;
1753 "Unexpected number of operands!");
1766 case X86::VPERMIL2PDrm:
1767 case X86::VPERMIL2PSrm:
1768 case X86::VPERMIL2PDYrm:
1769 case X86::VPERMIL2PSYrm: {
1771 "Unexpected number of operands!");
1774 if (!CtrlOp.
isImm())
1778 switch (
MI->getOpcode()) {
1780 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
1781 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
1795 case X86::VPPERMrrm: {
1797 "Unexpected number of operands!");
1810 case X86::MMX_MOVQ64rm: {
1812 "Unexpected number of operands!");
1814 std::string Comment;
1818 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
1819 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
1826#define MOV_CASE(Prefix, Suffix) \
1827 case X86::Prefix##MOVAPD##Suffix##rm: \
1828 case X86::Prefix##MOVAPS##Suffix##rm: \
1829 case X86::Prefix##MOVUPD##Suffix##rm: \
1830 case X86::Prefix##MOVUPS##Suffix##rm: \
1831 case X86::Prefix##MOVDQA##Suffix##rm: \
1832 case X86::Prefix##MOVDQU##Suffix##rm:
1834#define MOV_AVX512_CASE(Suffix) \
1835 case X86::VMOVDQA64##Suffix##rm: \
1836 case X86::VMOVDQA32##Suffix##rm: \
1837 case X86::VMOVDQU64##Suffix##rm: \
1838 case X86::VMOVDQU32##Suffix##rm: \
1839 case X86::VMOVDQU16##Suffix##rm: \
1840 case X86::VMOVDQU8##Suffix##rm: \
1841 case X86::VMOVAPS##Suffix##rm: \
1842 case X86::VMOVAPD##Suffix##rm: \
1843 case X86::VMOVUPS##Suffix##rm: \
1844 case X86::VMOVUPD##Suffix##rm:
1846#define CASE_ALL_MOV_RM() \
1850 MOV_AVX512_CASE(Z) \
1851 MOV_AVX512_CASE(Z256) \
1852 MOV_AVX512_CASE(Z128)
1857 case X86::VBROADCASTF128:
1858 case X86::VBROADCASTI128:
1859 case X86::VBROADCASTF32X4Z256rm:
1860 case X86::VBROADCASTF32X4rm:
1861 case X86::VBROADCASTF32X8rm:
1862 case X86::VBROADCASTF64X2Z128rm:
1863 case X86::VBROADCASTF64X2rm:
1864 case X86::VBROADCASTF64X4rm:
1865 case X86::VBROADCASTI32X4Z256rm:
1866 case X86::VBROADCASTI32X4rm:
1867 case X86::VBROADCASTI32X8rm:
1868 case X86::VBROADCASTI64X2Z128rm:
1869 case X86::VBROADCASTI64X2rm:
1870 case X86::VBROADCASTI64X4rm:
1872 "Unexpected number of operands!");
1876 switch (
MI->getOpcode()) {
1877 case X86::VBROADCASTF128: NumLanes = 2;
break;
1878 case X86::VBROADCASTI128: NumLanes = 2;
break;
1879 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2;
break;
1880 case X86::VBROADCASTF32X4rm: NumLanes = 4;
break;
1881 case X86::VBROADCASTF32X8rm: NumLanes = 2;
break;
1882 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2;
break;
1883 case X86::VBROADCASTF64X2rm: NumLanes = 4;
break;
1884 case X86::VBROADCASTF64X4rm: NumLanes = 2;
break;
1885 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2;
break;
1886 case X86::VBROADCASTI32X4rm: NumLanes = 4;
break;
1887 case X86::VBROADCASTI32X8rm: NumLanes = 2;
break;
1888 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2;
break;
1889 case X86::VBROADCASTI64X2rm: NumLanes = 4;
break;
1890 case X86::VBROADCASTI64X4rm: NumLanes = 2;
break;
1893 std::string Comment;
1897 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
1899 for (
int l = 0; l != NumLanes; ++l) {
1900 for (
int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
1902 if (i != 0 || l != 0)
1904 if (CDS->getElementType()->isIntegerTy())
1906 else if (CDS->getElementType()->isHalfTy() ||
1907 CDS->getElementType()->isFloatTy() ||
1908 CDS->getElementType()->isDoubleTy())
1916 }
else if (
auto *CV = dyn_cast<ConstantVector>(
C)) {
1918 for (
int l = 0; l != NumLanes; ++l) {
1919 for (
int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
1921 if (i != 0 || l != 0)
1924 CV->getType()->getPrimitiveSizeInBits(), CS);
1933 case X86::MOVDDUPrm:
1934 case X86::VMOVDDUPrm:
1935 case X86::VMOVDDUPZ128rm:
1936 case X86::VBROADCASTSSrm:
1937 case X86::VBROADCASTSSYrm:
1938 case X86::VBROADCASTSSZ128rm:
1939 case X86::VBROADCASTSSZ256rm:
1940 case X86::VBROADCASTSSZrm:
1941 case X86::VBROADCASTSDYrm:
1942 case X86::VBROADCASTSDZ256rm:
1943 case X86::VBROADCASTSDZrm:
1944 case X86::VPBROADCASTBrm:
1945 case X86::VPBROADCASTBYrm:
1946 case X86::VPBROADCASTBZ128rm:
1947 case X86::VPBROADCASTBZ256rm:
1948 case X86::VPBROADCASTBZrm:
1949 case X86::VPBROADCASTDrm:
1950 case X86::VPBROADCASTDYrm:
1951 case X86::VPBROADCASTDZ128rm:
1952 case X86::VPBROADCASTDZ256rm:
1953 case X86::VPBROADCASTDZrm:
1954 case X86::VPBROADCASTQrm:
1955 case X86::VPBROADCASTQYrm:
1956 case X86::VPBROADCASTQZ128rm:
1957 case X86::VPBROADCASTQZ256rm:
1958 case X86::VPBROADCASTQZrm:
1959 case X86::VPBROADCASTWrm:
1960 case X86::VPBROADCASTWYrm:
1961 case X86::VPBROADCASTWZ128rm:
1962 case X86::VPBROADCASTWZ256rm:
1963 case X86::VPBROADCASTWZrm:
1965 "Unexpected number of operands!");
1967 int NumElts, EltBits;
1968 switch (
MI->getOpcode()) {
1970 case X86::MOVDDUPrm: NumElts = 2; EltBits = 64;
break;
1971 case X86::VMOVDDUPrm: NumElts = 2; EltBits = 64;
break;
1972 case X86::VMOVDDUPZ128rm: NumElts = 2; EltBits = 64;
break;
1973 case X86::VBROADCASTSSrm: NumElts = 4; EltBits = 32;
break;
1974 case X86::VBROADCASTSSYrm: NumElts = 8; EltBits = 32;
break;
1975 case X86::VBROADCASTSSZ128rm: NumElts = 4; EltBits = 32;
break;
1976 case X86::VBROADCASTSSZ256rm: NumElts = 8; EltBits = 32;
break;
1977 case X86::VBROADCASTSSZrm: NumElts = 16; EltBits = 32;
break;
1978 case X86::VBROADCASTSDYrm: NumElts = 4; EltBits = 64;
break;
1979 case X86::VBROADCASTSDZ256rm: NumElts = 4; EltBits = 64;
break;
1980 case X86::VBROADCASTSDZrm: NumElts = 8; EltBits = 64;
break;
1981 case X86::VPBROADCASTBrm: NumElts = 16; EltBits = 8;
break;
1982 case X86::VPBROADCASTBYrm: NumElts = 32; EltBits = 8;
break;
1983 case X86::VPBROADCASTBZ128rm: NumElts = 16; EltBits = 8;
break;
1984 case X86::VPBROADCASTBZ256rm: NumElts = 32; EltBits = 8;
break;
1985 case X86::VPBROADCASTBZrm: NumElts = 64; EltBits = 8;
break;
1986 case X86::VPBROADCASTDrm: NumElts = 4; EltBits = 32;
break;
1987 case X86::VPBROADCASTDYrm: NumElts = 8; EltBits = 32;
break;
1988 case X86::VPBROADCASTDZ128rm: NumElts = 4; EltBits = 32;
break;
1989 case X86::VPBROADCASTDZ256rm: NumElts = 8; EltBits = 32;
break;
1990 case X86::VPBROADCASTDZrm: NumElts = 16; EltBits = 32;
break;
1991 case X86::VPBROADCASTQrm: NumElts = 2; EltBits = 64;
break;
1992 case X86::VPBROADCASTQYrm: NumElts = 4; EltBits = 64;
break;
1993 case X86::VPBROADCASTQZ128rm: NumElts = 2; EltBits = 64;
break;
1994 case X86::VPBROADCASTQZ256rm: NumElts = 4; EltBits = 64;
break;
1995 case X86::VPBROADCASTQZrm: NumElts = 8; EltBits = 64;
break;
1996 case X86::VPBROADCASTWrm: NumElts = 8; EltBits = 16;
break;
1997 case X86::VPBROADCASTWYrm: NumElts = 16; EltBits = 16;
break;
1998 case X86::VPBROADCASTWZ128rm: NumElts = 8; EltBits = 16;
break;
1999 case X86::VPBROADCASTWZ256rm: NumElts = 16; EltBits = 16;
break;
2000 case X86::VPBROADCASTWZrm: NumElts = 32; EltBits = 16;
break;
2003 std::string Comment;
2008 for (
int i = 0; i != NumElts; ++i) {
2024 X86MCInstLower MCInstLowering(*
MF, *
this);
2028 if (
MI->getOpcode() == X86::OR64rm) {
2029 for (
auto &Opd :
MI->operands()) {
2030 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2031 "swift_async_extendedFramePointerFlags") {
2032 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2041 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2048 switch (
MI->getOpcode()) {
2049 case TargetOpcode::DBG_VALUE:
2052 case X86::EH_RETURN:
2053 case X86::EH_RETURN64: {
2060 case X86::CLEANUPRET: {
2066 case X86::CATCHRET: {
2073 case X86::ENDBR64: {
2082 MCInstLowering.Lower(
MI, Inst);
2083 EmitAndCountInstruction(Inst);
2091 case X86::TAILJMPd64:
2092 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2098 case X86::TAILJMPd_CC:
2099 case X86::TAILJMPr64:
2100 case X86::TAILJMPm64:
2101 case X86::TAILJMPd64_CC:
2102 case X86::TAILJMPr64_REX:
2103 case X86::TAILJMPm64_REX:
2108 case X86::TLS_addr32:
2109 case X86::TLS_addr64:
2110 case X86::TLS_addrX32:
2111 case X86::TLS_base_addr32:
2112 case X86::TLS_base_addr64:
2113 case X86::TLS_base_addrX32:
2114 return LowerTlsAddr(MCInstLowering, *
MI);
2116 case X86::MOVPC32r: {
2127 EmitAndCountInstruction(
2133 bool hasFP = FrameLowering->
hasFP(*
MF);
2136 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2141 if (HasActiveDwarfFrame && !hasFP) {
2142 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2150 EmitAndCountInstruction(
2153 if (HasActiveDwarfFrame && !hasFP) {
2159 case X86::ADD32ri: {
2175 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2186 .addReg(
MI->getOperand(0).getReg())
2187 .
addReg(
MI->getOperand(1).getReg())
2191 case TargetOpcode::STATEPOINT:
2192 return LowerSTATEPOINT(*
MI, MCInstLowering);
2194 case TargetOpcode::FAULTING_OP:
2195 return LowerFAULTING_OP(*
MI, MCInstLowering);
2197 case TargetOpcode::FENTRY_CALL:
2198 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2200 case TargetOpcode::PATCHABLE_OP:
2201 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2203 case TargetOpcode::STACKMAP:
2204 return LowerSTACKMAP(*
MI);
2206 case TargetOpcode::PATCHPOINT:
2207 return LowerPATCHPOINT(*
MI, MCInstLowering);
2209 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2210 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2212 case TargetOpcode::PATCHABLE_RET:
2213 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2215 case TargetOpcode::PATCHABLE_TAIL_CALL:
2216 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2218 case TargetOpcode::PATCHABLE_EVENT_CALL:
2219 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2221 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2222 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2224 case X86::MORESTACK_RET:
2228 case X86::KCFI_CHECK:
2229 return LowerKCFI_CHECK(*
MI);
2231 case X86::ASAN_CHECK_MEMACCESS:
2232 return LowerASAN_CHECK_MEMACCESS(*
MI);
2234 case X86::MORESTACK_RET_RESTORE_R10:
2237 EmitAndCountInstruction(
2238 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2241 case X86::SEH_PushReg:
2242 case X86::SEH_SaveReg:
2243 case X86::SEH_SaveXMM:
2244 case X86::SEH_StackAlloc:
2245 case X86::SEH_StackAlign:
2246 case X86::SEH_SetFrame:
2247 case X86::SEH_PushFrame:
2248 case X86::SEH_EndPrologue:
2249 EmitSEHInstruction(
MI);
2252 case X86::SEH_Epilogue: {
2262 if (
MBBI->isCall() || !
MBBI->isPseudo()) {
2270 case X86::UBSAN_UD1:
2275 .addReg(X86::NoRegister)
2276 .addImm(
MI->getOperand(0).getImm())
2277 .
addReg(X86::NoRegister));
2279 case X86::CALL64pcrel32:
2280 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2286 MCInstLowering.Lower(
MI, TmpInst);
2303 EmitAndCountInstruction(TmpInst);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printConstant(const APInt &Val, raw_ostream &CS)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
static unsigned getRegisterWidth(const MCOperandInfo &Info)
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
#define CASE_ALL_MOV_RM()
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumWords() const
Get the number of words.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
MCSymbol * CurrentFnBegin
TargetMachine & TM
Target machine description.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
StringRef getValueAsString() const
Return the attribute's value as a string.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasInternalLinkage() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool canRelaxRelocations() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, SmallVectorImpl< char > &CB, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
Encode the given Inst to bytes and append to CB.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
const MCAsmInfo * getAsmInfo() const
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
iterator insert(iterator I, const MCOperand &Op)
void setFlags(unsigned F)
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
void setAllowAutoPadding(bool v)
bool getAllowAutoPadding() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
This class is a data container for one entry in a MachineConstantPool.
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
const Constant * ConstVal
union llvm::MachineConstantPoolEntry::@195 Val
The constant itself.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
const MachineOperand & getOperand(unsigned i) const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
MI-level patchpoint operands.
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isUEFI() const
Tests whether the OS is UEFI.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
bool isHalfTy() const
Return true if this is 'half', a 16-bit IEEE fp type.
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
bool useIndirectThunkCalls() const
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
bool isX86_64ExtendedReg(unsigned RegNo)
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool isKMasked(uint64_t TSFlags)
bool optimizeToFixedRegisterOrShortImmediateForm(MCInst &MI)
bool optimizeMOV(MCInst &MI, bool In64BitMode)
Simplify things like MOV32rm to MOV32o32a.
bool optimizeMOVSX(MCInst &MI)
bool optimizeVPCMPWithImmediateOneOrSix(MCInst &MI)
bool optimizeShiftRotateWithImmediateOne(MCInst &MI)
bool optimizeInstFromVEX3ToVEX2(MCInst &MI, const MCInstrDesc &Desc)
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
bool optimizeINCDEC(MCInst &MI, bool In64BitMode)
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
NodeAddr< CodeNode * > Code
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
constexpr unsigned BitWidth
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.