67 std::optional<MCOperand> LowerMachineOperand(
const MachineInstr *
MI,
105void X86AsmPrinter::StackMapShadowTracker::count(
MCInst &Inst,
113 CurrentShadowSize +=
Code.size();
114 if (CurrentShadowSize >= RequiredShadowSize)
119void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
121 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
123 emitX86Nops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
128void X86AsmPrinter::EmitAndCountInstruction(
MCInst &Inst) {
135 : Ctx(mf.getContext()), MF(mf),
TM(mf.getTarget()), MAI(*
TM.getMCAsmInfo()),
151 "Isn't a symbol reference");
167 Suffix =
"$non_lazy_ptr";
172 Name +=
DL.getPrivateGlobalPrefix();
179 }
else if (MO.
isMBB()) {
186 Sym = Ctx.getOrCreateSymbol(
Name);
197 if (!StubSym.getPointer()) {
207 getMachOMMI().getGVStubEntry(Sym);
225 const MCExpr *Expr =
nullptr;
302 assert(MAI.doesSetDirectiveSuppressReloc());
332 "Unexpected instruction!");
336 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
349 unsigned NewOpcode = 0;
354 case X86::MOVSX16rr8:
355 if (Op0 == X86::AX && Op1 == X86::AL)
356 NewOpcode = X86::CBW;
358 case X86::MOVSX32rr16:
359 if (Op0 == X86::EAX && Op1 == X86::AX)
360 NewOpcode = X86::CWDE;
362 case X86::MOVSX64rr32:
363 if (Op0 == X86::RAX && Op1 == X86::EAX)
364 NewOpcode = X86::CDQE;
368 if (NewOpcode != 0) {
379 if (
Printer.getSubtarget().is64Bit())
383 unsigned AddrBase = IsStore;
384 unsigned RegOp = IsStore ? 0 : 5;
385 unsigned AddrOp = AddrBase + 3;
393 "Unexpected instruction!");
397 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
403 bool Absolute =
true;
427 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
430std::optional<MCOperand>
468 Opcode = X86::JMP32r;
471 Opcode = X86::JMP32m;
473 case X86::TAILJMPr64:
474 Opcode = X86::JMP64r;
476 case X86::TAILJMPm64:
477 Opcode = X86::JMP64m;
479 case X86::TAILJMPr64_REX:
480 Opcode = X86::JMP64r_REX;
482 case X86::TAILJMPm64_REX:
483 Opcode = X86::JMP64m_REX;
486 case X86::TAILJMPd64:
489 case X86::TAILJMPd_CC:
490 case X86::TAILJMPd64_CC:
502 if (
auto MaybeMCOp = LowerMachineOperand(
MI, MO))
513 "Unexpected # of LEA operands");
515 "LEA has segment specified!");
521 case X86::MULX64Hrm: {
526 case X86::MULX32Hrr: NewOpc = X86::MULX32rr;
break;
527 case X86::MULX32Hrm: NewOpc = X86::MULX32rm;
break;
528 case X86::MULX64Hrr: NewOpc = X86::MULX64rr;
break;
529 case X86::MULX64Hrm: NewOpc = X86::MULX64rm;
break;
540 case X86::VMOVZPQILo2PQIrr:
542 case X86::VMOVAPDYrr:
544 case X86::VMOVAPSYrr:
546 case X86::VMOVDQAYrr:
548 case X86::VMOVDQUYrr:
550 case X86::VMOVUPDYrr:
552 case X86::VMOVUPSYrr: {
558 case X86::VMOVZPQILo2PQIrr: NewOpc = X86::VMOVPQI2QIrr;
break;
559 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV;
break;
560 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV;
break;
561 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV;
break;
562 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV;
break;
563 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV;
break;
564 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV;
break;
565 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV;
break;
566 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV;
break;
567 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV;
break;
568 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV;
break;
569 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV;
break;
570 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV;
break;
577 case X86::VMOVSSrr: {
583 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV;
break;
584 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV;
break;
591 case X86::VPCMPBZ128rmi:
case X86::VPCMPBZ128rmik:
592 case X86::VPCMPBZ128rri:
case X86::VPCMPBZ128rrik:
593 case X86::VPCMPBZ256rmi:
case X86::VPCMPBZ256rmik:
594 case X86::VPCMPBZ256rri:
case X86::VPCMPBZ256rrik:
595 case X86::VPCMPBZrmi:
case X86::VPCMPBZrmik:
596 case X86::VPCMPBZrri:
case X86::VPCMPBZrrik:
597 case X86::VPCMPDZ128rmi:
case X86::VPCMPDZ128rmik:
598 case X86::VPCMPDZ128rmib:
case X86::VPCMPDZ128rmibk:
599 case X86::VPCMPDZ128rri:
case X86::VPCMPDZ128rrik:
600 case X86::VPCMPDZ256rmi:
case X86::VPCMPDZ256rmik:
601 case X86::VPCMPDZ256rmib:
case X86::VPCMPDZ256rmibk:
602 case X86::VPCMPDZ256rri:
case X86::VPCMPDZ256rrik:
603 case X86::VPCMPDZrmi:
case X86::VPCMPDZrmik:
604 case X86::VPCMPDZrmib:
case X86::VPCMPDZrmibk:
605 case X86::VPCMPDZrri:
case X86::VPCMPDZrrik:
606 case X86::VPCMPQZ128rmi:
case X86::VPCMPQZ128rmik:
607 case X86::VPCMPQZ128rmib:
case X86::VPCMPQZ128rmibk:
608 case X86::VPCMPQZ128rri:
case X86::VPCMPQZ128rrik:
609 case X86::VPCMPQZ256rmi:
case X86::VPCMPQZ256rmik:
610 case X86::VPCMPQZ256rmib:
case X86::VPCMPQZ256rmibk:
611 case X86::VPCMPQZ256rri:
case X86::VPCMPQZ256rrik:
612 case X86::VPCMPQZrmi:
case X86::VPCMPQZrmik:
613 case X86::VPCMPQZrmib:
case X86::VPCMPQZrmibk:
614 case X86::VPCMPQZrri:
case X86::VPCMPQZrrik:
615 case X86::VPCMPWZ128rmi:
case X86::VPCMPWZ128rmik:
616 case X86::VPCMPWZ128rri:
case X86::VPCMPWZ128rrik:
617 case X86::VPCMPWZ256rmi:
case X86::VPCMPWZ256rmik:
618 case X86::VPCMPWZ256rri:
case X86::VPCMPWZ256rrik:
619 case X86::VPCMPWZrmi:
case X86::VPCMPWZrmik:
620 case X86::VPCMPWZrri:
case X86::VPCMPWZrrik: {
626 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPEQBZ128rm;
break;
627 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPEQBZ128rmk;
break;
628 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPEQBZ128rr;
break;
629 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPEQBZ128rrk;
break;
630 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPEQBZ256rm;
break;
631 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPEQBZ256rmk;
break;
632 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPEQBZ256rr;
break;
633 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPEQBZ256rrk;
break;
634 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPEQBZrm;
break;
635 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPEQBZrmk;
break;
636 case X86::VPCMPBZrri: NewOpc = X86::VPCMPEQBZrr;
break;
637 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPEQBZrrk;
break;
638 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPEQDZ128rm;
break;
639 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPEQDZ128rmb;
break;
640 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPEQDZ128rmbk;
break;
641 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPEQDZ128rmk;
break;
642 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPEQDZ128rr;
break;
643 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPEQDZ128rrk;
break;
644 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPEQDZ256rm;
break;
645 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPEQDZ256rmb;
break;
646 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPEQDZ256rmbk;
break;
647 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPEQDZ256rmk;
break;
648 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPEQDZ256rr;
break;
649 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPEQDZ256rrk;
break;
650 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPEQDZrm;
break;
651 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPEQDZrmb;
break;
652 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPEQDZrmbk;
break;
653 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPEQDZrmk;
break;
654 case X86::VPCMPDZrri: NewOpc = X86::VPCMPEQDZrr;
break;
655 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPEQDZrrk;
break;
656 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPEQQZ128rm;
break;
657 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPEQQZ128rmb;
break;
658 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPEQQZ128rmbk;
break;
659 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPEQQZ128rmk;
break;
660 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPEQQZ128rr;
break;
661 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPEQQZ128rrk;
break;
662 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPEQQZ256rm;
break;
663 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPEQQZ256rmb;
break;
664 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPEQQZ256rmbk;
break;
665 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPEQQZ256rmk;
break;
666 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPEQQZ256rr;
break;
667 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPEQQZ256rrk;
break;
668 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPEQQZrm;
break;
669 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPEQQZrmb;
break;
670 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPEQQZrmbk;
break;
671 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPEQQZrmk;
break;
672 case X86::VPCMPQZrri: NewOpc = X86::VPCMPEQQZrr;
break;
673 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPEQQZrrk;
break;
674 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPEQWZ128rm;
break;
675 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPEQWZ128rmk;
break;
676 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPEQWZ128rr;
break;
677 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPEQWZ128rrk;
break;
678 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPEQWZ256rm;
break;
679 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPEQWZ256rmk;
break;
680 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPEQWZ256rr;
break;
681 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPEQWZ256rrk;
break;
682 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPEQWZrm;
break;
683 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPEQWZrmk;
break;
684 case X86::VPCMPWZrri: NewOpc = X86::VPCMPEQWZrr;
break;
685 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPEQWZrrk;
break;
698 case X86::VPCMPBZ128rmi: NewOpc = X86::VPCMPGTBZ128rm;
break;
699 case X86::VPCMPBZ128rmik: NewOpc = X86::VPCMPGTBZ128rmk;
break;
700 case X86::VPCMPBZ128rri: NewOpc = X86::VPCMPGTBZ128rr;
break;
701 case X86::VPCMPBZ128rrik: NewOpc = X86::VPCMPGTBZ128rrk;
break;
702 case X86::VPCMPBZ256rmi: NewOpc = X86::VPCMPGTBZ256rm;
break;
703 case X86::VPCMPBZ256rmik: NewOpc = X86::VPCMPGTBZ256rmk;
break;
704 case X86::VPCMPBZ256rri: NewOpc = X86::VPCMPGTBZ256rr;
break;
705 case X86::VPCMPBZ256rrik: NewOpc = X86::VPCMPGTBZ256rrk;
break;
706 case X86::VPCMPBZrmi: NewOpc = X86::VPCMPGTBZrm;
break;
707 case X86::VPCMPBZrmik: NewOpc = X86::VPCMPGTBZrmk;
break;
708 case X86::VPCMPBZrri: NewOpc = X86::VPCMPGTBZrr;
break;
709 case X86::VPCMPBZrrik: NewOpc = X86::VPCMPGTBZrrk;
break;
710 case X86::VPCMPDZ128rmi: NewOpc = X86::VPCMPGTDZ128rm;
break;
711 case X86::VPCMPDZ128rmib: NewOpc = X86::VPCMPGTDZ128rmb;
break;
712 case X86::VPCMPDZ128rmibk: NewOpc = X86::VPCMPGTDZ128rmbk;
break;
713 case X86::VPCMPDZ128rmik: NewOpc = X86::VPCMPGTDZ128rmk;
break;
714 case X86::VPCMPDZ128rri: NewOpc = X86::VPCMPGTDZ128rr;
break;
715 case X86::VPCMPDZ128rrik: NewOpc = X86::VPCMPGTDZ128rrk;
break;
716 case X86::VPCMPDZ256rmi: NewOpc = X86::VPCMPGTDZ256rm;
break;
717 case X86::VPCMPDZ256rmib: NewOpc = X86::VPCMPGTDZ256rmb;
break;
718 case X86::VPCMPDZ256rmibk: NewOpc = X86::VPCMPGTDZ256rmbk;
break;
719 case X86::VPCMPDZ256rmik: NewOpc = X86::VPCMPGTDZ256rmk;
break;
720 case X86::VPCMPDZ256rri: NewOpc = X86::VPCMPGTDZ256rr;
break;
721 case X86::VPCMPDZ256rrik: NewOpc = X86::VPCMPGTDZ256rrk;
break;
722 case X86::VPCMPDZrmi: NewOpc = X86::VPCMPGTDZrm;
break;
723 case X86::VPCMPDZrmib: NewOpc = X86::VPCMPGTDZrmb;
break;
724 case X86::VPCMPDZrmibk: NewOpc = X86::VPCMPGTDZrmbk;
break;
725 case X86::VPCMPDZrmik: NewOpc = X86::VPCMPGTDZrmk;
break;
726 case X86::VPCMPDZrri: NewOpc = X86::VPCMPGTDZrr;
break;
727 case X86::VPCMPDZrrik: NewOpc = X86::VPCMPGTDZrrk;
break;
728 case X86::VPCMPQZ128rmi: NewOpc = X86::VPCMPGTQZ128rm;
break;
729 case X86::VPCMPQZ128rmib: NewOpc = X86::VPCMPGTQZ128rmb;
break;
730 case X86::VPCMPQZ128rmibk: NewOpc = X86::VPCMPGTQZ128rmbk;
break;
731 case X86::VPCMPQZ128rmik: NewOpc = X86::VPCMPGTQZ128rmk;
break;
732 case X86::VPCMPQZ128rri: NewOpc = X86::VPCMPGTQZ128rr;
break;
733 case X86::VPCMPQZ128rrik: NewOpc = X86::VPCMPGTQZ128rrk;
break;
734 case X86::VPCMPQZ256rmi: NewOpc = X86::VPCMPGTQZ256rm;
break;
735 case X86::VPCMPQZ256rmib: NewOpc = X86::VPCMPGTQZ256rmb;
break;
736 case X86::VPCMPQZ256rmibk: NewOpc = X86::VPCMPGTQZ256rmbk;
break;
737 case X86::VPCMPQZ256rmik: NewOpc = X86::VPCMPGTQZ256rmk;
break;
738 case X86::VPCMPQZ256rri: NewOpc = X86::VPCMPGTQZ256rr;
break;
739 case X86::VPCMPQZ256rrik: NewOpc = X86::VPCMPGTQZ256rrk;
break;
740 case X86::VPCMPQZrmi: NewOpc = X86::VPCMPGTQZrm;
break;
741 case X86::VPCMPQZrmib: NewOpc = X86::VPCMPGTQZrmb;
break;
742 case X86::VPCMPQZrmibk: NewOpc = X86::VPCMPGTQZrmbk;
break;
743 case X86::VPCMPQZrmik: NewOpc = X86::VPCMPGTQZrmk;
break;
744 case X86::VPCMPQZrri: NewOpc = X86::VPCMPGTQZrr;
break;
745 case X86::VPCMPQZrrik: NewOpc = X86::VPCMPGTQZrrk;
break;
746 case X86::VPCMPWZ128rmi: NewOpc = X86::VPCMPGTWZ128rm;
break;
747 case X86::VPCMPWZ128rmik: NewOpc = X86::VPCMPGTWZ128rmk;
break;
748 case X86::VPCMPWZ128rri: NewOpc = X86::VPCMPGTWZ128rr;
break;
749 case X86::VPCMPWZ128rrik: NewOpc = X86::VPCMPGTWZ128rrk;
break;
750 case X86::VPCMPWZ256rmi: NewOpc = X86::VPCMPGTWZ256rm;
break;
751 case X86::VPCMPWZ256rmik: NewOpc = X86::VPCMPGTWZ256rmk;
break;
752 case X86::VPCMPWZ256rri: NewOpc = X86::VPCMPGTWZ256rr;
break;
753 case X86::VPCMPWZ256rrik: NewOpc = X86::VPCMPGTWZ256rrk;
break;
754 case X86::VPCMPWZrmi: NewOpc = X86::VPCMPGTWZrm;
break;
755 case X86::VPCMPWZrmik: NewOpc = X86::VPCMPGTWZrmk;
break;
756 case X86::VPCMPWZrri: NewOpc = X86::VPCMPGTWZrr;
break;
757 case X86::VPCMPWZrrik: NewOpc = X86::VPCMPGTWZrrk;
break;
773 case X86::CALL64pcrel32:
778 case X86::EH_RETURN64: {
784 case X86::CLEANUPRET: {
791 case X86::CATCHRET: {
794 unsigned ReturnReg = Subtarget.is64Bit() ? X86::RAX : X86::EAX;
804 case X86::TAILJMPr64:
805 case X86::TAILJMPr64_REX:
807 case X86::TAILJMPd64:
812 case X86::TAILJMPd_CC:
813 case X86::TAILJMPd64_CC:
819 case X86::TAILJMPm64:
820 case X86::TAILJMPm64_REX:
822 "Unexpected number of operands!");
835 case X86::DEC16r: Opcode = X86::DEC16r_alt;
break;
836 case X86::DEC32r: Opcode = X86::DEC32r_alt;
break;
837 case X86::INC16r: Opcode = X86::INC16r_alt;
break;
838 case X86::INC32r: Opcode = X86::INC32r_alt;
break;
851 case X86::MOV8mr_NOREX:
853 case X86::MOV8rm_NOREX:
862 case X86::MOV8mr_NOREX:
863 case X86::MOV8mr: NewOpc = X86::MOV8o32a;
break;
864 case X86::MOV8rm_NOREX:
865 case X86::MOV8rm: NewOpc = X86::MOV8ao32;
break;
866 case X86::MOV16mr: NewOpc = X86::MOV16o32a;
break;
867 case X86::MOV16rm: NewOpc = X86::MOV16ao32;
break;
868 case X86::MOV32mr: NewOpc = X86::MOV32o32a;
break;
869 case X86::MOV32rm: NewOpc = X86::MOV32ao32;
break;
875 case X86::ADC8ri:
case X86::ADC16ri:
case X86::ADC32ri:
case X86::ADC64ri32:
876 case X86::ADD8ri:
case X86::ADD16ri:
case X86::ADD32ri:
case X86::ADD64ri32:
877 case X86::AND8ri:
case X86::AND16ri:
case X86::AND32ri:
case X86::AND64ri32:
878 case X86::CMP8ri:
case X86::CMP16ri:
case X86::CMP32ri:
case X86::CMP64ri32:
879 case X86::OR8ri:
case X86::OR16ri:
case X86::OR32ri:
case X86::OR64ri32:
880 case X86::SBB8ri:
case X86::SBB16ri:
case X86::SBB32ri:
case X86::SBB64ri32:
881 case X86::SUB8ri:
case X86::SUB16ri:
case X86::SUB32ri:
case X86::SUB64ri32:
882 case X86::TEST8ri:
case X86::TEST16ri:
case X86::TEST32ri:
case X86::TEST64ri32:
883 case X86::XOR8ri:
case X86::XOR16ri:
case X86::XOR32ri:
case X86::XOR64ri32: {
887 case X86::ADC8ri: NewOpc = X86::ADC8i8;
break;
888 case X86::ADC16ri: NewOpc = X86::ADC16i16;
break;
889 case X86::ADC32ri: NewOpc = X86::ADC32i32;
break;
890 case X86::ADC64ri32: NewOpc = X86::ADC64i32;
break;
891 case X86::ADD8ri: NewOpc = X86::ADD8i8;
break;
892 case X86::ADD16ri: NewOpc = X86::ADD16i16;
break;
893 case X86::ADD32ri: NewOpc = X86::ADD32i32;
break;
894 case X86::ADD64ri32: NewOpc = X86::ADD64i32;
break;
895 case X86::AND8ri: NewOpc = X86::AND8i8;
break;
896 case X86::AND16ri: NewOpc = X86::AND16i16;
break;
897 case X86::AND32ri: NewOpc = X86::AND32i32;
break;
898 case X86::AND64ri32: NewOpc = X86::AND64i32;
break;
899 case X86::CMP8ri: NewOpc = X86::CMP8i8;
break;
900 case X86::CMP16ri: NewOpc = X86::CMP16i16;
break;
901 case X86::CMP32ri: NewOpc = X86::CMP32i32;
break;
902 case X86::CMP64ri32: NewOpc = X86::CMP64i32;
break;
903 case X86::OR8ri: NewOpc = X86::OR8i8;
break;
904 case X86::OR16ri: NewOpc = X86::OR16i16;
break;
905 case X86::OR32ri: NewOpc = X86::OR32i32;
break;
906 case X86::OR64ri32: NewOpc = X86::OR64i32;
break;
907 case X86::SBB8ri: NewOpc = X86::SBB8i8;
break;
908 case X86::SBB16ri: NewOpc = X86::SBB16i16;
break;
909 case X86::SBB32ri: NewOpc = X86::SBB32i32;
break;
910 case X86::SBB64ri32: NewOpc = X86::SBB64i32;
break;
911 case X86::SUB8ri: NewOpc = X86::SUB8i8;
break;
912 case X86::SUB16ri: NewOpc = X86::SUB16i16;
break;
913 case X86::SUB32ri: NewOpc = X86::SUB32i32;
break;
914 case X86::SUB64ri32: NewOpc = X86::SUB64i32;
break;
915 case X86::TEST8ri: NewOpc = X86::TEST8i8;
break;
916 case X86::TEST16ri: NewOpc = X86::TEST16i16;
break;
917 case X86::TEST32ri: NewOpc = X86::TEST32i32;
break;
918 case X86::TEST64ri32: NewOpc = X86::TEST64i32;
break;
919 case X86::XOR8ri: NewOpc = X86::XOR8i8;
break;
920 case X86::XOR16ri: NewOpc = X86::XOR16i16;
break;
921 case X86::XOR32ri: NewOpc = X86::XOR32i32;
break;
922 case X86::XOR64ri32: NewOpc = X86::XOR64i32;
break;
929 case X86::MOVSX16rr8:
930 case X86::MOVSX32rr16:
931 case X86::MOVSX64rr32:
936 case X86::VCMPPDYrri:
938 case X86::VCMPPSYrri:
940 case X86::VCMPSSrr: {
945 unsigned Imm =
MI->getOperand(3).getImm() & 0x7;
959 case X86::VMOVHLPSrr:
960 case X86::VUNPCKHPDrr:
964 case X86::MASKMOVDQU:
965 case X86::VMASKMOVDQU:
974 if (
MI->getDesc().isCommutable() &&
986 if (X86::isBSF(OutMI.
getOpcode()) && !MF.getFunction().hasOptSize()) {
990 if (FlagDef && FlagDef->
isDead())
998void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
1001 bool Is64Bits =
MI.getOpcode() != X86::TLS_addr32 &&
1002 MI.getOpcode() != X86::TLS_base_addr32;
1003 bool Is64BitsLP64 =
MI.getOpcode() == X86::TLS_addr64 ||
1004 MI.getOpcode() == X86::TLS_base_addr64;
1008 switch (
MI.getOpcode()) {
1009 case X86::TLS_addr32:
1010 case X86::TLS_addr64:
1011 case X86::TLS_addrX32:
1014 case X86::TLS_base_addr32:
1017 case X86::TLS_base_addr64:
1018 case X86::TLS_base_addrX32:
1026 MCInstLowering.GetSymbolFromOperand(
MI.getOperand(3)), SRVK, Ctx);
1038 if (NeedsPadding && Is64BitsLP64)
1064 EmitAndCountInstruction(
1099 EmitAndCountInstruction(
1114 unsigned MaxNopLength = 1;
1115 if (Subtarget->is64Bit()) {
1118 if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
1120 else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
1122 else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
1126 }
if (Subtarget->is32Bit())
1130 NumBytes = std::min(NumBytes, MaxNopLength);
1133 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
1134 IndexReg = Displacement = SegmentReg = 0;
1147 Opc = X86::XCHG16ar;
1162 IndexReg = X86::RAX;
1168 IndexReg = X86::RAX;
1179 IndexReg = X86::RAX;
1185 IndexReg = X86::RAX;
1191 IndexReg = X86::RAX;
1192 SegmentReg = X86::CS;
1196 unsigned NumPrefixes = std::min(NumBytes - NopSize, 5U);
1197 NopSize += NumPrefixes;
1198 for (
unsigned i = 0; i != NumPrefixes; ++i)
1199 OS.emitBytes(
"\x66");
1207 OS.emitInstruction(
MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX),
1216 .addImm(Displacement)
1217 .addReg(SegmentReg),
1221 assert(NopSize <= NumBytes &&
"We overemitted?");
1228 unsigned NopsToEmit = NumBytes;
1231 NumBytes -=
emitNop(
OS, NumBytes, Subtarget);
1232 assert(NopsToEmit >= NumBytes &&
"Emitted more than I asked for!");
1237 X86MCInstLower &MCIL) {
1238 assert(Subtarget->is64Bit() &&
"Statepoint currently only supports X86-64");
1243 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
1249 unsigned CallOpcode;
1250 switch (CallTarget.
getType()) {
1253 CallTargetMCOp = MCIL.LowerSymbolOperand(
1254 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
1255 CallOpcode = X86::CALL64pcrel32;
1263 CallOpcode = X86::CALL64pcrel32;
1273 "yet implemented.");
1275 CallOpcode = X86::CALL64r;
1285 CallInst.addOperand(CallTargetMCOp);
1297void X86AsmPrinter::LowerFAULTING_OP(
const MachineInstr &FaultingMI,
1298 X86MCInstLower &MCIL) {
1309 unsigned OperandsBeginIdx = 4;
1319 MI.setOpcode(Opcode);
1321 if (DefRegister != X86::NoRegister)
1326 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&FaultingMI, MO))
1327 MI.addOperand(*MaybeOperand);
1334 X86MCInstLower &MCIL) {
1335 bool Is64Bits = Subtarget->is64Bit();
1341 EmitAndCountInstruction(
1342 MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
1347 assert(std::next(
MI.getIterator())->isCall() &&
1348 "KCFI_CHECK not followed by a call instruction");
1355 int64_t PrefixNops = 0;
1366 const Register AddrReg =
MI.getOperand(0).getReg();
1370 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
1371 EmitAndCountInstruction(
1374 .addReg(X86::NoRegister)
1378 .addReg(X86::NoRegister)
1379 .addImm(-(PrefixNops + 4))
1380 .addReg(X86::NoRegister));
1383 EmitAndCountInstruction(
1395void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
1402 const auto &
Reg =
MI.getOperand(0).getReg();
1407 bool OrShadowOffset;
1409 AccessInfo.CompileKernel, &ShadowBase,
1410 &MappingScale, &OrShadowOffset);
1414 std::string SymName = (
"__asan_check_" +
Name +
"_" +
Op +
"_" +
1415 Twine(1ULL << AccessInfo.AccessSizeIndex) +
"_" +
1420 "OrShadowOffset is not supported with optimized callbacks");
1422 EmitAndCountInstruction(
1429 X86MCInstLower &MCIL) {
1434 unsigned MinSize =
MI.getOperand(0).getImm();
1435 unsigned Opcode =
MI.getOperand(1).getImm();
1438 bool EmptyInst = (Opcode == TargetOpcode::PATCHABLE_OP);
1443 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1453 if (
Code.size() < MinSize) {
1454 if (MinSize == 2 && Subtarget->is32Bit() &&
1456 (Subtarget->getCPU().empty() || Subtarget->getCPU() ==
"pentium3")) {
1462 MCInstBuilder(X86::MOV32rr_REV).addReg(X86::EDI).addReg(X86::EDI),
1464 }
else if (MinSize == 2 && Opcode == X86::PUSH64r) {
1473 assert(NopSize == MinSize &&
"Could not implement MinSize!");
1491 unsigned NumShadowBytes =
MI.getOperand(1).getImm();
1492 SMShadowTracker.reset(NumShadowBytes);
1498 X86MCInstLower &MCIL) {
1499 assert(Subtarget->is64Bit() &&
"Patchpoint currently only supports X86-64");
1511 unsigned ScratchIdx = opers.getNextScratchIdx();
1512 unsigned EncodedBytes = 0;
1529 CalleeMCOp = MCIL.LowerSymbolOperand(CalleeMO,
1530 MCIL.GetSymbolFromOperand(CalleeMO));
1536 Register ScratchReg =
MI.getOperand(ScratchIdx).getReg();
1542 EmitAndCountInstruction(
1547 "Lowering patchpoint with thunks not yet implemented.");
1548 EmitAndCountInstruction(
MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
1552 unsigned NumBytes = opers.getNumPatchBytes();
1553 assert(NumBytes >= EncodedBytes &&
1554 "Patchpoint can't request size less than the length of a call.");
1559void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(
const MachineInstr &
MI,
1560 X86MCInstLower &MCIL) {
1561 assert(Subtarget->is64Bit() &&
"XRay custom events only supports X86-64");
1586 OutStreamer->AddComment(
"# XRay Custom Event Log");
1597 const Register DestRegs[] = {X86::RDI, X86::RSI};
1598 bool UsedMask[] = {
false,
false};
1607 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1608 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1609 assert(
Op->isReg() &&
"Only support arguments in registers");
1612 if (SrcRegs[
I] != DestRegs[
I]) {
1614 EmitAndCountInstruction(
1625 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1626 if (SrcRegs[
I] != DestRegs[
I])
1627 EmitAndCountInstruction(
1639 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1642 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1644 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1648 OutStreamer->AddComment(
"xray custom event end.");
1656void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(
const MachineInstr &
MI,
1657 X86MCInstLower &MCIL) {
1658 assert(Subtarget->is64Bit() &&
"XRay typed events only supports X86-64");
1683 OutStreamer->AddComment(
"# XRay Typed Event Log");
1695 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1696 bool UsedMask[] = {
false,
false,
false};
1705 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1706 if (
auto Op = MCIL.LowerMachineOperand(&
MI,
MI.getOperand(
I))) {
1708 assert(
Op->isReg() &&
"Only supports arguments in registers");
1711 if (SrcRegs[
I] != DestRegs[
I]) {
1713 EmitAndCountInstruction(
1729 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I)
1731 EmitAndCountInstruction(
1743 .
addOperand(MCIL.LowerSymbolOperand(TOp, TSym)));
1746 for (
unsigned I =
sizeof UsedMask;
I-- > 0;)
1748 EmitAndCountInstruction(
MCInstBuilder(X86::POP64r).addReg(DestRegs[
I]));
1758void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(
const MachineInstr &
MI,
1759 X86MCInstLower &MCIL) {
1764 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1766 if (
F.getFnAttribute(
"patchable-function-entry")
1768 .getAsInteger(10, Num))
1799 X86MCInstLower &MCIL) {
1819 unsigned OpCode =
MI.getOperand(0).getImm();
1821 Ret.setOpcode(OpCode);
1823 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1824 Ret.addOperand(*MaybeOperand);
1830void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(
const MachineInstr &
MI,
1831 X86MCInstLower &MCIL) {
1853 unsigned OpCode =
MI.getOperand(0).getImm();
1862 if (
auto MaybeOperand = MCIL.LowerMachineOperand(&
MI, MO))
1884 if (!Op.isCPI() || Op.getOffset() != 0)
1888 MI.getParent()->getParent()->getConstantPool()->getConstants();
1901 std::string Comment;
1918 SrcOp1.
isReg() ? GetRegisterName(SrcOp1.
getReg()) :
"mem";
1920 SrcOp2.
isReg() ? GetRegisterName(SrcOp2.
getReg()) :
"mem";
1924 if (Src1Name == Src2Name)
1925 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i)
1926 if (ShuffleMask[i] >= e)
1927 ShuffleMask[i] -= e;
1935 if (SrcOp1Idx > 1) {
1936 assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) &&
"Unexpected writemask");
1939 if (WriteMaskOp.
isReg()) {
1940 CS <<
" {%" << GetRegisterName(WriteMaskOp.
getReg()) <<
"}";
1942 if (SrcOp1Idx == 2) {
1950 for (
int i = 0, e = ShuffleMask.
size(); i != e; ++i) {
1960 bool isSrc1 = ShuffleMask[i] < (int)e;
1961 CS << (isSrc1 ? Src1Name : Src2Name) <<
'[';
1963 bool IsFirst =
true;
1965 (ShuffleMask[i] < (
int)e) == isSrc1) {
1973 CS << ShuffleMask[i] % (int)e;
2002 Flt.toString(Str, 0, 0);
2007 if (isa<UndefValue>(COp)) {
2009 }
else if (
auto *CI = dyn_cast<ConstantInt>(COp)) {
2011 }
else if (
auto *CF = dyn_cast<ConstantFP>(COp)) {
2026 switch (
MI->getOpcode()) {
2027 case X86::SEH_PushReg:
2030 case X86::SEH_StackAlloc:
2033 case X86::SEH_StackAlign:
2036 case X86::SEH_SetFrame:
2037 assert(
MI->getOperand(1).getImm() == 0 &&
2038 ".cv_fpo_setframe takes no offset");
2041 case X86::SEH_EndPrologue:
2044 case X86::SEH_SaveReg:
2045 case X86::SEH_SaveXMM:
2046 case X86::SEH_PushFrame:
2056 switch (
MI->getOpcode()) {
2057 case X86::SEH_PushReg:
2061 case X86::SEH_SaveReg:
2063 MI->getOperand(1).getImm());
2066 case X86::SEH_SaveXMM:
2068 MI->getOperand(1).getImm());
2071 case X86::SEH_StackAlloc:
2072 OutStreamer->emitWinCFIAllocStack(
MI->getOperand(0).getImm());
2075 case X86::SEH_SetFrame:
2077 MI->getOperand(1).getImm());
2080 case X86::SEH_PushFrame:
2081 OutStreamer->emitWinCFIPushFrame(
MI->getOperand(0).getImm());
2084 case X86::SEH_EndPrologue:
2094 if (
Info.RegClass == X86::VR128RegClassID ||
2095 Info.RegClass == X86::VR128XRegClassID)
2097 if (
Info.RegClass == X86::VR256RegClassID ||
2098 Info.RegClass == X86::VR256XRegClassID)
2100 if (
Info.RegClass == X86::VR512RegClassID)
2107 switch (
MI->getOpcode()) {
2112 case X86::VPSHUFBrm:
2113 case X86::VPSHUFBYrm:
2114 case X86::VPSHUFBZ128rm:
2115 case X86::VPSHUFBZ128rmk:
2116 case X86::VPSHUFBZ128rmkz:
2117 case X86::VPSHUFBZ256rm:
2118 case X86::VPSHUFBZ256rmk:
2119 case X86::VPSHUFBZ256rmkz:
2120 case X86::VPSHUFBZrm:
2121 case X86::VPSHUFBZrmk:
2122 case X86::VPSHUFBZrmkz: {
2123 unsigned SrcIdx = 1;
2135 "Unexpected number of operands!");
2148 case X86::VPERMILPSrm:
2149 case X86::VPERMILPSYrm:
2150 case X86::VPERMILPSZ128rm:
2151 case X86::VPERMILPSZ128rmk:
2152 case X86::VPERMILPSZ128rmkz:
2153 case X86::VPERMILPSZ256rm:
2154 case X86::VPERMILPSZ256rmk:
2155 case X86::VPERMILPSZ256rmkz:
2156 case X86::VPERMILPSZrm:
2157 case X86::VPERMILPSZrmk:
2158 case X86::VPERMILPSZrmkz:
2159 case X86::VPERMILPDrm:
2160 case X86::VPERMILPDYrm:
2161 case X86::VPERMILPDZ128rm:
2162 case X86::VPERMILPDZ128rmk:
2163 case X86::VPERMILPDZ128rmkz:
2164 case X86::VPERMILPDZ256rm:
2165 case X86::VPERMILPDZ256rmk:
2166 case X86::VPERMILPDZ256rmkz:
2167 case X86::VPERMILPDZrm:
2168 case X86::VPERMILPDZrmk:
2169 case X86::VPERMILPDZrmkz: {
2171 switch (
MI->getOpcode()) {
2173 case X86::VPERMILPSrm:
2174 case X86::VPERMILPSYrm:
2175 case X86::VPERMILPSZ128rm:
2176 case X86::VPERMILPSZ256rm:
2177 case X86::VPERMILPSZrm:
2178 case X86::VPERMILPSZ128rmkz:
2179 case X86::VPERMILPSZ256rmkz:
2180 case X86::VPERMILPSZrmkz:
2181 case X86::VPERMILPSZ128rmk:
2182 case X86::VPERMILPSZ256rmk:
2183 case X86::VPERMILPSZrmk:
2186 case X86::VPERMILPDrm:
2187 case X86::VPERMILPDYrm:
2188 case X86::VPERMILPDZ128rm:
2189 case X86::VPERMILPDZ256rm:
2190 case X86::VPERMILPDZrm:
2191 case X86::VPERMILPDZ128rmkz:
2192 case X86::VPERMILPDZ256rmkz:
2193 case X86::VPERMILPDZrmkz:
2194 case X86::VPERMILPDZ128rmk:
2195 case X86::VPERMILPDZ256rmk:
2196 case X86::VPERMILPDZrmk:
2201 unsigned SrcIdx = 1;
2213 "Unexpected number of operands!");
2226 case X86::VPERMIL2PDrm:
2227 case X86::VPERMIL2PSrm:
2228 case X86::VPERMIL2PDYrm:
2229 case X86::VPERMIL2PSYrm: {
2231 "Unexpected number of operands!");
2234 if (!CtrlOp.
isImm())
2238 switch (
MI->getOpcode()) {
2240 case X86::VPERMIL2PSrm:
case X86::VPERMIL2PSYrm: ElSize = 32;
break;
2241 case X86::VPERMIL2PDrm:
case X86::VPERMIL2PDYrm: ElSize = 64;
break;
2255 case X86::VPPERMrrm: {
2257 "Unexpected number of operands!");
2270 case X86::MMX_MOVQ64rm: {
2272 "Unexpected number of operands!");
2274 std::string Comment;
2278 if (
auto *CF = dyn_cast<ConstantFP>(
C)) {
2279 CS <<
"0x" <<
toString(CF->getValueAPF().bitcastToAPInt(), 16,
false);
2286#define MOV_CASE(Prefix, Suffix) \
2287 case X86::Prefix##MOVAPD##Suffix##rm: \
2288 case X86::Prefix##MOVAPS##Suffix##rm: \
2289 case X86::Prefix##MOVUPD##Suffix##rm: \
2290 case X86::Prefix##MOVUPS##Suffix##rm: \
2291 case X86::Prefix##MOVDQA##Suffix##rm: \
2292 case X86::Prefix##MOVDQU##Suffix##rm:
2294#define MOV_AVX512_CASE(Suffix) \
2295 case X86::VMOVDQA64##Suffix##rm: \
2296 case X86::VMOVDQA32##Suffix##rm: \
2297 case X86::VMOVDQU64##Suffix##rm: \
2298 case X86::VMOVDQU32##Suffix##rm: \
2299 case X86::VMOVDQU16##Suffix##rm: \
2300 case X86::VMOVDQU8##Suffix##rm: \
2301 case X86::VMOVAPS##Suffix##rm: \
2302 case X86::VMOVAPD##Suffix##rm: \
2303 case X86::VMOVUPS##Suffix##rm: \
2304 case X86::VMOVUPD##Suffix##rm:
2306#define CASE_ALL_MOV_RM() \
2310 MOV_AVX512_CASE(Z) \
2311 MOV_AVX512_CASE(Z256) \
2312 MOV_AVX512_CASE(Z128)
2317 case X86::VBROADCASTF128:
2318 case X86::VBROADCASTI128:
2319 case X86::VBROADCASTF32X4Z256rm:
2320 case X86::VBROADCASTF32X4rm:
2321 case X86::VBROADCASTF32X8rm:
2322 case X86::VBROADCASTF64X2Z128rm:
2323 case X86::VBROADCASTF64X2rm:
2324 case X86::VBROADCASTF64X4rm:
2325 case X86::VBROADCASTI32X4Z256rm:
2326 case X86::VBROADCASTI32X4rm:
2327 case X86::VBROADCASTI32X8rm:
2328 case X86::VBROADCASTI64X2Z128rm:
2329 case X86::VBROADCASTI64X2rm:
2330 case X86::VBROADCASTI64X4rm:
2332 "Unexpected number of operands!");
2336 switch (
MI->getOpcode()) {
2337 case X86::VBROADCASTF128: NumLanes = 2;
break;
2338 case X86::VBROADCASTI128: NumLanes = 2;
break;
2339 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2;
break;
2340 case X86::VBROADCASTF32X4rm: NumLanes = 4;
break;
2341 case X86::VBROADCASTF32X8rm: NumLanes = 2;
break;
2342 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2;
break;
2343 case X86::VBROADCASTF64X2rm: NumLanes = 4;
break;
2344 case X86::VBROADCASTF64X4rm: NumLanes = 2;
break;
2345 case X86::VBROADCASTI32X4Z256rm: NumLanes = 2;
break;
2346 case X86::VBROADCASTI32X4rm: NumLanes = 4;
break;
2347 case X86::VBROADCASTI32X8rm: NumLanes = 2;
break;
2348 case X86::VBROADCASTI64X2Z128rm: NumLanes = 2;
break;
2349 case X86::VBROADCASTI64X2rm: NumLanes = 4;
break;
2350 case X86::VBROADCASTI64X4rm: NumLanes = 2;
break;
2353 std::string Comment;
2357 if (
auto *CDS = dyn_cast<ConstantDataSequential>(
C)) {
2359 for (
int l = 0; l != NumLanes; ++l) {
2360 for (
int i = 0, NumElements = CDS->getNumElements(); i < NumElements;
2362 if (i != 0 || l != 0)
2364 if (CDS->getElementType()->isIntegerTy())
2366 else if (CDS->getElementType()->isHalfTy() ||
2367 CDS->getElementType()->isFloatTy() ||
2368 CDS->getElementType()->isDoubleTy())
2376 }
else if (
auto *CV = dyn_cast<ConstantVector>(
C)) {
2378 for (
int l = 0; l != NumLanes; ++l) {
2379 for (
int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands;
2381 if (i != 0 || l != 0)
2392 case X86::MOVDDUPrm:
2393 case X86::VMOVDDUPrm:
2394 case X86::VMOVDDUPZ128rm:
2395 case X86::VBROADCASTSSrm:
2396 case X86::VBROADCASTSSYrm:
2397 case X86::VBROADCASTSSZ128rm:
2398 case X86::VBROADCASTSSZ256rm:
2399 case X86::VBROADCASTSSZrm:
2400 case X86::VBROADCASTSDYrm:
2401 case X86::VBROADCASTSDZ256rm:
2402 case X86::VBROADCASTSDZrm:
2403 case X86::VPBROADCASTBrm:
2404 case X86::VPBROADCASTBYrm:
2405 case X86::VPBROADCASTBZ128rm:
2406 case X86::VPBROADCASTBZ256rm:
2407 case X86::VPBROADCASTBZrm:
2408 case X86::VPBROADCASTDrm:
2409 case X86::VPBROADCASTDYrm:
2410 case X86::VPBROADCASTDZ128rm:
2411 case X86::VPBROADCASTDZ256rm:
2412 case X86::VPBROADCASTDZrm:
2413 case X86::VPBROADCASTQrm:
2414 case X86::VPBROADCASTQYrm:
2415 case X86::VPBROADCASTQZ128rm:
2416 case X86::VPBROADCASTQZ256rm:
2417 case X86::VPBROADCASTQZrm:
2418 case X86::VPBROADCASTWrm:
2419 case X86::VPBROADCASTWYrm:
2420 case X86::VPBROADCASTWZ128rm:
2421 case X86::VPBROADCASTWZ256rm:
2422 case X86::VPBROADCASTWZrm:
2424 "Unexpected number of operands!");
2427 switch (
MI->getOpcode()) {
2429 case X86::MOVDDUPrm: NumElts = 2;
break;
2430 case X86::VMOVDDUPrm: NumElts = 2;
break;
2431 case X86::VMOVDDUPZ128rm: NumElts = 2;
break;
2432 case X86::VBROADCASTSSrm: NumElts = 4;
break;
2433 case X86::VBROADCASTSSYrm: NumElts = 8;
break;
2434 case X86::VBROADCASTSSZ128rm: NumElts = 4;
break;
2435 case X86::VBROADCASTSSZ256rm: NumElts = 8;
break;
2436 case X86::VBROADCASTSSZrm: NumElts = 16;
break;
2437 case X86::VBROADCASTSDYrm: NumElts = 4;
break;
2438 case X86::VBROADCASTSDZ256rm: NumElts = 4;
break;
2439 case X86::VBROADCASTSDZrm: NumElts = 8;
break;
2440 case X86::VPBROADCASTBrm: NumElts = 16;
break;
2441 case X86::VPBROADCASTBYrm: NumElts = 32;
break;
2442 case X86::VPBROADCASTBZ128rm: NumElts = 16;
break;
2443 case X86::VPBROADCASTBZ256rm: NumElts = 32;
break;
2444 case X86::VPBROADCASTBZrm: NumElts = 64;
break;
2445 case X86::VPBROADCASTDrm: NumElts = 4;
break;
2446 case X86::VPBROADCASTDYrm: NumElts = 8;
break;
2447 case X86::VPBROADCASTDZ128rm: NumElts = 4;
break;
2448 case X86::VPBROADCASTDZ256rm: NumElts = 8;
break;
2449 case X86::VPBROADCASTDZrm: NumElts = 16;
break;
2450 case X86::VPBROADCASTQrm: NumElts = 2;
break;
2451 case X86::VPBROADCASTQYrm: NumElts = 4;
break;
2452 case X86::VPBROADCASTQZ128rm: NumElts = 2;
break;
2453 case X86::VPBROADCASTQZ256rm: NumElts = 4;
break;
2454 case X86::VPBROADCASTQZrm: NumElts = 8;
break;
2455 case X86::VPBROADCASTWrm: NumElts = 8;
break;
2456 case X86::VPBROADCASTWYrm: NumElts = 16;
break;
2457 case X86::VPBROADCASTWZ128rm: NumElts = 8;
break;
2458 case X86::VPBROADCASTWZ256rm: NumElts = 16;
break;
2459 case X86::VPBROADCASTWZrm: NumElts = 32;
break;
2462 std::string Comment;
2467 for (
int i = 0; i != NumElts; ++i) {
2483 X86MCInstLower MCInstLowering(*
MF, *
this);
2487 if (
MI->getOpcode() == X86::OR64rm) {
2488 for (
auto &Opd :
MI->operands()) {
2489 if (Opd.isSymbol() &&
StringRef(Opd.getSymbolName()) ==
2490 "swift_async_extendedFramePointerFlags") {
2491 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags =
true;
2500 OutStreamer->AddComment(
"EVEX TO VEX Compression ",
false);
2507 switch (
MI->getOpcode()) {
2508 case TargetOpcode::DBG_VALUE:
2511 case X86::EH_RETURN:
2512 case X86::EH_RETURN64: {
2519 case X86::CLEANUPRET: {
2525 case X86::CATCHRET: {
2532 case X86::ENDBR64: {
2541 MCInstLowering.Lower(
MI, Inst);
2542 EmitAndCountInstruction(Inst);
2550 case X86::TAILJMPd64:
2551 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2557 case X86::TAILJMPd_CC:
2558 case X86::TAILJMPr64:
2559 case X86::TAILJMPm64:
2560 case X86::TAILJMPd64_CC:
2561 case X86::TAILJMPr64_REX:
2562 case X86::TAILJMPm64_REX:
2567 case X86::TLS_addr32:
2568 case X86::TLS_addr64:
2569 case X86::TLS_addrX32:
2570 case X86::TLS_base_addr32:
2571 case X86::TLS_base_addr64:
2572 case X86::TLS_base_addrX32:
2573 return LowerTlsAddr(MCInstLowering, *
MI);
2575 case X86::MOVPC32r: {
2586 EmitAndCountInstruction(
2592 bool hasFP = FrameLowering->
hasFP(*
MF);
2595 bool HasActiveDwarfFrame =
OutStreamer->getNumFrameInfos() &&
2600 if (HasActiveDwarfFrame && !hasFP) {
2601 OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth);
2608 EmitAndCountInstruction(
2611 if (HasActiveDwarfFrame && !hasFP) {
2617 case X86::ADD32ri: {
2633 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(
MI->getOperand(2));
2644 .addReg(
MI->getOperand(0).getReg())
2645 .
addReg(
MI->getOperand(1).getReg())
2649 case TargetOpcode::STATEPOINT:
2650 return LowerSTATEPOINT(*
MI, MCInstLowering);
2652 case TargetOpcode::FAULTING_OP:
2653 return LowerFAULTING_OP(*
MI, MCInstLowering);
2655 case TargetOpcode::FENTRY_CALL:
2656 return LowerFENTRY_CALL(*
MI, MCInstLowering);
2658 case TargetOpcode::PATCHABLE_OP:
2659 return LowerPATCHABLE_OP(*
MI, MCInstLowering);
2661 case TargetOpcode::STACKMAP:
2662 return LowerSTACKMAP(*
MI);
2664 case TargetOpcode::PATCHPOINT:
2665 return LowerPATCHPOINT(*
MI, MCInstLowering);
2667 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2668 return LowerPATCHABLE_FUNCTION_ENTER(*
MI, MCInstLowering);
2670 case TargetOpcode::PATCHABLE_RET:
2671 return LowerPATCHABLE_RET(*
MI, MCInstLowering);
2673 case TargetOpcode::PATCHABLE_TAIL_CALL:
2674 return LowerPATCHABLE_TAIL_CALL(*
MI, MCInstLowering);
2676 case TargetOpcode::PATCHABLE_EVENT_CALL:
2677 return LowerPATCHABLE_EVENT_CALL(*
MI, MCInstLowering);
2679 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2680 return LowerPATCHABLE_TYPED_EVENT_CALL(*
MI, MCInstLowering);
2682 case X86::MORESTACK_RET:
2686 case X86::KCFI_CHECK:
2687 return LowerKCFI_CHECK(*
MI);
2689 case X86::ASAN_CHECK_MEMACCESS:
2690 return LowerASAN_CHECK_MEMACCESS(*
MI);
2692 case X86::MORESTACK_RET_RESTORE_R10:
2695 EmitAndCountInstruction(
2696 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));
2699 case X86::SEH_PushReg:
2700 case X86::SEH_SaveReg:
2701 case X86::SEH_SaveXMM:
2702 case X86::SEH_StackAlloc:
2703 case X86::SEH_StackAlign:
2704 case X86::SEH_SetFrame:
2705 case X86::SEH_PushFrame:
2706 case X86::SEH_EndPrologue:
2707 EmitSEHInstruction(
MI);
2710 case X86::SEH_Epilogue: {
2720 if (
MBBI->isCall() || !
MBBI->isPseudo()) {
2728 case X86::UBSAN_UD1:
2733 .addReg(X86::NoRegister)
2734 .addImm(
MI->getOperand(0).getImm())
2735 .
addReg(X86::NoRegister));
2737 case X86::CALL64pcrel32:
2738 if (IndCSPrefix &&
MI->hasRegisterImplicitUseOperand(X86::R11))
2744 MCInstLowering.Lower(
MI, TmpInst);
2761 EmitAndCountInstruction(TmpInst);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Analysis containing CSE Info
Fixup Statepoint Caller Saved
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
Memory true print Memory SSA Printer
static MCSymbol * GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP)
const char LLVMTargetMachineRef TM
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
static MCOperand LowerSymbolOperand(const MachineInstr *MI, const MachineOperand &MO, AsmPrinter &AP)
static void emitX86Nops(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the optimal amount of multi-byte nops on X86.
static unsigned getRetOpcode(const X86Subtarget &Subtarget)
static void printConstant(const APInt &Val, raw_ostream &CS)
static unsigned convertTailJumpOpcode(unsigned Opcode)
static const Constant * getConstantFromPool(const MachineInstr &MI, const MachineOperand &Op)
static void addConstantComments(const MachineInstr *MI, MCStreamer &OutStreamer)
static unsigned getRegisterWidth(const MCOperandInfo &Info)
static MachineBasicBlock::const_iterator PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI)
static unsigned emitNop(MCStreamer &OS, unsigned NumBytes, const X86Subtarget *Subtarget)
Emit the largest nop instruction smaller than or equal to NumBytes bytes.
static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode)
Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with a short fixed-register form.
static void SimplifyMOVSX(MCInst &Inst)
If a movsx instruction has a shorter encoding for the used register simplify the instruction to use i...
#define CASE_ALL_MOV_RM()
static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx, unsigned SrcOp2Idx, ArrayRef< int > Mask)
static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode)
Simplify things like MOV32rm to MOV32o32a.
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
unsigned getNumWords() const
Get the number of words.
const uint64_t * getRawData() const
This function returns a pointer to the internal storage of the APInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class is intended to be used as a driving class for all asm writers.
MCSymbol * getSymbol(const GlobalValue *GV) const
MCSymbol * CurrentFnBegin
TargetMachine & TM
Target machine description.
virtual MCSymbol * GetCPISymbol(unsigned CPID) const
Return the symbol for the specified constant pool entry.
void emitKCFITrapEntry(const MachineFunction &MF, const MCSymbol *Symbol)
MachineFunction * MF
The current machine function.
MCSymbol * GetJTISymbol(unsigned JTID, bool isLinkerPrivate=false) const
Return the symbol for the specified jump table entry.
void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind, uint8_t Version=0)
MCSymbol * getSymbolPreferLocal(const GlobalValue &GV) const
Similar to getSymbol() but preferred for references.
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSymbol * createTempSymbol(const Twine &Name) const
bool isPositionIndependent() const
MCSymbol * CurrentPatchableFunctionEntrySym
The symbol for the entry in __patchable_function_entires.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
StringRef getValueAsString() const
Return the attribute's value as a string.
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
void recordFaultingOp(FaultKind FaultTy, const MCSymbol *FaultingLabel, const MCSymbol *HandlerLabel)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasInternalLinkage() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
bool canRelaxRelocations() const
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
const MCAsmInfo * getAsmInfo() const
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
iterator insert(iterator I, const MCOperand &Op)
void setFlags(unsigned F)
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
const MCOperand & getOperand(unsigned i) const
This holds information about one operand of a machine instruction, indicating the register class for ...
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual void AddComment(const Twine &T, bool EOL=true)
Add a textual comment.
virtual void emitRawComment(const Twine &T, bool TabPrefix=true)
Print T and prefix it with the comment string (normally #) and optionally a tab.
void setAllowAutoPadding(bool v)
bool getAllowAutoPadding() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
StringRef getName() const
getName - Get the symbol name.
MachineInstrBundleIterator< const MachineInstr > const_iterator
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
This class is a data container for one entry in a MachineConstantPool.
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
union llvm::MachineConstantPoolEntry::@193 Val
The constant itself.
const Constant * ConstVal
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineBasicBlock & front() const
Representation of each machine instruction.
iterator_range< mop_iterator > operands()
const MachineOperand & getOperand(unsigned i) const
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
PointerIntPair< MCSymbol *, 1, bool > StubValueTy
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
void setTargetFlags(unsigned F)
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
void getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV, bool CannotUsePrivateLabel) const
Print the appropriate prefix and the specified global variable's name.
bool getRtLibUseGOT() const
Returns true if PLT should be avoided for RTLib calls.
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
MI-level patchpoint operands.
PointerIntPair - This class implements a pair of a pointer and small integer.
PointerTy getPointer() const
Wrapper class representing virtual and physical registers.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
constexpr bool empty() const
empty - Check if the string is empty.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCRegisterInfo * getMCRegisterInfo() const
MCTargetOptions MCOptions
Machine level options.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
static const char * getRegisterName(MCRegister Reg)
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
const X86Subtarget & getSubtarget() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
unsigned getSlotSize() const
bool isTargetWindowsMSVC() const
bool useIndirectThunkCalls() const
X86 target streamer implementing x86-only assembly directives.
virtual bool emitFPOPushReg(unsigned Reg, SMLoc L={})
virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L={})
virtual bool emitFPOEndPrologue(SMLoc L={})
virtual bool emitFPOStackAlign(unsigned Align, SMLoc L={})
virtual bool emitFPOStackAlloc(unsigned StackAlloc, SMLoc L={})
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
A raw_ostream that writes to an SmallVector or SmallString.
This provides a very simple, boring adaptor for a begin and end iterator into a range type.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
bool isKMergeMasked(uint64_t TSFlags)
@ MRMSrcReg
MRMSrcReg - This form is used for instructions that use the Mod/RM byte to specify a source,...
bool isX86_64ExtendedReg(unsigned RegNo)
@ MO_TLSLD
MO_TLSLD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
@ MO_GOT_ABSOLUTE_ADDRESS
MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a relocation of: SYMBOL_LABEL + [.
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
@ MO_NTPOFF
MO_NTPOFF - On a symbol operand this indicates that the immediate is the negative thread-pointer offs...
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
@ MO_INDNTPOFF
MO_INDNTPOFF - On a symbol operand this indicates that the immediate is the absolute address of the G...
@ MO_GOTNTPOFF
MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry w...
@ MO_TPOFF
MO_TPOFF - On a symbol operand this indicates that the immediate is the thread-pointer offset for the...
@ MO_TLVP_PIC_BASE
MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate is some TLS offset from the ...
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
@ MO_ABS8
MO_ABS8 - On a symbol operand this indicates that the symbol is known to be an absolute symbol in ran...
@ MO_PLT
MO_PLT - On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol n...
@ MO_TLSGD
MO_TLSGD - On a symbol operand this indicates that the immediate is the offset of the GOT entry with ...
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
@ MO_GOTTPOFF
MO_GOTTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry wi...
@ MO_SECREL
MO_SECREL - On a symbol operand this indicates that the immediate is the offset from beginning of sec...
@ MO_DTPOFF
MO_DTPOFF - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
@ MO_TLSLDM
MO_TLSLDM - On a symbol operand this indicates that the immediate is the offset of the GOT entry with...
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
bool isKMasked(uint64_t TSFlags)
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
void DecodeVPERMILPMask(unsigned NumElts, unsigned ScalarBits, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMILPD/VPERMILPS variable mask from a raw array of constants.
MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High=false)
void DecodeVPERMIL2PMask(unsigned NumElts, unsigned ScalarBits, unsigned M2Z, ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPERMIL2PD/VPERMIL2PS variable mask from a raw array of constants.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void DecodeVPPERMMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a VPPERM mask from a raw array of constants such as from BUILD_VECTOR.
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize, bool IsKasan, uint64_t *ShadowBase, int *MappingScale, bool *OrShadowOffset)
void DecodePSHUFBMask(ArrayRef< uint64_t > RawMask, const APInt &UndefElts, SmallVectorImpl< int > &ShuffleMask)
Decode a PSHUFB mask from a raw array of constants such as from BUILD_VECTOR.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A RAII helper which defines a region of instructions which can't have padding added between them for ...
void changeAndComment(bool b)
NoAutoPaddingScope(MCStreamer &OS)
const bool OldAllowAutoPadding
This struct is a compact representation of a valid (non-zero power of two) alignment.