61 #define GET_ASSEMBLER_HEADER
62 #include "SparcGenAsmMatcher.inc"
67 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
70 bool MatchingInlineAsm)
override;
71 bool ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc)
override;
73 SMLoc &EndLoc)
override;
76 bool ParseDirective(
AsmToken DirectiveID)
override;
79 unsigned Kind)
override;
94 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
104 bool matchRegisterName(
const AsmToken &Tok,
unsigned &RegNo,
107 bool matchSparcAsmModifiers(
const MCExpr *&EVal,
SMLoc &EndLoc);
130 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
137 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
138 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
139 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
140 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
143 Sparc::I0,
Sparc::I1, Sparc::I2, Sparc::I3,
144 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
147 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
148 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
149 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
150 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
151 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
152 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
153 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
154 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
157 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
158 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
159 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
160 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
161 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
162 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
163 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
164 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
167 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
168 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
169 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
170 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
173 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
174 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
175 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
176 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
177 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
178 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
179 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
180 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
183 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
184 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
185 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
186 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
189 Sparc::C0,
Sparc::C1, Sparc::C2, Sparc::C3,
190 Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
191 Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
192 Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
193 Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
194 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
195 Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
196 Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
199 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
200 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
201 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
202 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
231 SMLoc StartLoc, EndLoc;
261 SparcOperand(KindTy K) :
Kind(K) {}
263 bool isToken()
const override {
return Kind == k_Token; }
264 bool isReg()
const override {
return Kind == k_Register; }
265 bool isImm()
const override {
return Kind == k_Immediate; }
266 bool isMem()
const override {
return isMEMrr() || isMEMri(); }
267 bool isMEMrr()
const {
return Kind == k_MemoryReg; }
268 bool isMEMri()
const {
return Kind == k_MemoryImm; }
269 bool isMembarTag()
const {
return Kind == k_Immediate; }
271 bool isCallTarget()
const {
276 return CE->getValue() % 4 == 0;
281 bool isShiftAmtImm5()
const {
286 return isUInt<5>(
CE->getValue());
291 bool isShiftAmtImm6()
const {
296 return isUInt<6>(
CE->getValue());
302 return (
Kind == k_Register &&
Reg.Kind == rk_IntReg);
305 bool isFloatReg()
const {
306 return (
Kind == k_Register &&
Reg.Kind == rk_FloatReg);
309 bool isFloatOrDoubleReg()
const {
310 return (
Kind == k_Register && (
Reg.Kind == rk_FloatReg
311 ||
Reg.Kind == rk_DoubleReg));
314 bool isCoprocReg()
const {
315 return (
Kind == k_Register &&
Reg.Kind == rk_CoprocReg);
323 unsigned getReg()
const override {
324 assert((
Kind == k_Register) &&
"Invalid access!");
328 const MCExpr *getImm()
const {
329 assert((
Kind == k_Immediate) &&
"Invalid access!");
333 unsigned getMemBase()
const {
334 assert((
Kind == k_MemoryReg ||
Kind == k_MemoryImm) &&
"Invalid access!");
338 unsigned getMemOffsetReg()
const {
339 assert((
Kind == k_MemoryReg) &&
"Invalid access!");
340 return Mem.OffsetReg;
343 const MCExpr *getMemOff()
const {
344 assert((
Kind == k_MemoryImm) &&
"Invalid access!");
349 SMLoc getStartLoc()
const override {
353 SMLoc getEndLoc()
const override {
359 case k_Token: OS <<
"Token: " << getToken() <<
"\n";
break;
360 case k_Register: OS <<
"Reg: #" <<
getReg() <<
"\n";
break;
361 case k_Immediate: OS <<
"Imm: " << getImm() <<
"\n";
break;
362 case k_MemoryReg: OS <<
"Mem: " << getMemBase() <<
"+"
363 << getMemOffsetReg() <<
"\n";
break;
364 case k_MemoryImm:
assert(getMemOff() !=
nullptr);
365 OS <<
"Mem: " << getMemBase()
366 <<
"+" << *getMemOff()
371 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
372 assert(
N == 1 &&
"Invalid number of operands!");
376 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
377 assert(
N == 1 &&
"Invalid number of operands!");
378 const MCExpr *Expr = getImm();
382 void addShiftAmtImm5Operands(
MCInst &Inst,
unsigned N)
const {
383 assert(
N == 1 &&
"Invalid number of operands!");
384 addExpr(Inst, getImm());
386 void addShiftAmtImm6Operands(
MCInst &Inst,
unsigned N)
const {
387 assert(
N == 1 &&
"Invalid number of operands!");
388 addExpr(Inst, getImm());
395 else if (
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
401 void addMEMrrOperands(
MCInst &Inst,
unsigned N)
const {
402 assert(
N == 2 &&
"Invalid number of operands!");
406 assert(getMemOffsetReg() != 0 &&
"Invalid offset");
410 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
411 assert(
N == 2 &&
"Invalid number of operands!");
415 const MCExpr *Expr = getMemOff();
419 void addMembarTagOperands(
MCInst &Inst,
unsigned N)
const {
420 assert(
N == 1 &&
"Invalid number of operands!");
421 const MCExpr *Expr = getImm();
426 assert(
N == 1 &&
"Invalid number of operands!");
427 addExpr(Inst, getImm());
430 static std::unique_ptr<SparcOperand> CreateToken(
StringRef Str,
SMLoc S) {
431 auto Op = std::make_unique<SparcOperand>(k_Token);
432 Op->Tok.Data = Str.data();
433 Op->Tok.Length = Str.size();
439 static std::unique_ptr<SparcOperand> CreateReg(
unsigned RegNum,
unsigned Kind,
441 auto Op = std::make_unique<SparcOperand>(k_Register);
442 Op->Reg.RegNum = RegNum;
443 Op->Reg.Kind = (SparcOperand::RegisterKind)
Kind;
449 static std::unique_ptr<SparcOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
451 auto Op = std::make_unique<SparcOperand>(k_Immediate);
458 static bool MorphToIntPairReg(SparcOperand &
Op) {
459 unsigned Reg =
Op.getReg();
461 unsigned regIdx = 32;
462 if (
Reg >= Sparc::G0 &&
Reg <= Sparc::G7)
463 regIdx =
Reg - Sparc::G0;
464 else if (
Reg >= Sparc::O0 &&
Reg <= Sparc::O7)
465 regIdx =
Reg - Sparc::O0 + 8;
467 regIdx =
Reg - Sparc::L0 + 16;
468 else if (
Reg >= Sparc::I0 &&
Reg <= Sparc::I7)
469 regIdx =
Reg - Sparc::I0 + 24;
470 if (regIdx % 2 || regIdx > 31)
473 Op.Reg.Kind = rk_IntPairReg;
477 static bool MorphToDoubleReg(SparcOperand &
Op) {
478 unsigned Reg =
Op.getReg();
480 unsigned regIdx =
Reg - Sparc::F0;
481 if (regIdx % 2 || regIdx > 31)
484 Op.Reg.Kind = rk_DoubleReg;
488 static bool MorphToQuadReg(SparcOperand &
Op) {
489 unsigned Reg =
Op.getReg();
491 switch (
Op.Reg.Kind) {
494 regIdx =
Reg - Sparc::F0;
495 if (regIdx % 4 || regIdx > 31)
500 regIdx =
Reg - Sparc::D0;
501 if (regIdx % 2 || regIdx > 31)
507 Op.Reg.Kind = rk_QuadReg;
511 static bool MorphToCoprocPairReg(SparcOperand &
Op) {
512 unsigned Reg =
Op.getReg();
513 assert(
Op.Reg.Kind == rk_CoprocReg);
514 unsigned regIdx = 32;
515 if (
Reg >= Sparc::C0 &&
Reg <= Sparc::C31)
516 regIdx =
Reg - Sparc::C0;
517 if (regIdx % 2 || regIdx > 31)
520 Op.Reg.Kind = rk_CoprocPairReg;
524 static std::unique_ptr<SparcOperand>
525 MorphToMEMrr(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
526 unsigned offsetReg =
Op->getReg();
527 Op->Kind = k_MemoryReg;
529 Op->Mem.OffsetReg = offsetReg;
530 Op->Mem.Off =
nullptr;
534 static std::unique_ptr<SparcOperand>
536 auto Op = std::make_unique<SparcOperand>(k_MemoryReg);
538 Op->Mem.OffsetReg = Sparc::G0;
539 Op->Mem.Off =
nullptr;
545 static std::unique_ptr<SparcOperand>
546 MorphToMEMri(
unsigned Base, std::unique_ptr<SparcOperand>
Op) {
548 Op->Kind = k_MemoryImm;
550 Op->Mem.OffsetReg = 0;
558 bool SparcAsmParser::expandSET(
MCInst &Inst,
SMLoc IDLoc,
567 int64_t RawImmValue = IsImm ? MCValOp.
getImm() : 0;
570 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
572 "set: argument must be between -2147483648 and 4294967295");
577 int32_t ImmValue = RawImmValue;
581 bool IsEffectivelyImm13 =
582 IsImm && ((
is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
594 if (!IsEffectivelyImm13) {
615 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
618 if (IsEffectivelyImm13)
632 bool SparcAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
636 bool MatchingInlineAsm) {
641 switch (MatchResult) {
642 case Match_Success: {
660 case Match_MissingFeature:
662 "instruction requires a CPU feature not currently enabled");
664 case Match_InvalidOperand: {
665 SMLoc ErrorLoc = IDLoc;
668 return Error(IDLoc,
"too few operands for instruction");
671 if (ErrorLoc ==
SMLoc())
675 return Error(ErrorLoc,
"invalid operand for instruction");
677 case Match_MnemonicFail:
678 return Error(IDLoc,
"invalid instruction mnemonic");
683 bool SparcAsmParser::ParseRegister(
unsigned &RegNo,
SMLoc &StartLoc,
686 return Error(StartLoc,
"invalid register name");
700 unsigned regKind = SparcOperand::rk_None;
701 if (matchRegisterName(Tok, RegNo, regKind)) {
706 getLexer().UnLex(Tok);
719 Operands.push_back(SparcOperand::CreateToken(
Name, NameLoc));
728 SMLoc Loc = getLexer().getLoc();
729 return Error(Loc,
"unexpected token");
733 SMLoc Loc = getLexer().getLoc();
734 return Error(Loc,
"unexpected token");
745 SMLoc Loc = getLexer().getLoc();
746 return Error(Loc,
"unexpected token");
751 SMLoc Loc = getLexer().getLoc();
752 return Error(Loc,
"unexpected token");
758 bool SparcAsmParser::
759 ParseDirective(
AsmToken DirectiveID)
763 if (IDVal ==
".register") {
768 if (IDVal ==
".proc") {
783 std::unique_ptr<SparcOperand>
LHS;
793 if (!
LHS->isIntReg()) {
794 Error(
LHS->getStartLoc(),
"invalid register kind for this operand");
804 std::unique_ptr<SparcOperand>
RHS;
808 if (
RHS->isReg() && !
RHS->isIntReg()) {
809 Error(
RHS->getStartLoc(),
"invalid register kind for this operand");
821 Operands.push_back(SparcOperand::CreateMEMr(
LHS->getReg(),
S,
E));
825 template <
unsigned N>
835 if (getParser().parseExpression(Expr))
840 Error(
S,
"constant expression expected");
844 if (!isUInt<N>(
CE->getValue())) {
845 Error(
S,
"immediate shift value out of range");
849 Operands.push_back(SparcOperand::CreateImm(Expr,
S,
E));
858 std::unique_ptr<SparcOperand>
Mask;
860 if (!
Mask->isImm() || !
Mask->getImm()->evaluateAsAbsolute(ImmVal) ||
861 ImmVal < 0 || ImmVal > 127) {
862 Error(
S,
"invalid membar mask number");
868 SMLoc TagStart = getLexer().getLoc();
871 .
Case(
"LoadLoad", 0x1)
873 .
Case(
"LoadStore", 0x4)
874 .
Case(
"StoreStore", 0x8)
875 .
Case(
"Lookaside", 0x10)
876 .
Case(
"MemIssue", 0x20)
883 Error(TagStart,
"unknown membar tag");
895 Operands.push_back(SparcOperand::CreateImm(EVal,
S,
E));
903 switch (getLexer().getKind()) {
914 if (getParser().parseExpression(DestValue))
917 bool IsPic = getContext().getObjectFileInfo()->isPositionIndependent();
922 Operands.push_back(SparcOperand::CreateImm(DestExpr,
S,
E));
939 Operands.push_back(SparcOperand::CreateToken(
"[",
943 if (Mnemonic ==
"cas" || Mnemonic ==
"casx" || Mnemonic ==
"casa") {
949 unsigned RegNo, RegKind;
950 if (!matchRegisterName(Parser.
getTok(), RegNo, RegKind))
955 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind,
S,
E));
967 Operands.push_back(SparcOperand::CreateToken(
"]",
973 std::unique_ptr<SparcOperand>
Op;
974 ResTy = parseSparcAsmOperand(
Op,
false);
982 std::unique_ptr<SparcOperand>
Op;
984 ResTy = parseSparcAsmOperand(
Op, (Mnemonic ==
"call"));
995 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &
Op,
1002 switch (getLexer().getKind()) {
1009 if (matchRegisterName(Parser.
getTok(), RegNo, RegKind)) {
1015 Op = SparcOperand::CreateReg(RegNo, RegKind,
S,
E);
1018 Op = SparcOperand::CreateToken(
"%psr",
S);
1021 Op = SparcOperand::CreateToken(
"%fsr",
S);
1024 Op = SparcOperand::CreateToken(
"%fq",
S);
1027 Op = SparcOperand::CreateToken(
"%csr",
S);
1030 Op = SparcOperand::CreateToken(
"%cq",
S);
1033 Op = SparcOperand::CreateToken(
"%wim",
S);
1036 Op = SparcOperand::CreateToken(
"%tbr",
S);
1039 Op = SparcOperand::CreateToken(
"%pc",
S);
1043 Op = SparcOperand::CreateToken(
"%xcc",
S);
1045 Op = SparcOperand::CreateToken(
"%icc",
S);
1050 if (matchSparcAsmModifiers(EVal,
E)) {
1052 Op = SparcOperand::CreateImm(EVal,
S,
E);
1062 if (getParser().parseExpression(EVal,
E))
1066 if (!EVal->evaluateAsAbsolute(Res)) {
1069 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1077 Op = SparcOperand::CreateImm(EVal,
S,
E);
1093 if (modName ==
"a" || modName ==
"pn" || modName ==
"pt") {
1094 Operands.push_back(SparcOperand::CreateToken(modName,
1102 bool SparcAsmParser::matchRegisterName(
const AsmToken &Tok,
unsigned &RegNo,
1103 unsigned &RegKind) {
1106 RegKind = SparcOperand::rk_None;
1111 if (
name.equals(
"fp")) {
1113 RegKind = SparcOperand::rk_IntReg;
1117 if (
name.equals(
"sp")) {
1119 RegKind = SparcOperand::rk_IntReg;
1123 if (
name.equals(
"y")) {
1125 RegKind = SparcOperand::rk_Special;
1129 if (
name.substr(0, 3).equals_insensitive(
"asr") &&
1130 !
name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
1132 RegKind = SparcOperand::rk_Special;
1137 if (
name.equals(
"fprs")) {
1139 RegKind = SparcOperand::rk_Special;
1143 if (
name.equals(
"icc")) {
1145 RegKind = SparcOperand::rk_Special;
1149 if (
name.equals(
"psr")) {
1151 RegKind = SparcOperand::rk_Special;
1155 if (
name.equals(
"fsr")) {
1157 RegKind = SparcOperand::rk_Special;
1161 if (
name.equals(
"fq")) {
1163 RegKind = SparcOperand::rk_Special;
1167 if (
name.equals(
"csr")) {
1168 RegNo = Sparc::CPSR;
1169 RegKind = SparcOperand::rk_Special;
1173 if (
name.equals(
"cq")) {
1175 RegKind = SparcOperand::rk_Special;
1179 if (
name.equals(
"wim")) {
1181 RegKind = SparcOperand::rk_Special;
1185 if (
name.equals(
"tbr")) {
1187 RegKind = SparcOperand::rk_Special;
1191 if (
name.equals(
"xcc")) {
1194 RegKind = SparcOperand::rk_Special;
1199 if (
name.substr(0, 3).equals_insensitive(
"fcc") &&
1200 !
name.substr(3).getAsInteger(10, intVal) && intVal < 4) {
1202 RegNo = Sparc::FCC0 + intVal;
1203 RegKind = SparcOperand::rk_Special;
1208 if (
name.substr(0, 1).equals_insensitive(
"g") &&
1209 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1211 RegKind = SparcOperand::rk_IntReg;
1215 if (
name.substr(0, 1).equals_insensitive(
"o") &&
1216 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1218 RegKind = SparcOperand::rk_IntReg;
1221 if (
name.substr(0, 1).equals_insensitive(
"l") &&
1222 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1224 RegKind = SparcOperand::rk_IntReg;
1227 if (
name.substr(0, 1).equals_insensitive(
"i") &&
1228 !
name.substr(1).getAsInteger(10, intVal) && intVal < 8) {
1230 RegKind = SparcOperand::rk_IntReg;
1234 if (
name.substr(0, 1).equals_insensitive(
"f") &&
1235 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1237 RegKind = SparcOperand::rk_FloatReg;
1241 if (
name.substr(0, 1).equals_insensitive(
"f") &&
1242 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal >= 32 &&
1243 intVal <= 62 && (intVal % 2 == 0)) {
1246 RegKind = SparcOperand::rk_DoubleReg;
1251 if (
name.substr(0, 1).equals_insensitive(
"r") &&
1252 !
name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1254 RegKind = SparcOperand::rk_IntReg;
1259 if (
name.substr(0, 1).equals_insensitive(
"c") &&
1260 !
name.substr(1).getAsInteger(10, intVal) && intVal < 32) {
1262 RegKind = SparcOperand::rk_CoprocReg;
1266 if (
name.equals(
"tpc")) {
1268 RegKind = SparcOperand::rk_Special;
1271 if (
name.equals(
"tnpc")) {
1272 RegNo = Sparc::TNPC;
1273 RegKind = SparcOperand::rk_Special;
1276 if (
name.equals(
"tstate")) {
1277 RegNo = Sparc::TSTATE;
1278 RegKind = SparcOperand::rk_Special;
1281 if (
name.equals(
"tt")) {
1283 RegKind = SparcOperand::rk_Special;
1286 if (
name.equals(
"tick")) {
1287 RegNo = Sparc::TICK;
1288 RegKind = SparcOperand::rk_Special;
1291 if (
name.equals(
"tba")) {
1293 RegKind = SparcOperand::rk_Special;
1296 if (
name.equals(
"pstate")) {
1297 RegNo = Sparc::PSTATE;
1298 RegKind = SparcOperand::rk_Special;
1301 if (
name.equals(
"tl")) {
1303 RegKind = SparcOperand::rk_Special;
1306 if (
name.equals(
"pil")) {
1308 RegKind = SparcOperand::rk_Special;
1311 if (
name.equals(
"cwp")) {
1313 RegKind = SparcOperand::rk_Special;
1316 if (
name.equals(
"cansave")) {
1317 RegNo = Sparc::CANSAVE;
1318 RegKind = SparcOperand::rk_Special;
1321 if (
name.equals(
"canrestore")) {
1322 RegNo = Sparc::CANRESTORE;
1323 RegKind = SparcOperand::rk_Special;
1326 if (
name.equals(
"cleanwin")) {
1327 RegNo = Sparc::CLEANWIN;
1328 RegKind = SparcOperand::rk_Special;
1331 if (
name.equals(
"otherwin")) {
1332 RegNo = Sparc::OTHERWIN;
1333 RegKind = SparcOperand::rk_Special;
1336 if (
name.equals(
"wstate")) {
1337 RegNo = Sparc::WSTATE;
1338 RegKind = SparcOperand::rk_Special;
1341 if (
name.equals(
"pc")) {
1343 RegKind = SparcOperand::rk_Special;
1355 if (
const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1386 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1403 bool SparcAsmParser::matchSparcAsmModifiers(
const MCExpr *&EVal,
1425 EVal = adjustPICRelocation(VK, subExpr);
1435 #define GET_REGISTER_MATCHER
1436 #define GET_MATCHER_IMPLEMENTATION
1437 #include "SparcGenAsmMatcher.inc"
1441 SparcOperand &
Op = (SparcOperand &)GOp;
1442 if (
Op.isFloatOrDoubleReg()) {
1446 if (!
Op.isFloatReg() || SparcOperand::MorphToDoubleReg(
Op))
1450 if (SparcOperand::MorphToQuadReg(
Op))
1455 if (
Op.isIntReg() &&
Kind == MCK_IntPair) {
1456 if (SparcOperand::MorphToIntPairReg(
Op))
1459 if (
Op.isCoprocReg() &&
Kind == MCK_CoprocPair) {
1460 if (SparcOperand::MorphToCoprocPairReg(
Op))
1463 return Match_InvalidOperand;