LLVM  15.0.0git
SparcMCTargetDesc.h
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1 //===-- SparcMCTargetDesc.h - Sparc Target Descriptions ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Sparc specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 
18 #include <memory>
19 
20 namespace llvm {
21 class MCAsmBackend;
22 class MCCodeEmitter;
23 class MCContext;
24 class MCInstrInfo;
25 class MCObjectTargetWriter;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class MCTargetOptions;
29 class Target;
30 
31 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
32  MCContext &Ctx);
33 MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
34  const MCRegisterInfo &MRI,
35  const MCTargetOptions &Options);
36 std::unique_ptr<MCObjectTargetWriter> createSparcELFObjectWriter(bool Is64Bit,
37  uint8_t OSABI);
38 } // End llvm namespace
39 
40 // Defines symbolic names for Sparc registers. This defines a mapping from
41 // register name to register number.
42 //
43 #define GET_REGINFO_ENUM
44 #include "SparcGenRegisterInfo.inc"
45 
46 // Defines symbolic names for the Sparc instructions.
47 //
48 #define GET_INSTRINFO_ENUM
49 #include "SparcGenInstrInfo.inc"
50 
51 #define GET_SUBTARGETINFO_ENUM
52 #include "SparcGenSubtargetInfo.inc"
53 
54 #endif
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::createSparcELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Definition: SparcELFObjectWriter.cpp:147
llvm::createSparcMCCodeEmitter
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SparcMCCodeEmitter.cpp:259
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:855
T
#define T
Definition: Mips16ISelLowering.cpp:341
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
DataTypes.h
llvm::createSparcAsmBackend
MCAsmBackend * createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: SparcAsmBackend.cpp:371