LLVM  14.0.0git
SparcAsmBackend.cpp
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1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
11 #include "llvm/MC/MCAsmBackend.h"
13 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCObjectWriter.h"
17 #include "llvm/MC/MCValue.h"
18 #include "llvm/MC/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
24  switch (Kind) {
25  default:
26  llvm_unreachable("Unknown fixup kind!");
27  case FK_Data_1:
28  case FK_Data_2:
29  case FK_Data_4:
30  case FK_Data_8:
31  return Value;
32 
35  return (Value >> 2) & 0x3fffffff;
36 
38  return (Value >> 2) & 0x3fffff;
39 
41  return (Value >> 2) & 0x7ffff;
42 
44  return (Value >> 2) & 0xc000;
45 
47  return (Value >> 2) & 0x3fff;
48 
56  return (Value >> 10) & 0x3fffff;
57 
60  return Value & 0x1fff;
61 
68  return Value & 0x3ff;
69 
71  return (Value >> 22) & 0x3fffff;
72 
74  return (Value >> 12) & 0x3ff;
75 
77  return Value & 0xfff;
78 
80  return (Value >> 42) & 0x3fffff;
81 
83  return (Value >> 32) & 0x3ff;
84 
89  assert(Value == 0 && "Sparc TLS relocs expect zero Value");
90  return 0;
91 
100  return 0;
101  }
102 }
103 
104 /// getFixupKindNumBytes - The number of bytes the fixup may change.
105 static unsigned getFixupKindNumBytes(unsigned Kind) {
106  switch (Kind) {
107  default:
108  return 4;
109  case FK_Data_1:
110  return 1;
111  case FK_Data_2:
112  return 2;
113  case FK_Data_8:
114  return 8;
115  }
116 }
117 
118 namespace {
119  class SparcAsmBackend : public MCAsmBackend {
120  protected:
121  const Target &TheTarget;
122  bool Is64Bit;
123 
124  public:
125  SparcAsmBackend(const Target &T)
126  : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little
127  : support::big),
128  TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
129 
130  unsigned getNumFixupKinds() const override {
132  }
133 
134  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
135  const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
136  // name offset bits flags
137  { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
138  { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
139  { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
140  { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
141  { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
142  { "fixup_sparc_13", 19, 13, 0 },
143  { "fixup_sparc_hi22", 10, 22, 0 },
144  { "fixup_sparc_lo10", 22, 10, 0 },
145  { "fixup_sparc_h44", 10, 22, 0 },
146  { "fixup_sparc_m44", 22, 10, 0 },
147  { "fixup_sparc_l44", 20, 12, 0 },
148  { "fixup_sparc_hh", 10, 22, 0 },
149  { "fixup_sparc_hm", 22, 10, 0 },
150  { "fixup_sparc_lm", 10, 22, 0 },
151  { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
152  { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
153  { "fixup_sparc_got22", 10, 22, 0 },
154  { "fixup_sparc_got10", 22, 10, 0 },
155  { "fixup_sparc_got13", 19, 13, 0 },
156  { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
157  { "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
158  { "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
159  { "fixup_sparc_tls_gd_add", 0, 0, 0 },
160  { "fixup_sparc_tls_gd_call", 0, 0, 0 },
161  { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
162  { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
163  { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
164  { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
165  { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
166  { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
167  { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
168  { "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
169  { "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
170  { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
171  { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
172  { "fixup_sparc_tls_ie_add", 0, 0, 0 },
173  { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
174  { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
175  };
176 
177  const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
178  // name offset bits flags
179  { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
180  { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
181  { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
182  { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
183  { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
184  { "fixup_sparc_13", 0, 13, 0 },
185  { "fixup_sparc_hi22", 0, 22, 0 },
186  { "fixup_sparc_lo10", 0, 10, 0 },
187  { "fixup_sparc_h44", 0, 22, 0 },
188  { "fixup_sparc_m44", 0, 10, 0 },
189  { "fixup_sparc_l44", 0, 12, 0 },
190  { "fixup_sparc_hh", 0, 22, 0 },
191  { "fixup_sparc_hm", 0, 10, 0 },
192  { "fixup_sparc_lm", 0, 22, 0 },
193  { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
194  { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
195  { "fixup_sparc_got22", 0, 22, 0 },
196  { "fixup_sparc_got10", 0, 10, 0 },
197  { "fixup_sparc_got13", 0, 13, 0 },
198  { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
199  { "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
200  { "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
201  { "fixup_sparc_tls_gd_add", 0, 0, 0 },
202  { "fixup_sparc_tls_gd_call", 0, 0, 0 },
203  { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
204  { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
205  { "fixup_sparc_tls_ldm_add", 0, 0, 0 },
206  { "fixup_sparc_tls_ldm_call", 0, 0, 0 },
207  { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
208  { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
209  { "fixup_sparc_tls_ldo_add", 0, 0, 0 },
210  { "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
211  { "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
212  { "fixup_sparc_tls_ie_ld", 0, 0, 0 },
213  { "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
214  { "fixup_sparc_tls_ie_add", 0, 0, 0 },
215  { "fixup_sparc_tls_le_hix22", 0, 0, 0 },
216  { "fixup_sparc_tls_le_lox10", 0, 0, 0 }
217  };
218 
221 
222  assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
223  "Invalid kind!");
224  if (Endian == support::little)
225  return InfosLE[Kind - FirstTargetFixupKind];
226 
227  return InfosBE[Kind - FirstTargetFixupKind];
228  }
229 
230  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
231  const MCValue &Target) override {
232  switch ((Sparc::Fixups)Fixup.getKind()) {
233  default:
234  return false;
236  if (Target.getSymA()->getSymbol().isTemporary())
237  return false;
257  return true;
258  }
259  }
260 
261  /// fixupNeedsRelaxation - Target specific predicate for whether a given
262  /// fixup requires the associated instruction to be relaxed.
263  bool fixupNeedsRelaxation(const MCFixup &Fixup,
264  uint64_t Value,
265  const MCRelaxableFragment *DF,
266  const MCAsmLayout &Layout) const override {
267  // FIXME.
268  llvm_unreachable("fixupNeedsRelaxation() unimplemented");
269  return false;
270  }
271  void relaxInstruction(MCInst &Inst,
272  const MCSubtargetInfo &STI) const override {
273  // FIXME.
274  llvm_unreachable("relaxInstruction() unimplemented");
275  }
276 
277  bool writeNopData(raw_ostream &OS, uint64_t Count,
278  const MCSubtargetInfo *STI) const override {
279  // Cannot emit NOP with size not multiple of 32 bits.
280  if (Count % 4 != 0)
281  return false;
282 
283  uint64_t NumNops = Count / 4;
284  for (uint64_t i = 0; i != NumNops; ++i)
285  support::endian::write<uint32_t>(OS, 0x01000000, Endian);
286 
287  return true;
288  }
289  };
290 
291  class ELFSparcAsmBackend : public SparcAsmBackend {
292  Triple::OSType OSType;
293  public:
294  ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
295  SparcAsmBackend(T), OSType(OSType) { }
296 
297  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
299  uint64_t Value, bool IsResolved,
300  const MCSubtargetInfo *STI) const override {
301 
302  Value = adjustFixupValue(Fixup.getKind(), Value);
303  if (!Value) return; // Doesn't change encoding.
304 
305  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
306  unsigned Offset = Fixup.getOffset();
307  // For each byte of the fragment that the fixup touches, mask in the bits
308  // from the fixup value. The Value has been "split up" into the
309  // appropriate bitfields above.
310  for (unsigned i = 0; i != NumBytes; ++i) {
311  unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i;
312  Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
313  }
314  }
315 
316  std::unique_ptr<MCObjectTargetWriter>
317  createObjectTargetWriter() const override {
318  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
319  return createSparcELFObjectWriter(Is64Bit, OSABI);
320  }
321  };
322 
323 } // end anonymous namespace
324 
326  const MCSubtargetInfo &STI,
327  const MCRegisterInfo &MRI,
328  const MCTargetOptions &Options) {
329  return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
330 }
i
i
Definition: README.txt:29
llvm::Sparc::fixup_sparc_br22
@ fixup_sparc_br22
fixup_sparc_br22 - 22-bit PC relative relocation for branches
Definition: SparcFixupKinds.h:22
llvm::Sparc::fixup_sparc_br19
@ fixup_sparc_br19
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
Definition: SparcFixupKinds.h:26
getName
static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
getFixupKindNumBytes - The number of bytes the fixup may change.
Definition: SparcAsmBackend.cpp:105
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
llvm::Sparc::fixup_sparc_br16_2
@ fixup_sparc_br16_2
fixup_sparc_bpr - 16-bit fixup for bpr
Definition: SparcFixupKinds.h:29
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:74
T
llvm::createSparcELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Definition: SparcELFObjectWriter.cpp:138
SparcMCTargetDesc.h
llvm::Sparc::fixup_sparc_wplt30
@ fixup_sparc_wplt30
fixup_sparc_wplt30
Definition: SparcFixupKinds.h:76
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::Sparc::fixup_sparc_tls_ie_add
@ fixup_sparc_tls_ie_add
Definition: SparcFixupKinds.h:94
llvm::Sparc::fixup_sparc_tls_gd_add
@ fixup_sparc_tls_gd_add
Definition: SparcFixupKinds.h:81
llvm::Sparc::fixup_sparc_tls_gd_hi22
@ fixup_sparc_tls_gd_hi22
fixups for Thread Local Storage
Definition: SparcFixupKinds.h:79
MCFixupKindInfo.h
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Sparc::fixup_sparc_tls_ie_hi22
@ fixup_sparc_tls_ie_hi22
Definition: SparcFixupKinds.h:90
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::Sparc::fixup_sparc_hi22
@ fixup_sparc_hi22
fixup_sparc_hi22 - 22-bit fixup corresponding to hi(foo) for sethi
Definition: SparcFixupKinds.h:37
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::Sparc::fixup_sparc_br16_14
@ fixup_sparc_br16_14
Definition: SparcFixupKinds.h:30
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:36
llvm::Sparc::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: SparcFixupKinds.h:100
MCAsmBackend.h
llvm::MutableArrayRef< char >
SparcFixupKinds.h
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:107
llvm::Sparc::fixup_sparc_h44
@ fixup_sparc_h44
fixup_sparc_h44 - 22-bit fixup corresponding to h44(foo)
Definition: SparcFixupKinds.h:43
llvm::Sparc::fixup_sparc_pc22
@ fixup_sparc_pc22
fixup_sparc_pc22 - 22-bit fixup corresponding to pc22(foo)
Definition: SparcFixupKinds.h:61
MCSubtargetInfo.h
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::Sparc::fixup_sparc_tls_ldo_lox10
@ fixup_sparc_tls_ldo_lox10
Definition: SparcFixupKinds.h:88
llvm::Sparc::fixup_sparc_tls_ie_ldx
@ fixup_sparc_tls_ie_ldx
Definition: SparcFixupKinds.h:93
llvm::Sparc::fixup_sparc_tls_ie_ld
@ fixup_sparc_tls_ie_ld
Definition: SparcFixupKinds.h:92
llvm::Sparc::fixup_sparc_tls_ie_lo10
@ fixup_sparc_tls_ie_lo10
Definition: SparcFixupKinds.h:91
llvm::Sparc::fixup_sparc_13
@ fixup_sparc_13
fixup_sparc_13 - 13-bit fixup
Definition: SparcFixupKinds.h:33
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCAssembler
Definition: MCAssembler.h:60
uint64_t
llvm::Sparc::fixup_sparc_tls_ldm_call
@ fixup_sparc_tls_ldm_call
Definition: SparcFixupKinds.h:86
llvm::Triple::getOS
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:321
MCELFObjectWriter.h
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
llvm::Sparc::fixup_sparc_tls_ldo_add
@ fixup_sparc_tls_ldo_add
Definition: SparcFixupKinds.h:89
llvm::Sparc::fixup_sparc_tls_gd_call
@ fixup_sparc_tls_gd_call
Definition: SparcFixupKinds.h:82
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::Sparc::fixup_sparc_tls_ldm_lo10
@ fixup_sparc_tls_ldm_lo10
Definition: SparcFixupKinds.h:84
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::Sparc::fixup_sparc_tls_le_lox10
@ fixup_sparc_tls_le_lox10
Definition: SparcFixupKinds.h:96
llvm::MCELFObjectTargetWriter::getOSABI
uint8_t getOSABI() const
Definition: MCELFObjectWriter.h:101
llvm::Sparc::fixup_sparc_got13
@ fixup_sparc_got13
fixup_sparc_got13 - 13-bit fixup corresponding to got13(foo)
Definition: SparcFixupKinds.h:73
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm::Sparc::fixup_sparc_pc10
@ fixup_sparc_pc10
fixup_sparc_pc10 - 10-bit fixup corresponding to pc10(foo)
Definition: SparcFixupKinds.h:64
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Sparc::fixup_sparc_tls_gd_lo10
@ fixup_sparc_tls_gd_lo10
Definition: SparcFixupKinds.h:80
llvm::Sparc::fixup_sparc_l44
@ fixup_sparc_l44
fixup_sparc_l44 - 12-bit fixup corresponding to l44(foo)
Definition: SparcFixupKinds.h:49
llvm::Sparc::Fixups
Fixups
Definition: SparcFixupKinds.h:16
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:286
llvm::Sparc::fixup_sparc_tls_le_hix22
@ fixup_sparc_tls_le_hix22
Definition: SparcFixupKinds.h:95
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
MCObjectWriter.h
llvm::Triple::OSType
OSType
Definition: Triple.h:169
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::Sparc::fixup_sparc_m44
@ fixup_sparc_m44
fixup_sparc_m44 - 10-bit fixup corresponding to m44(foo)
Definition: SparcFixupKinds.h:46
llvm::Sparc::fixup_sparc_tls_ldo_hix22
@ fixup_sparc_tls_ldo_hix22
Definition: SparcFixupKinds.h:87
llvm::Sparc::fixup_sparc_call30
@ fixup_sparc_call30
Definition: SparcFixupKinds.h:18
llvm::Sparc::fixup_sparc_lo10
@ fixup_sparc_lo10
fixup_sparc_lo10 - 10-bit fixup corresponding to lo(foo)
Definition: SparcFixupKinds.h:40
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::Sparc::fixup_sparc_hh
@ fixup_sparc_hh
fixup_sparc_hh - 22-bit fixup corresponding to hh(foo)
Definition: SparcFixupKinds.h:52
MCValue.h
llvm::Sparc::fixup_sparc_got22
@ fixup_sparc_got22
fixup_sparc_got22 - 22-bit fixup corresponding to got22(foo)
Definition: SparcFixupKinds.h:67
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:37
llvm::Sparc::fixup_sparc_tls_ldm_hi22
@ fixup_sparc_tls_ldm_hi22
Definition: SparcFixupKinds.h:83
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
llvm::Sparc::fixup_sparc_got10
@ fixup_sparc_got10
fixup_sparc_got10 - 10-bit fixup corresponding to got10(foo)
Definition: SparcFixupKinds.h:70
TargetRegistry.h
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::Sparc::fixup_sparc_lm
@ fixup_sparc_lm
fixup_sparc_lm - 22-bit fixup corresponding to lm(foo)
Definition: SparcFixupKinds.h:58
llvm::Sparc::fixup_sparc_tls_ldm_add
@ fixup_sparc_tls_ldm_add
Definition: SparcFixupKinds.h:85
llvm::support::big
@ big
Definition: Endian.h:27
adjustFixupValue
static unsigned adjustFixupValue(unsigned Kind, uint64_t Value)
Definition: SparcAsmBackend.cpp:23
llvm::Sparc::fixup_sparc_hm
@ fixup_sparc_hm
fixup_sparc_hm - 10-bit fixup corresponding to hm(foo)
Definition: SparcFixupKinds.h:55
llvm::createSparcAsmBackend
MCAsmBackend * createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: SparcAsmBackend.cpp:325