LLVM 17.0.0git
SparcMCCodeEmitter.cpp
Go to the documentation of this file.
1//===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SparcMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
14#include "SparcMCExpr.h"
15#include "SparcMCTargetDesc.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/MC/MCAsmInfo.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCFixup.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCSymbol.h"
31#include "llvm/Support/Endian.h"
35#include <cassert>
36#include <cstdint>
37
38using namespace llvm;
39
40#define DEBUG_TYPE "mccodeemitter"
41
42STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43
44namespace {
45
46class SparcMCCodeEmitter : public MCCodeEmitter {
47 MCContext &Ctx;
48
49public:
50 SparcMCCodeEmitter(const MCInstrInfo &, MCContext &ctx)
51 : Ctx(ctx) {}
52 SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
53 SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
54 ~SparcMCCodeEmitter() override = default;
55
56 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
58 const MCSubtargetInfo &STI) const override;
59
60 // getBinaryCodeForInstr - TableGen'erated function for getting the
61 // binary encoding for an instruction.
62 uint64_t getBinaryCodeForInstr(const MCInst &MI,
64 const MCSubtargetInfo &STI) const;
65
66 /// getMachineOpValue - Return binary encoding of operand. If the machine
67 /// operand requires relocation, record the relocation and return zero.
68 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70 const MCSubtargetInfo &STI) const;
71 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
73 const MCSubtargetInfo &STI) const;
74 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
76 const MCSubtargetInfo &STI) const;
77 unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
79 const MCSubtargetInfo &STI) const;
80 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
82 const MCSubtargetInfo &STI) const;
83 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
85 const MCSubtargetInfo &STI) const;
86};
87
88} // end anonymous namespace
89
90void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
92 const MCSubtargetInfo &STI) const {
93 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
95 Ctx.getAsmInfo()->isLittleEndian() ? support::little
96 : support::big);
97
98 // Some instructions have phantom operands that only contribute a fixup entry.
99 unsigned SymOpNo = 0;
100 switch (MI.getOpcode()) {
101 default: break;
102 case SP::TLS_CALL: SymOpNo = 1; break;
103 case SP::GDOP_LDrr:
104 case SP::GDOP_LDXrr:
105 case SP::TLS_ADDrr:
106 case SP::TLS_ADDXrr:
107 case SP::TLS_LDrr:
108 case SP::TLS_LDXrr: SymOpNo = 3; break;
109 }
110 if (SymOpNo != 0) {
111 const MCOperand &MO = MI.getOperand(SymOpNo);
112 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
113 assert(op == 0 && "Unexpected operand value!");
114 (void)op; // suppress warning.
115 }
116
117 ++MCNumEmitted; // Keep track of the # of mi's emitted.
118}
119
120unsigned SparcMCCodeEmitter::
121getMachineOpValue(const MCInst &MI, const MCOperand &MO,
123 const MCSubtargetInfo &STI) const {
124 if (MO.isReg())
125 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
126
127 if (MO.isImm())
128 return MO.getImm();
129
130 assert(MO.isExpr());
131 const MCExpr *Expr = MO.getExpr();
132 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
133 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
134 Fixups.push_back(MCFixup::create(0, Expr, Kind));
135 return 0;
136 }
137
138 int64_t Res;
139 if (Expr->evaluateAsAbsolute(Res))
140 return Res;
141
142 llvm_unreachable("Unhandled expression!");
143 return 0;
144}
145
146unsigned
147SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
149 const MCSubtargetInfo &STI) const {
150 const MCOperand &MO = MI.getOperand(OpNo);
151
152 if (MO.isImm())
153 return MO.getImm();
154
155 assert(MO.isExpr() &&
156 "getSImm13OpValue expects only expressions or an immediate");
157
158 const MCExpr *Expr = MO.getExpr();
159
160 // Constant value, no fixup is needed
161 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
162 return CE->getValue();
163
165 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
166 Kind = MCFixupKind(SExpr->getFixupKind());
167 } else {
168 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
170 : MCFixupKind(Sparc::fixup_sparc_13);
171 }
172
173 Fixups.push_back(MCFixup::create(0, Expr, Kind));
174 return 0;
175}
176
177unsigned SparcMCCodeEmitter::
178getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
180 const MCSubtargetInfo &STI) const {
181 const MCOperand &MO = MI.getOperand(OpNo);
182 const MCExpr *Expr = MO.getExpr();
183 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
184
185 if (MI.getOpcode() == SP::TLS_CALL) {
186 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
187 // encodeInstruction.
188#ifndef NDEBUG
189 // Verify that the callee is actually __tls_get_addr.
190 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
191 "Unexpected expression in TLS_CALL");
192 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
193 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
194 "Unexpected function for TLS_CALL");
195#endif
196 return 0;
197 }
198
200 Fixups.push_back(MCFixup::create(0, Expr, Kind));
201 return 0;
202}
203
204unsigned SparcMCCodeEmitter::
205getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
207 const MCSubtargetInfo &STI) const {
208 const MCOperand &MO = MI.getOperand(OpNo);
209 if (MO.isReg() || MO.isImm())
210 return getMachineOpValue(MI, MO, Fixups, STI);
211
212 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
214 return 0;
215}
216
217unsigned SparcMCCodeEmitter::
218getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
220 const MCSubtargetInfo &STI) const {
221 const MCOperand &MO = MI.getOperand(OpNo);
222 if (MO.isReg() || MO.isImm())
223 return getMachineOpValue(MI, MO, Fixups, STI);
224
225 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
227 return 0;
228}
229
230unsigned SparcMCCodeEmitter::
231getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
233 const MCSubtargetInfo &STI) const {
234 const MCOperand &MO = MI.getOperand(OpNo);
235 if (MO.isReg() || MO.isImm())
236 return getMachineOpValue(MI, MO, Fixups, STI);
237
238 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
240 Fixups.push_back(MCFixup::create(0, MO.getExpr(),
242
243 return 0;
244}
245
246#include "SparcGenMCCodeEmitter.inc"
247
249 MCContext &Ctx) {
250 return new SparcMCCodeEmitter(MCII, Ctx);
251}
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
#define op(i)
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Definition: Statistic.h:167
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
ExprKind getKind() const
Definition: MCExpr.h:81
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:87
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
const MCExpr * getExpr() const
Definition: MCInst.h:114
bool isExpr() const
Definition: MCInst.h:65
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
const MCSymbol & getSymbol() const
Definition: MCExpr.h:399
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:203
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: SparcMCExpr.h:90
Sparc::Fixups getFixupKind() const
getFixupKind - Get the fixup kind of this expression.
Definition: SparcMCExpr.h:93
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_sparc_got13
fixup_sparc_got13 - 13-bit fixup corresponding to got13(foo)
@ fixup_sparc_br19
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
@ fixup_sparc_13
fixup_sparc_13 - 13-bit fixup
@ fixup_sparc_br16_2
fixup_sparc_bpr - 16-bit fixup for bpr
@ fixup_sparc_br22
fixup_sparc_br22 - 22-bit PC relative relocation for branches
@ CE
Windows NT (Windows on ARM)
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)