40#define DEBUG_TYPE "mccodeemitter"
42STATISTIC(MCNumEmitted,
"Number of MC instructions emitted");
52 SparcMCCodeEmitter(
const SparcMCCodeEmitter &) =
delete;
53 SparcMCCodeEmitter &
operator=(
const SparcMCCodeEmitter &) =
delete;
54 ~SparcMCCodeEmitter()
override =
default;
71 unsigned getCallTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
77 unsigned getSImm13OpValue(
const MCInst &
MI,
unsigned OpNo,
80 unsigned getBranchPredTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
83 unsigned getBranchOnRegTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
93 unsigned Bits = getBinaryCodeForInstr(
MI, Fixups, STI);
100 switch (
MI.getOpcode()) {
102 case SP::TLS_CALL: SymOpNo = 1;
break;
108 case SP::TLS_LDXrr: SymOpNo = 3;
break;
113 assert(
op == 0 &&
"Unexpected operand value!");
120unsigned SparcMCCodeEmitter::
125 return Ctx.getRegisterInfo()->getEncodingValue(MO.
getReg());
132 if (
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
139 if (Expr->evaluateAsAbsolute(Res))
147SparcMCCodeEmitter::getSImm13OpValue(
const MCInst &
MI,
unsigned OpNo,
156 "getSImm13OpValue expects only expressions or an immediate");
162 return CE->getValue();
165 if (
const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
168 bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
177unsigned SparcMCCodeEmitter::
178getCallTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
183 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
185 if (
MI.getOpcode() == SP::TLS_CALL) {
191 "Unexpected expression in TLS_CALL");
194 "Unexpected function for TLS_CALL");
204unsigned SparcMCCodeEmitter::
205getBranchTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
210 return getMachineOpValue(
MI, MO, Fixups, STI);
217unsigned SparcMCCodeEmitter::
218getBranchPredTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
223 return getMachineOpValue(
MI, MO, Fixups, STI);
230unsigned SparcMCCodeEmitter::
231getBranchOnRegTargetOpValue(
const MCInst &
MI,
unsigned OpNo,
236 return getMachineOpValue(
MI, MO, Fixups, STI);
246#include "SparcGenMCCodeEmitter.inc"
250 return new SparcMCCodeEmitter(MCII, Ctx);
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
@ SymbolRef
References to labels and assigned expressions.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
const MCSymbol & getSymbol() const
StringRef getName() const
getName - Get the symbol name.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Sparc::Fixups getFixupKind() const
getFixupKind - Get the fixup kind of this expression.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ fixup_sparc_got13
fixup_sparc_got13 - 13-bit fixup corresponding to got13(foo)
@ fixup_sparc_br19
fixup_sparc_br19 - 19-bit PC relative relocation for branches on icc/xcc
@ fixup_sparc_13
fixup_sparc_13 - 13-bit fixup
@ fixup_sparc_br16_2
fixup_sparc_bpr - 16-bit fixup for bpr
@ fixup_sparc_br22
fixup_sparc_br22 - 22-bit PC relative relocation for branches
@ CE
Windows NT (Windows on ARM)
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
MCCodeEmitter * createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)