43#define DEBUG_TYPE "mccodeemitter"
45STATISTIC(MCNumEmitted,
"Number of MC instructions emitted.");
46STATISTIC(MCNumCPRelocations,
"Number of constant pool relocations created.");
57 : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
59 ARMMCCodeEmitter(
const ARMMCCodeEmitter &) =
delete;
60 ARMMCCodeEmitter &
operator=(
const ARMMCCodeEmitter &) =
delete;
61 ~ARMMCCodeEmitter()
override =
default;
73 return TT.isOSBinFormatMachO();
76 unsigned getMachineSoImmOpValue(
unsigned SoImm)
const;
97 bool EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
98 unsigned &Reg,
unsigned &Imm,
206 template<
unsigned Bits,
unsigned Shift>
306 unsigned getCCOutOpValue(
const MCInst &
MI,
unsigned Op,
311 return MI.getOperand(Op).getReg() == ARM::CPSR;
314 unsigned getModImmOpValue(
const MCInst &
MI,
unsigned Op,
333 unsigned getT2SOImmOpValue(
const MCInst &
MI,
unsigned Op,
346 unsigned SoImm = MO.
getImm();
348 assert(Encoded != ~0U &&
"Not a Thumb2 so_imm value?");
352 unsigned getT2AddrModeSORegOpValue(
const MCInst &
MI,
unsigned OpNum,
355 template<
unsigned Bits,
unsigned Shift>
356 unsigned getT2AddrModeImmOpValue(
const MCInst &
MI,
unsigned OpNum,
359 unsigned getT2AddrModeImm8OffsetOpValue(
const MCInst &
MI,
unsigned OpNum,
364 unsigned getSORegRegOpValue(
const MCInst &
MI,
unsigned Op,
367 unsigned getSORegImmOpValue(
const MCInst &
MI,
unsigned Op,
370 unsigned getT2SORegOpValue(
const MCInst &
MI,
unsigned Op,
374 unsigned getNEONVcvtImm32OpValue(
const MCInst &
MI,
unsigned Op,
377 return 64 -
MI.getOperand(Op).getImm();
380 unsigned getBitfieldInvertedMaskOpValue(
const MCInst &
MI,
unsigned Op,
384 unsigned getRegisterListOpValue(
const MCInst &
MI,
unsigned Op,
387 unsigned getAddrMode6AddressOpValue(
const MCInst &
MI,
unsigned Op,
390 unsigned getAddrMode6OneLane32AddressOpValue(
const MCInst &
MI,
unsigned Op,
393 unsigned getAddrMode6DupAddressOpValue(
const MCInst &
MI,
unsigned Op,
396 unsigned getAddrMode6OffsetOpValue(
const MCInst &
MI,
unsigned Op,
400 unsigned getShiftRight8Imm(
const MCInst &
MI,
unsigned Op,
403 unsigned getShiftRight16Imm(
const MCInst &
MI,
unsigned Op,
406 unsigned getShiftRight32Imm(
const MCInst &
MI,
unsigned Op,
409 unsigned getShiftRight64Imm(
const MCInst &
MI,
unsigned Op,
413 unsigned getThumbSRImmOpValue(
const MCInst &
MI,
unsigned Op,
417 unsigned NEONThumb2DataIPostEncoder(
const MCInst &
MI,
418 unsigned EncodedValue,
420 unsigned NEONThumb2LoadStorePostEncoder(
const MCInst &
MI,
421 unsigned EncodedValue,
423 unsigned NEONThumb2DupPostEncoder(
const MCInst &
MI,
424 unsigned EncodedValue,
426 unsigned NEONThumb2V8PostEncoder(
const MCInst &
MI,
427 unsigned EncodedValue,
430 unsigned VFPThumb2PostEncoder(
const MCInst &
MI,
431 unsigned EncodedValue,
444 for (
unsigned i = 0; i !=
Size; ++i) {
445 unsigned Shift = IsLittleEndian ? i * 8 : (
Size - 1 - i) * 8;
446 EmitByte((Val >> Shift) & 0xff,
OS);
454 template <
bool isNeg, ARM::Fixups fixup>
469 template <
unsigned size>
480unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(
const MCInst &
MI,
481 unsigned EncodedValue,
487 unsigned Bit24 = EncodedValue & 0x01000000;
488 unsigned Bit28 = Bit24 << 4;
489 EncodedValue &= 0xEFFFFFFF;
490 EncodedValue |= Bit28;
491 EncodedValue |= 0x0F000000;
500unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(
const MCInst &
MI,
501 unsigned EncodedValue,
504 EncodedValue &= 0xF0FFFFFF;
505 EncodedValue |= 0x09000000;
514unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(
const MCInst &
MI,
515 unsigned EncodedValue,
518 EncodedValue &= 0x00FFFFFF;
519 EncodedValue |= 0xEE000000;
527unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(
const MCInst &
MI,
528 unsigned EncodedValue,
531 EncodedValue |= 0xC000000;
539unsigned ARMMCCodeEmitter::
540VFPThumb2PostEncoder(
const MCInst &
MI,
unsigned EncodedValue,
543 EncodedValue &= 0x0FFFFFFF;
544 EncodedValue |= 0xE0000000;
551unsigned ARMMCCodeEmitter::
571 case ARM::Q0:
case ARM::Q1:
case ARM::Q2:
case ARM::Q3:
572 case ARM::Q4:
case ARM::Q5:
case ARM::Q6:
case ARM::Q7:
573 case ARM::Q8:
case ARM::Q9:
case ARM::Q10:
case ARM::Q11:
574 case ARM::Q12:
case ARM::Q13:
case ARM::Q14:
case ARM::Q15:
577 }
else if (MO.
isImm()) {
578 return static_cast<unsigned>(MO.
getImm());
590bool ARMMCCodeEmitter::
591EncodeAddrModeOpValues(
const MCInst &
MI,
unsigned OpIdx,
unsigned &Reg,
599 int32_t SImm = MO1.
getImm();
603 if (SImm == INT32_MIN) {
628 assert(MO.
isExpr() &&
"Unexpected branch target type!");
641 uint32_t S = (offset & 0x800000) >> 23;
642 uint32_t J1 = (offset & 0x400000) >> 22;
643 uint32_t J2 = (offset & 0x200000) >> 21;
658getThumbBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
671getThumbBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
683getThumbBRTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
690 return (MO.
getImm() >> 1);
695getThumbBCCTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
702 return (MO.
getImm() >> 1);
707getThumbCBTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
713 return (MO.
getImm() >> 1);
718 int NumOp =
MI.getNumOperands();
720 for (
int i = 0; i < NumOp-1; ++i) {
736getBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
744 return getARMBranchTargetOpValue(
MI, OpIdx, Fixups, STI);
750getARMBranchTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
756 return ::getBranchTargetOpValue(
MI, OpIdx,
758 return ::getBranchTargetOpValue(
MI, OpIdx,
766getARMBLTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
772 return ::getBranchTargetOpValue(
MI, OpIdx,
781getARMBLXTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
793uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
804 bool I = (Val & 0x800000);
805 bool J1 = (Val & 0x400000);
806 bool J2 = (Val & 0x200000);
823getAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
830 int64_t offset = MO.
getImm();
834 if (offset == INT32_MIN) {
837 }
else if (offset < 0) {
855 assert(SoImmVal != -1 &&
"Not a valid so_imm value!");
864getT2AdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
871 int32_t Val = MO.
getImm();
872 if (Val == INT32_MIN)
884getITMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
888 assert(MaskMO.
isImm() &&
"Unexpected operand type!");
896 assert(OpIdx > 0 &&
"IT mask appears first!");
898 assert(CondMO.
isImm() &&
"Unexpected operand type!");
899 if (CondMO.
getImm() & 1) {
901 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
902 Mask ^= BitsAboveLowBit;
911getThumbAdrLabelOpValue(
const MCInst &
MI,
unsigned OpIdx,
924getThumbAddrModeRegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
934 return (Rm << 3) | Rn;
940ARMMCCodeEmitter::getMVEShiftImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
951 unsigned Size, ShiftImm;
952 switch(
MI.getOpcode()) {
953 case ARM::MVE_VSHLL_imms16bh:
954 case ARM::MVE_VSHLL_imms16th:
955 case ARM::MVE_VSHLL_immu16bh:
956 case ARM::MVE_VSHLL_immu16th:
959 case ARM::MVE_VSHLL_imms8bh:
960 case ARM::MVE_VSHLL_imms8th:
961 case ARM::MVE_VSHLL_immu8bh:
962 case ARM::MVE_VSHLL_immu8th:
968 ShiftImm =
MI.getOperand(OpIdx).getImm();
969 return Size + ShiftImm;
974getAddrModeImm12OpValue(
const MCInst &
MI,
unsigned OpIdx,
980 unsigned Reg = 0, Imm12 = 0;
987 isAdd = EncodeAddrModeOpValues(
MI, OpIdx, Reg, Imm12, Fixups, STI);
988 }
else if (MO1.
isExpr()) {
990 "Thumb mode requires different encoding");
1006 ++MCNumCPRelocations;
1010 if (
Offset == INT32_MIN) {
1027template<
unsigned Bits,
unsigned Shift>
1029getT2ScaledImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1041 int32_t
Imm =
MI.getOperand(OpIdx).getImm();
1042 bool isAdd =
Imm >= 0;
1060getMveAddrModeRQOpValue(
const MCInst &
MI,
unsigned OpIdx,
1071 assert(Qm < 8 &&
"Qm is supposed to be encodable in 3 bits");
1073 return (Rn << 3) | Qm;
1080getMveAddrModeQOpValue(
const MCInst &
MI,
unsigned OpIdx,
1089 int32_t
Imm =
M1.getImm();
1091 bool isAdd =
Imm >= 0;
1103 assert(Qm < 8 &&
"Qm is supposed to be encodable in 3 bits");
1105 return (Qm << 8) |
Imm;
1111getT2AddrModeImm8s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1126 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1131 ++MCNumCPRelocations;
1133 isAdd = EncodeAddrModeOpValues(
MI, OpIdx, Reg, Imm8, Fixups, STI);
1141 assert(((Imm8 & 0x3) == 0) &&
"Not a valid immediate!");
1153ARMMCCodeEmitter::getT2AddrModeImm7s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1161 bool isAdd = EncodeAddrModeOpValues(
MI, OpIdx, Reg, Imm7, Fixups, STI);
1180getT2AddrModeImm0_1020s4OpValue(
const MCInst &
MI,
unsigned OpIdx,
1189 return (Reg << 8) |
Imm8;
1193ARMMCCodeEmitter::getHiLo16ImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1201 return static_cast<unsigned>(MO.
getImm());
1207 const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(
E);
1211 const int64_t
Value = MCE->getValue();
1212 if (
Value > UINT32_MAX)
1215 switch (ARM16Expr->
getKind()) {
1217 return (int32_t(
Value) & 0xffff0000) >> 16;
1219 return (int32_t(
Value) & 0x0000ffff);
1224 switch (ARM16Expr->
getKind()) {
1249getLdStSORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1260 unsigned SBits = getShiftOp(ShOp);
1264 assert((ShImm & ~0x1f) == 0 &&
"Out of range shift amount");
1283getAddrMode2OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1299 Binary |= getShiftOp(ShOp) << 5;
1306getPostIdxRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1313 bool isAdd = MO1.
getImm() != 0;
1318getAddrMode3OffsetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1334 return Imm8 | (isAdd << 8) | (
isImm << 9);
1338getAddrMode3OpValue(
const MCInst &
MI,
unsigned OpIdx,
1354 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1359 ++MCNumCPRelocations;
1360 return (Rn << 9) | (1 << 13);
1370 return (Rn << 9) |
Imm8 | (isAdd << 8) | (
isImm << 13);
1375getAddrModeThumbSPOpValue(
const MCInst &
MI,
unsigned OpIdx,
1381 assert(
MI.getOperand(OpIdx).getReg() == ARM::SP &&
1382 "Unexpected base register!");
1386 return MO1.
getImm() & 0xff;
1391getAddrModeISOpValue(
const MCInst &
MI,
unsigned OpIdx,
1400 unsigned Imm5 = MO1.
getImm();
1401 return ((Imm5 & 0x1f) << 3) | Rn;
1406getAddrModePCOpValue(
const MCInst &
MI,
unsigned OpIdx,
1412 return (MO.
getImm() >> 2);
1417getAddrMode5OpValue(
const MCInst &
MI,
unsigned OpIdx,
1432 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1441 ++MCNumCPRelocations;
1443 EncodeAddrModeOpValues(
MI, OpIdx, Reg, Imm8, Fixups, STI);
1457getAddrMode5FP16OpValue(
const MCInst &
MI,
unsigned OpIdx,
1472 assert(MO.
isExpr() &&
"Unexpected machine operand type!");
1481 ++MCNumCPRelocations;
1483 EncodeAddrModeOpValues(
MI, OpIdx, Reg, Imm8, Fixups, STI);
1495unsigned ARMMCCodeEmitter::
1496getSORegRegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1519 unsigned Rs = MO1.
getReg();
1543unsigned ARMMCCodeEmitter::
1544getSORegImmOpValue(
const MCInst &
MI,
unsigned OpIdx,
1585 assert(
Offset < 32 &&
"Offset must be in range 0-31!");
1590unsigned ARMMCCodeEmitter::
1591getT2AddrModeSORegOpValue(
const MCInst &
MI,
unsigned OpNum,
1609template<
unsigned Bits,
unsigned Shift>
1610unsigned ARMMCCodeEmitter::
1611getT2AddrModeImmOpValue(
const MCInst &
MI,
unsigned OpNum,
1623 int32_t tmp = (int32_t)MO2.
getImm();
1624 if (tmp == INT32_MIN) {
1626 }
else if (tmp < 0) {
1631 Value |= (tmp >> Shift) & ((1U << Bits) - 1);
1635unsigned ARMMCCodeEmitter::
1636getT2AddrModeImm8OffsetOpValue(
const MCInst &
MI,
unsigned OpNum,
1643 int32_t tmp = (int32_t)MO1.
getImm();
1652unsigned ARMMCCodeEmitter::
1653getT2SORegOpValue(
const MCInst &
MI,
unsigned OpIdx,
1695unsigned ARMMCCodeEmitter::
1696getBitfieldInvertedMaskOpValue(
const MCInst &
MI,
unsigned Op,
1705 assert(v != 0 && lsb < 32 && msb < 32 &&
"Illegal bitfield mask!");
1706 return lsb | (msb << 5);
1709unsigned ARMMCCodeEmitter::
1710getRegisterListOpValue(
const MCInst &
MI,
unsigned Op,
1719 unsigned Reg =
MI.getOperand(Op).getReg();
1720 bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1721 bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1725 if (SPRRegs || DPRRegs) {
1728 unsigned NumRegs = (
MI.getNumOperands() -
Op) & 0xff;
1729 Binary |= (RegNo & 0x1f) << 8;
1732 if (
MI.getOpcode() == ARM::VSCCLRMD ||
MI.getOpcode() == ARM::VSCCLRMS)
1742 return MRI.getEncodingValue(
LHS.getReg()) <
1743 MRI.getEncodingValue(
RHS.getReg());
1745 for (
unsigned I = Op,
E =
MI.getNumOperands();
I <
E; ++
I) {
1746 unsigned RegNo =
MRI.getEncodingValue(
MI.getOperand(
I).getReg());
1756unsigned ARMMCCodeEmitter::
1757getAddrMode6AddressOpValue(
const MCInst &
MI,
unsigned Op,
1766 switch (
Imm.getImm()) {
1770 case 8:
Align = 0x01;
break;
1771 case 16:
Align = 0x02;
break;
1772 case 32:
Align = 0x03;
break;
1775 return RegNo | (
Align << 4);
1780unsigned ARMMCCodeEmitter::
1781getAddrMode6OneLane32AddressOpValue(
const MCInst &
MI,
unsigned Op,
1790 switch (
Imm.getImm()) {
1795 case 2:
Align = 0x00;
break;
1796 case 4:
Align = 0x03;
break;
1799 return RegNo | (
Align << 4);
1807unsigned ARMMCCodeEmitter::
1808getAddrMode6DupAddressOpValue(
const MCInst &
MI,
unsigned Op,
1817 switch (
Imm.getImm()) {
1821 case 8:
Align = 0x01;
break;
1822 case 16:
Align = 0x03;
break;
1825 return RegNo | (
Align << 4);
1828unsigned ARMMCCodeEmitter::
1829getAddrMode6OffsetOpValue(
const MCInst &
MI,
unsigned Op,
1833 if (MO.
getReg() == 0)
return 0x0D;
1837unsigned ARMMCCodeEmitter::
1838getShiftRight8Imm(
const MCInst &
MI,
unsigned Op,
1841 return 8 -
MI.getOperand(Op).getImm();
1844unsigned ARMMCCodeEmitter::
1845getShiftRight16Imm(
const MCInst &
MI,
unsigned Op,
1848 return 16 -
MI.getOperand(Op).getImm();
1851unsigned ARMMCCodeEmitter::
1852getShiftRight32Imm(
const MCInst &
MI,
unsigned Op,
1855 return 32 -
MI.getOperand(Op).getImm();
1858unsigned ARMMCCodeEmitter::
1859getShiftRight64Imm(
const MCInst &
MI,
unsigned Op,
1862 return 64 -
MI.getOperand(Op).getImm();
1865void ARMMCCodeEmitter::
1885 EmitConstant(Binary >> 16, 2,
OS);
1886 EmitConstant(Binary & 0xffff, 2,
OS);
1888 EmitConstant(Binary,
Size,
OS);
1892template <
bool isNeg, ARM::Fixups fixup>
1894ARMMCCodeEmitter::getBFTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1899 return ::getBranchTargetOpValue(
MI, OpIdx, fixup, Fixups, STI);
1900 return isNeg ? -(MO.
getImm() >> 1) : (MO.
getImm() >> 1);
1904ARMMCCodeEmitter::getBFAfterTargetOpValue(
const MCInst &
MI,
unsigned OpIdx,
1921 assert(Diff == 4 || Diff == 2);
1926uint32_t ARMMCCodeEmitter::getVPTMaskOpValue(
const MCInst &
MI,
unsigned OpIdx,
1937 unsigned PrevBit = 0;
1938 for (
int i = 3; i >= 0; --i) {
1942 if ((
Value & ~(~0U << i)) == 0) {
1957uint32_t ARMMCCodeEmitter::getRestrictedCondCodeOpValue(
1966 assert(0 &&
"Unexpected Condition!");
1986getPowerTwoOpValue(
const MCInst &
MI,
unsigned OpIdx,
1994template <
unsigned start>
1996getMVEPairVectorIndexOpValue(
const MCInst &
MI,
unsigned OpIdx,
2003 return Value - start;
2006#include "ARMGenMCCodeEmitter.inc"
2010 return new ARMMCCodeEmitter(MCII, Ctx,
true);
2015 return new ARMMCCodeEmitter(MCII, Ctx,
false);
unsigned const MachineRegisterInfo * MRI
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isThumb(const MCSubtargetInfo &STI)
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
static int32_t encodeThumbBLOffset(int32_t offset)
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool isReg(const MCInst &MI, unsigned OpNo)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
APInt bitcastToAPInt() const
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
VariantKind getKind() const
getOpcode - Get the kind of this expression.
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
MCCodeEmitter - Generic instruction encoding interface.
virtual void encodeInstruction(const MCInst &Inst, raw_ostream &OS, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI) const =0
EncodeInstruction - Encode the given Inst to bytes on the output stream OS.
MCCodeEmitter & operator=(const MCCodeEmitter &)=delete
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
@ Target
Target specific expression.
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
unsigned getReg() const
Returns the register number.
const MCExpr * getExpr() const
uint64_t getDFPImm() const
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Triple - Helper class for working with autoconf configuration names.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned char getAM3Offset(unsigned AM3Opc)
unsigned getSORegOffset(unsigned Op)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
unsigned getAM2Offset(unsigned AM2Opc)
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
ShiftOpc getSORegShOp(unsigned Op)
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM2Op(unsigned AM2Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
@ fixup_thumb_adr_pcrel_10
@ fixup_arm_pcrel_10_unscaled
@ fixup_bfcsel_else_target
@ fixup_arm_ldst_pcrel_12
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
unsigned M1(unsigned Val)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
unsigned M0(unsigned Val)
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
This struct is a compact representation of a valid (non-zero power of two) alignment.