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ARMMCCodeEmitter.cpp
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1 //===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the ARMMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCFixup.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/Support/Casting.h"
32 #include "llvm/Support/Compiler.h"
36 #include <algorithm>
37 #include <cassert>
38 #include <cstdint>
39 #include <cstdlib>
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mccodeemitter"
44 
45 STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
46 STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
47 
48 namespace {
49 
50 class ARMMCCodeEmitter : public MCCodeEmitter {
51  const MCInstrInfo &MCII;
52  const MCContext &CTX;
53  bool IsLittleEndian;
54 
55 public:
56  ARMMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx, bool IsLittle)
57  : MCII(mcii), CTX(ctx), IsLittleEndian(IsLittle) {
58  }
59  ARMMCCodeEmitter(const ARMMCCodeEmitter &) = delete;
60  ARMMCCodeEmitter &operator=(const ARMMCCodeEmitter &) = delete;
61  ~ARMMCCodeEmitter() override = default;
62 
63  bool isThumb(const MCSubtargetInfo &STI) const {
64  return STI.getFeatureBits()[ARM::ModeThumb];
65  }
66 
67  bool isThumb2(const MCSubtargetInfo &STI) const {
68  return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
69  }
70 
71  bool isTargetMachO(const MCSubtargetInfo &STI) const {
72  const Triple &TT = STI.getTargetTriple();
73  return TT.isOSBinFormatMachO();
74  }
75 
76  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
77 
78  // getBinaryCodeForInstr - TableGen'erated function for getting the
79  // binary encoding for an instruction.
80  uint64_t getBinaryCodeForInstr(const MCInst &MI,
82  const MCSubtargetInfo &STI) const;
83 
84  /// getMachineOpValue - Return binary encoding of operand. If the machine
85  /// operand requires relocation, record the relocation and return zero.
86  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
88  const MCSubtargetInfo &STI) const;
89 
90  /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of
91  /// the specified operand. This is used for operands with :lower16: and
92  /// :upper16: prefixes.
93  uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
95  const MCSubtargetInfo &STI) const;
96 
97  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
98  unsigned &Reg, unsigned &Imm,
100  const MCSubtargetInfo &STI) const;
101 
102  /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate
103  /// BL branch target.
104  uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
106  const MCSubtargetInfo &STI) const;
107 
108  /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
109  /// BLX branch target.
110  uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
112  const MCSubtargetInfo &STI) const;
113 
114  /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
115  uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
117  const MCSubtargetInfo &STI) const;
118 
119  /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
120  uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
122  const MCSubtargetInfo &STI) const;
123 
124  /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
125  uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
127  const MCSubtargetInfo &STI) const;
128 
129  /// getBranchTargetOpValue - Return encoding info for 24-bit immediate
130  /// branch target.
131  uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
133  const MCSubtargetInfo &STI) const;
134 
135  /// getThumbBranchTargetOpValue - Return encoding info for 24-bit
136  /// immediate Thumb2 direct branch target.
137  uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
139  const MCSubtargetInfo &STI) const;
140 
141  /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate
142  /// branch target.
143  uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
145  const MCSubtargetInfo &STI) const;
146  uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
148  const MCSubtargetInfo &STI) const;
149  uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
151  const MCSubtargetInfo &STI) const;
152 
153  /// getAdrLabelOpValue - Return encoding info for 12-bit immediate
154  /// ADR label target.
155  uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
157  const MCSubtargetInfo &STI) const;
158  uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
160  const MCSubtargetInfo &STI) const;
161  uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
163  const MCSubtargetInfo &STI) const;
164 
165 
166  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
167  /// operand.
168  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
170  const MCSubtargetInfo &STI) const;
171 
172  /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand.
173  uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
175  const MCSubtargetInfo &STI) const;
176 
177  /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
178  /// operand.
179  uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
181  const MCSubtargetInfo &STI) const;
182 
183  /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
184  /// operand.
185  uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
187  const MCSubtargetInfo &STI) const;
188 
189  /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
190  /// operand.
191  uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
193  const MCSubtargetInfo &STI) const;
194 
195 
196  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
197  /// operand as needed by load/store instructions.
198  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
200  const MCSubtargetInfo &STI) const;
201 
202  /// getLdStmModeOpValue - Return encoding for load/store multiple mode.
203  uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx,
205  const MCSubtargetInfo &STI) const {
207  switch (Mode) {
208  default: llvm_unreachable("Unknown addressing sub-mode!");
209  case ARM_AM::da: return 0;
210  case ARM_AM::ia: return 1;
211  case ARM_AM::db: return 2;
212  case ARM_AM::ib: return 3;
213  }
214  }
215 
216  /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
217  ///
218  unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
219  switch (ShOpc) {
220  case ARM_AM::no_shift:
221  case ARM_AM::lsl: return 0;
222  case ARM_AM::lsr: return 1;
223  case ARM_AM::asr: return 2;
224  case ARM_AM::ror:
225  case ARM_AM::rrx: return 3;
226  }
227  llvm_unreachable("Invalid ShiftOpc!");
228  }
229 
230  /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
231  uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
232  SmallVectorImpl<MCFixup> &Fixups,
233  const MCSubtargetInfo &STI) const;
234 
235  /// getPostIdxRegOpValue - Return encoding for postidx_reg operands.
236  uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
237  SmallVectorImpl<MCFixup> &Fixups,
238  const MCSubtargetInfo &STI) const;
239 
240  /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
241  uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
242  SmallVectorImpl<MCFixup> &Fixups,
243  const MCSubtargetInfo &STI) const;
244 
245  /// getAddrMode3OpValue - Return encoding for addrmode3 operands.
246  uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
247  SmallVectorImpl<MCFixup> &Fixups,
248  const MCSubtargetInfo &STI) const;
249 
250  /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12'
251  /// operand.
252  uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
253  SmallVectorImpl<MCFixup> &Fixups,
254  const MCSubtargetInfo &STI) const;
255 
256  /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
257  uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
258  SmallVectorImpl<MCFixup> &Fixups,
259  const MCSubtargetInfo &STI) const;
260 
261  /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
262  uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
263  SmallVectorImpl<MCFixup> &Fixups,
264  const MCSubtargetInfo &STI) const;
265 
266  /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
267  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
268  SmallVectorImpl<MCFixup> &Fixups,
269  const MCSubtargetInfo &STI) const;
270 
271  /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
272  uint32_t getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
273  SmallVectorImpl<MCFixup> &Fixups,
274  const MCSubtargetInfo &STI) const;
275 
276  /// getCCOutOpValue - Return encoding of the 's' bit.
277  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
278  SmallVectorImpl<MCFixup> &Fixups,
279  const MCSubtargetInfo &STI) const {
280  // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
281  // '1' respectively.
282  return MI.getOperand(Op).getReg() == ARM::CPSR;
283  }
284 
285  unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
286  SmallVectorImpl<MCFixup> &Fixups,
287  const MCSubtargetInfo &ST) const {
288  const MCOperand &MO = MI.getOperand(Op);
289 
290  // Support for fixups (MCFixup)
291  if (MO.isExpr()) {
292  const MCExpr *Expr = MO.getExpr();
293  // Fixups resolve to plain values that need to be encoded.
295  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
296  return 0;
297  }
298 
299  // Immediate is already in its encoded format
300  return MO.getImm();
301  }
302 
303  /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
304  unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op,
305  SmallVectorImpl<MCFixup> &Fixups,
306  const MCSubtargetInfo &STI) const {
307  const MCOperand &MO = MI.getOperand(Op);
308 
309  // Support for fixups (MCFixup)
310  if (MO.isExpr()) {
311  const MCExpr *Expr = MO.getExpr();
312  // Fixups resolve to plain values that need to be encoded.
314  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
315  return 0;
316  }
317  unsigned SoImm = MO.getImm();
318  unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
319  assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
320  return Encoded;
321  }
322 
323  unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
324  SmallVectorImpl<MCFixup> &Fixups,
325  const MCSubtargetInfo &STI) const;
326  unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
327  SmallVectorImpl<MCFixup> &Fixups,
328  const MCSubtargetInfo &STI) const;
329  unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
330  SmallVectorImpl<MCFixup> &Fixups,
331  const MCSubtargetInfo &STI) const;
332 
333  /// getSORegOpValue - Return an encoded so_reg shifted register value.
334  unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op,
335  SmallVectorImpl<MCFixup> &Fixups,
336  const MCSubtargetInfo &STI) const;
337  unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op,
338  SmallVectorImpl<MCFixup> &Fixups,
339  const MCSubtargetInfo &STI) const;
340  unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
341  SmallVectorImpl<MCFixup> &Fixups,
342  const MCSubtargetInfo &STI) const;
343 
344  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
345  SmallVectorImpl<MCFixup> &Fixups,
346  const MCSubtargetInfo &STI) const {
347  return 64 - MI.getOperand(Op).getImm();
348  }
349 
350  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
351  SmallVectorImpl<MCFixup> &Fixups,
352  const MCSubtargetInfo &STI) const;
353 
354  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
355  SmallVectorImpl<MCFixup> &Fixups,
356  const MCSubtargetInfo &STI) const;
357  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
358  SmallVectorImpl<MCFixup> &Fixups,
359  const MCSubtargetInfo &STI) const;
360  unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
361  SmallVectorImpl<MCFixup> &Fixups,
362  const MCSubtargetInfo &STI) const;
363  unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
364  SmallVectorImpl<MCFixup> &Fixups,
365  const MCSubtargetInfo &STI) const;
366  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
367  SmallVectorImpl<MCFixup> &Fixups,
368  const MCSubtargetInfo &STI) const;
369 
370  unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
371  SmallVectorImpl<MCFixup> &Fixups,
372  const MCSubtargetInfo &STI) const;
373  unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
374  SmallVectorImpl<MCFixup> &Fixups,
375  const MCSubtargetInfo &STI) const;
376  unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
377  SmallVectorImpl<MCFixup> &Fixups,
378  const MCSubtargetInfo &STI) const;
379  unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
380  SmallVectorImpl<MCFixup> &Fixups,
381  const MCSubtargetInfo &STI) const;
382 
383  unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
384  SmallVectorImpl<MCFixup> &Fixups,
385  const MCSubtargetInfo &STI) const;
386 
387  unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
388  unsigned EncodedValue,
389  const MCSubtargetInfo &STI) const;
390  unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
391  unsigned EncodedValue,
392  const MCSubtargetInfo &STI) const;
393  unsigned NEONThumb2DupPostEncoder(const MCInst &MI,
394  unsigned EncodedValue,
395  const MCSubtargetInfo &STI) const;
396  unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
397  unsigned EncodedValue,
398  const MCSubtargetInfo &STI) const;
399 
400  unsigned VFPThumb2PostEncoder(const MCInst &MI,
401  unsigned EncodedValue,
402  const MCSubtargetInfo &STI) const;
403 
404  void EmitByte(unsigned char C, raw_ostream &OS) const {
405  OS << (char)C;
406  }
407 
408  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
409  // Output the constant in little endian byte order.
410  for (unsigned i = 0; i != Size; ++i) {
411  unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
412  EmitByte((Val >> Shift) & 0xff, OS);
413  }
414  }
415 
416  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
417  SmallVectorImpl<MCFixup> &Fixups,
418  const MCSubtargetInfo &STI) const override;
419 };
420 
421 } // end anonymous namespace
422 
423 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
424 /// instructions, and rewrite them to their Thumb2 form if we are currently in
425 /// Thumb2 mode.
426 unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI,
427  unsigned EncodedValue,
428  const MCSubtargetInfo &STI) const {
429  if (isThumb2(STI)) {
430  // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved
431  // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are
432  // set to 1111.
433  unsigned Bit24 = EncodedValue & 0x01000000;
434  unsigned Bit28 = Bit24 << 4;
435  EncodedValue &= 0xEFFFFFFF;
436  EncodedValue |= Bit28;
437  EncodedValue |= 0x0F000000;
438  }
439 
440  return EncodedValue;
441 }
442 
443 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
444 /// instructions, and rewrite them to their Thumb2 form if we are currently in
445 /// Thumb2 mode.
446 unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI,
447  unsigned EncodedValue,
448  const MCSubtargetInfo &STI) const {
449  if (isThumb2(STI)) {
450  EncodedValue &= 0xF0FFFFFF;
451  EncodedValue |= 0x09000000;
452  }
453 
454  return EncodedValue;
455 }
456 
457 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
458 /// instructions, and rewrite them to their Thumb2 form if we are currently in
459 /// Thumb2 mode.
460 unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI,
461  unsigned EncodedValue,
462  const MCSubtargetInfo &STI) const {
463  if (isThumb2(STI)) {
464  EncodedValue &= 0x00FFFFFF;
465  EncodedValue |= 0xEE000000;
466  }
467 
468  return EncodedValue;
469 }
470 
471 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
472 /// if we are in Thumb2.
473 unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI,
474  unsigned EncodedValue,
475  const MCSubtargetInfo &STI) const {
476  if (isThumb2(STI)) {
477  EncodedValue |= 0xC000000; // Set bits 27-26
478  }
479 
480  return EncodedValue;
481 }
482 
483 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
484 /// them to their Thumb2 form if we are currently in Thumb2 mode.
485 unsigned ARMMCCodeEmitter::
486 VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue,
487  const MCSubtargetInfo &STI) const {
488  if (isThumb2(STI)) {
489  EncodedValue &= 0x0FFFFFFF;
490  EncodedValue |= 0xE0000000;
491  }
492  return EncodedValue;
493 }
494 
495 /// getMachineOpValue - Return binary encoding of operand. If the machine
496 /// operand requires relocation, record the relocation and return zero.
497 unsigned ARMMCCodeEmitter::
498 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
499  SmallVectorImpl<MCFixup> &Fixups,
500  const MCSubtargetInfo &STI) const {
501  if (MO.isReg()) {
502  unsigned Reg = MO.getReg();
503  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
504 
505  // Q registers are encoded as 2x their register number.
506  switch (Reg) {
507  default:
508  return RegNo;
509  case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3:
510  case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7:
511  case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11:
512  case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
513  return 2 * RegNo;
514  }
515  } else if (MO.isImm()) {
516  return static_cast<unsigned>(MO.getImm());
517  } else if (MO.isFPImm()) {
518  return static_cast<unsigned>(APFloat(MO.getFPImm())
519  .bitcastToAPInt().getHiBits(32).getLimitedValue());
520  }
521 
522  llvm_unreachable("Unable to encode MCOperand!");
523 }
524 
525 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
526 bool ARMMCCodeEmitter::
527 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
528  unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups,
529  const MCSubtargetInfo &STI) const {
530  const MCOperand &MO = MI.getOperand(OpIdx);
531  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
532 
533  Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
534 
535  int32_t SImm = MO1.getImm();
536  bool isAdd = true;
537 
538  // Special value for #-0
539  if (SImm == INT32_MIN) {
540  SImm = 0;
541  isAdd = false;
542  }
543 
544  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
545  if (SImm < 0) {
546  SImm = -SImm;
547  isAdd = false;
548  }
549 
550  Imm = SImm;
551  return isAdd;
552 }
553 
554 /// getBranchTargetOpValue - Helper function to get the branch target operand,
555 /// which is either an immediate or requires a fixup.
556 static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
557  unsigned FixupKind,
558  SmallVectorImpl<MCFixup> &Fixups,
559  const MCSubtargetInfo &STI) {
560  const MCOperand &MO = MI.getOperand(OpIdx);
561 
562  // If the destination is an immediate, we have nothing to do.
563  if (MO.isImm()) return MO.getImm();
564  assert(MO.isExpr() && "Unexpected branch target type!");
565  const MCExpr *Expr = MO.getExpr();
566  MCFixupKind Kind = MCFixupKind(FixupKind);
567  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
568 
569  // All of the information is in the fixup.
570  return 0;
571 }
572 
573 // Thumb BL and BLX use a strange offset encoding where bits 22 and 21 are
574 // determined by negating them and XOR'ing them with bit 23.
575 static int32_t encodeThumbBLOffset(int32_t offset) {
576  offset >>= 1;
577  uint32_t S = (offset & 0x800000) >> 23;
578  uint32_t J1 = (offset & 0x400000) >> 22;
579  uint32_t J2 = (offset & 0x200000) >> 21;
580  J1 = (~J1 & 0x1);
581  J2 = (~J2 & 0x1);
582  J1 ^= S;
583  J2 ^= S;
584 
585  offset &= ~0x600000;
586  offset |= J1 << 22;
587  offset |= J2 << 21;
588 
589  return offset;
590 }
591 
592 /// getThumbBLTargetOpValue - Return encoding info for immediate branch target.
593 uint32_t ARMMCCodeEmitter::
594 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
595  SmallVectorImpl<MCFixup> &Fixups,
596  const MCSubtargetInfo &STI) const {
597  const MCOperand MO = MI.getOperand(OpIdx);
598  if (MO.isExpr())
600  Fixups, STI);
601  return encodeThumbBLOffset(MO.getImm());
602 }
603 
604 /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate
605 /// BLX branch target.
606 uint32_t ARMMCCodeEmitter::
607 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
608  SmallVectorImpl<MCFixup> &Fixups,
609  const MCSubtargetInfo &STI) const {
610  const MCOperand MO = MI.getOperand(OpIdx);
611  if (MO.isExpr())
613  Fixups, STI);
614  return encodeThumbBLOffset(MO.getImm());
615 }
616 
617 /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target.
618 uint32_t ARMMCCodeEmitter::
619 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
620  SmallVectorImpl<MCFixup> &Fixups,
621  const MCSubtargetInfo &STI) const {
622  const MCOperand MO = MI.getOperand(OpIdx);
623  if (MO.isExpr())
625  Fixups, STI);
626  return (MO.getImm() >> 1);
627 }
628 
629 /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target.
630 uint32_t ARMMCCodeEmitter::
631 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
632  SmallVectorImpl<MCFixup> &Fixups,
633  const MCSubtargetInfo &STI) const {
634  const MCOperand MO = MI.getOperand(OpIdx);
635  if (MO.isExpr())
637  Fixups, STI);
638  return (MO.getImm() >> 1);
639 }
640 
641 /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target.
642 uint32_t ARMMCCodeEmitter::
643 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
644  SmallVectorImpl<MCFixup> &Fixups,
645  const MCSubtargetInfo &STI) const {
646  const MCOperand MO = MI.getOperand(OpIdx);
647  if (MO.isExpr())
649  return (MO.getImm() >> 1);
650 }
651 
652 /// Return true if this branch has a non-always predication
653 static bool HasConditionalBranch(const MCInst &MI) {
654  int NumOp = MI.getNumOperands();
655  if (NumOp >= 2) {
656  for (int i = 0; i < NumOp-1; ++i) {
657  const MCOperand &MCOp1 = MI.getOperand(i);
658  const MCOperand &MCOp2 = MI.getOperand(i + 1);
659  if (MCOp1.isImm() && MCOp2.isReg() &&
660  (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
661  if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
662  return true;
663  }
664  }
665  }
666  return false;
667 }
668 
669 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
670 /// target.
672 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
673  SmallVectorImpl<MCFixup> &Fixups,
674  const MCSubtargetInfo &STI) const {
675  // FIXME: This really, really shouldn't use TargetMachine. We don't want
676  // coupling between MC and TM anywhere we can help it.
677  if (isThumb2(STI))
678  return
679  ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI);
680  return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI);
681 }
682 
683 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
684 /// target.
685 uint32_t ARMMCCodeEmitter::
686 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
687  SmallVectorImpl<MCFixup> &Fixups,
688  const MCSubtargetInfo &STI) const {
689  const MCOperand MO = MI.getOperand(OpIdx);
690  if (MO.isExpr()) {
691  if (HasConditionalBranch(MI))
693  ARM::fixup_arm_condbranch, Fixups, STI);
695  ARM::fixup_arm_uncondbranch, Fixups, STI);
696  }
697 
698  return MO.getImm() >> 2;
699 }
700 
701 uint32_t ARMMCCodeEmitter::
702 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
703  SmallVectorImpl<MCFixup> &Fixups,
704  const MCSubtargetInfo &STI) const {
705  const MCOperand MO = MI.getOperand(OpIdx);
706  if (MO.isExpr()) {
707  if (HasConditionalBranch(MI))
709  ARM::fixup_arm_condbl, Fixups, STI);
711  }
712 
713  return MO.getImm() >> 2;
714 }
715 
716 uint32_t ARMMCCodeEmitter::
717 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
718  SmallVectorImpl<MCFixup> &Fixups,
719  const MCSubtargetInfo &STI) const {
720  const MCOperand MO = MI.getOperand(OpIdx);
721  if (MO.isExpr())
722  return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI);
723 
724  return MO.getImm() >> 1;
725 }
726 
727 /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit
728 /// immediate branch target.
729 uint32_t ARMMCCodeEmitter::getThumbBranchTargetOpValue(
730  const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
731  const MCSubtargetInfo &STI) const {
732  unsigned Val = 0;
733  const MCOperand MO = MI.getOperand(OpIdx);
734 
735  if(MO.isExpr())
737  else
738  Val = MO.getImm() >> 1;
739 
740  bool I = (Val & 0x800000);
741  bool J1 = (Val & 0x400000);
742  bool J2 = (Val & 0x200000);
743  if (I ^ J1)
744  Val &= ~0x400000;
745  else
746  Val |= 0x400000;
747 
748  if (I ^ J2)
749  Val &= ~0x200000;
750  else
751  Val |= 0x200000;
752 
753  return Val;
754 }
755 
756 /// getAdrLabelOpValue - Return encoding info for 12-bit shifted-immediate
757 /// ADR label target.
758 uint32_t ARMMCCodeEmitter::
759 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
760  SmallVectorImpl<MCFixup> &Fixups,
761  const MCSubtargetInfo &STI) const {
762  const MCOperand MO = MI.getOperand(OpIdx);
763  if (MO.isExpr())
765  Fixups, STI);
766  int64_t offset = MO.getImm();
767  uint32_t Val = 0x2000;
768 
769  int SoImmVal;
770  if (offset == INT32_MIN) {
771  Val = 0x1000;
772  SoImmVal = 0;
773  } else if (offset < 0) {
774  Val = 0x1000;
775  offset *= -1;
776  SoImmVal = ARM_AM::getSOImmVal(offset);
777  if(SoImmVal == -1) {
778  Val = 0x2000;
779  offset *= -1;
780  SoImmVal = ARM_AM::getSOImmVal(offset);
781  }
782  } else {
783  SoImmVal = ARM_AM::getSOImmVal(offset);
784  if(SoImmVal == -1) {
785  Val = 0x1000;
786  offset *= -1;
787  SoImmVal = ARM_AM::getSOImmVal(offset);
788  }
789  }
790 
791  assert(SoImmVal != -1 && "Not a valid so_imm value!");
792 
793  Val |= SoImmVal;
794  return Val;
795 }
796 
797 /// getT2AdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
798 /// target.
799 uint32_t ARMMCCodeEmitter::
800 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
801  SmallVectorImpl<MCFixup> &Fixups,
802  const MCSubtargetInfo &STI) const {
803  const MCOperand MO = MI.getOperand(OpIdx);
804  if (MO.isExpr())
806  Fixups, STI);
807  int32_t Val = MO.getImm();
808  if (Val == INT32_MIN)
809  Val = 0x1000;
810  else if (Val < 0) {
811  Val *= -1;
812  Val |= 0x1000;
813  }
814  return Val;
815 }
816 
817 /// getThumbAdrLabelOpValue - Return encoding info for 8-bit immediate ADR label
818 /// target.
819 uint32_t ARMMCCodeEmitter::
820 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
821  SmallVectorImpl<MCFixup> &Fixups,
822  const MCSubtargetInfo &STI) const {
823  const MCOperand MO = MI.getOperand(OpIdx);
824  if (MO.isExpr())
826  Fixups, STI);
827  return MO.getImm();
828 }
829 
830 /// getThumbAddrModeRegRegOpValue - Return encoding info for 'reg + reg'
831 /// operand.
832 uint32_t ARMMCCodeEmitter::
833 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
835  const MCSubtargetInfo &STI) const {
836  // [Rn, Rm]
837  // {5-3} = Rm
838  // {2-0} = Rn
839  const MCOperand &MO1 = MI.getOperand(OpIdx);
840  const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
841  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
842  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
843  return (Rm << 3) | Rn;
844 }
845 
846 /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
847 uint32_t ARMMCCodeEmitter::
848 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
849  SmallVectorImpl<MCFixup> &Fixups,
850  const MCSubtargetInfo &STI) const {
851  // {17-13} = reg
852  // {12} = (U)nsigned (add == '1', sub == '0')
853  // {11-0} = imm12
854  unsigned Reg, Imm12;
855  bool isAdd = true;
856  // If The first operand isn't a register, we have a label reference.
857  const MCOperand &MO = MI.getOperand(OpIdx);
858  if (!MO.isReg()) {
859  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
860  Imm12 = 0;
861 
862  if (MO.isExpr()) {
863  const MCExpr *Expr = MO.getExpr();
864  isAdd = false ; // 'U' bit is set as part of the fixup.
865 
867  if (isThumb2(STI))
869  else
871  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
872 
873  ++MCNumCPRelocations;
874  } else {
875  Reg = ARM::PC;
876  int32_t Offset = MO.getImm();
877  if (Offset == INT32_MIN) {
878  Offset = 0;
879  isAdd = false;
880  } else if (Offset < 0) {
881  Offset *= -1;
882  isAdd = false;
883  }
884  Imm12 = Offset;
885  }
886  } else
887  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
888 
889  uint32_t Binary = Imm12 & 0xfff;
890  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
891  if (isAdd)
892  Binary |= (1 << 12);
893  Binary |= (Reg << 13);
894  return Binary;
895 }
896 
897 /// getT2Imm8s4OpValue - Return encoding info for
898 /// '+/- imm8<<2' operand.
899 uint32_t ARMMCCodeEmitter::
900 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx,
901  SmallVectorImpl<MCFixup> &Fixups,
902  const MCSubtargetInfo &STI) const {
903  // FIXME: The immediate operand should have already been encoded like this
904  // before ever getting here. The encoder method should just need to combine
905  // the MI operands for the register and the offset into a single
906  // representation for the complex operand in the .td file. This isn't just
907  // style, unfortunately. As-is, we can't represent the distinct encoding
908  // for #-0.
909 
910  // {8} = (U)nsigned (add == '1', sub == '0')
911  // {7-0} = imm8
912  int32_t Imm8 = MI.getOperand(OpIdx).getImm();
913  bool isAdd = Imm8 >= 0;
914 
915  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
916  if (Imm8 < 0)
917  Imm8 = -(uint32_t)Imm8;
918 
919  // Scaled by 4.
920  Imm8 /= 4;
921 
922  uint32_t Binary = Imm8 & 0xff;
923  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
924  if (isAdd)
925  Binary |= (1 << 8);
926  return Binary;
927 }
928 
929 /// getT2AddrModeImm8s4OpValue - Return encoding info for
930 /// 'reg +/- imm8<<2' operand.
931 uint32_t ARMMCCodeEmitter::
932 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
933  SmallVectorImpl<MCFixup> &Fixups,
934  const MCSubtargetInfo &STI) const {
935  // {12-9} = reg
936  // {8} = (U)nsigned (add == '1', sub == '0')
937  // {7-0} = imm8
938  unsigned Reg, Imm8;
939  bool isAdd = true;
940  // If The first operand isn't a register, we have a label reference.
941  const MCOperand &MO = MI.getOperand(OpIdx);
942  if (!MO.isReg()) {
943  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
944  Imm8 = 0;
945  isAdd = false ; // 'U' bit is set as part of the fixup.
946 
947  assert(MO.isExpr() && "Unexpected machine operand type!");
948  const MCExpr *Expr = MO.getExpr();
950  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
951 
952  ++MCNumCPRelocations;
953  } else
954  isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
955 
956  // FIXME: The immediate operand should have already been encoded like this
957  // before ever getting here. The encoder method should just need to combine
958  // the MI operands for the register and the offset into a single
959  // representation for the complex operand in the .td file. This isn't just
960  // style, unfortunately. As-is, we can't represent the distinct encoding
961  // for #-0.
962  uint32_t Binary = (Imm8 >> 2) & 0xff;
963  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
964  if (isAdd)
965  Binary |= (1 << 8);
966  Binary |= (Reg << 9);
967  return Binary;
968 }
969 
970 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for
971 /// 'reg + imm8<<2' operand.
972 uint32_t ARMMCCodeEmitter::
973 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx,
974  SmallVectorImpl<MCFixup> &Fixups,
975  const MCSubtargetInfo &STI) const {
976  // {11-8} = reg
977  // {7-0} = imm8
978  const MCOperand &MO = MI.getOperand(OpIdx);
979  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
980  unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
981  unsigned Imm8 = MO1.getImm();
982  return (Reg << 8) | Imm8;
983 }
984 
985 uint32_t
986 ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
987  SmallVectorImpl<MCFixup> &Fixups,
988  const MCSubtargetInfo &STI) const {
989  // {20-16} = imm{15-12}
990  // {11-0} = imm{11-0}
991  const MCOperand &MO = MI.getOperand(OpIdx);
992  if (MO.isImm())
993  // Hi / lo 16 bits already extracted during earlier passes.
994  return static_cast<unsigned>(MO.getImm());
995 
996  // Handle :upper16: and :lower16: assembly prefixes.
997  const MCExpr *E = MO.getExpr();
999  if (E->getKind() == MCExpr::Target) {
1000  const ARMMCExpr *ARM16Expr = cast<ARMMCExpr>(E);
1001  E = ARM16Expr->getSubExpr();
1002 
1003  if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
1004  const int64_t Value = MCE->getValue();
1005  if (Value > UINT32_MAX)
1006  report_fatal_error("constant value truncated (limited to 32-bit)");
1007 
1008  switch (ARM16Expr->getKind()) {
1010  return (int32_t(Value) & 0xffff0000) >> 16;
1012  return (int32_t(Value) & 0x0000ffff);
1013  default: llvm_unreachable("Unsupported ARMFixup");
1014  }
1015  }
1016 
1017  switch (ARM16Expr->getKind()) {
1018  default: llvm_unreachable("Unsupported ARMFixup");
1022  break;
1026  break;
1027  }
1028 
1029  Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
1030  return 0;
1031  }
1032  // If the expression doesn't have :upper16: or :lower16: on it,
1033  // it's just a plain immediate expression, previously those evaluated to
1034  // the lower 16 bits of the expression regardless of whether
1035  // we have a movt or a movw, but that led to misleadingly results.
1036  // This is disallowed in the AsmParser in validateInstruction()
1037  // so this should never happen.
1038  llvm_unreachable("expression without :upper16: or :lower16:");
1039 }
1040 
1041 uint32_t ARMMCCodeEmitter::
1042 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
1043  SmallVectorImpl<MCFixup> &Fixups,
1044  const MCSubtargetInfo &STI) const {
1045  const MCOperand &MO = MI.getOperand(OpIdx);
1046  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1047  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1048  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1049  unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1050  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
1051  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
1053  unsigned SBits = getShiftOp(ShOp);
1054 
1055  // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1056  // amount. However, it would be an easy mistake to make so check here.
1057  assert((ShImm & ~0x1f) == 0 && "Out of range shift amount");
1058 
1059  // {16-13} = Rn
1060  // {12} = isAdd
1061  // {11-0} = shifter
1062  // {3-0} = Rm
1063  // {4} = 0
1064  // {6-5} = type
1065  // {11-7} = imm
1066  uint32_t Binary = Rm;
1067  Binary |= Rn << 13;
1068  Binary |= SBits << 5;
1069  Binary |= ShImm << 7;
1070  if (isAdd)
1071  Binary |= 1 << 12;
1072  return Binary;
1073 }
1074 
1075 uint32_t ARMMCCodeEmitter::
1076 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1077  SmallVectorImpl<MCFixup> &Fixups,
1078  const MCSubtargetInfo &STI) const {
1079  // {13} 1 == imm12, 0 == Rm
1080  // {12} isAdd
1081  // {11-0} imm12/Rm
1082  const MCOperand &MO = MI.getOperand(OpIdx);
1083  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1084  unsigned Imm = MO1.getImm();
1085  bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
1086  bool isReg = MO.getReg() != 0;
1087  uint32_t Binary = ARM_AM::getAM2Offset(Imm);
1088  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
1089  if (isReg) {
1091  Binary <<= 7; // Shift amount is bits [11:7]
1092  Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
1093  Binary |= CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); // Rm is bits [3:0]
1094  }
1095  return Binary | (isAdd << 12) | (isReg << 13);
1096 }
1097 
1098 uint32_t ARMMCCodeEmitter::
1099 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx,
1100  SmallVectorImpl<MCFixup> &Fixups,
1101  const MCSubtargetInfo &STI) const {
1102  // {4} isAdd
1103  // {3-0} Rm
1104  const MCOperand &MO = MI.getOperand(OpIdx);
1105  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1106  bool isAdd = MO1.getImm() != 0;
1107  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()) | (isAdd << 4);
1108 }
1109 
1110 uint32_t ARMMCCodeEmitter::
1111 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
1112  SmallVectorImpl<MCFixup> &Fixups,
1113  const MCSubtargetInfo &STI) const {
1114  // {9} 1 == imm8, 0 == Rm
1115  // {8} isAdd
1116  // {7-4} imm7_4/zero
1117  // {3-0} imm3_0/Rm
1118  const MCOperand &MO = MI.getOperand(OpIdx);
1119  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1120  unsigned Imm = MO1.getImm();
1121  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1122  bool isImm = MO.getReg() == 0;
1124  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1125  if (!isImm)
1126  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1127  return Imm8 | (isAdd << 8) | (isImm << 9);
1128 }
1129 
1130 uint32_t ARMMCCodeEmitter::
1131 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx,
1132  SmallVectorImpl<MCFixup> &Fixups,
1133  const MCSubtargetInfo &STI) const {
1134  // {13} 1 == imm8, 0 == Rm
1135  // {12-9} Rn
1136  // {8} isAdd
1137  // {7-4} imm7_4/zero
1138  // {3-0} imm3_0/Rm
1139  const MCOperand &MO = MI.getOperand(OpIdx);
1140  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
1141  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
1142 
1143  // If The first operand isn't a register, we have a label reference.
1144  if (!MO.isReg()) {
1145  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1146 
1147  assert(MO.isExpr() && "Unexpected machine operand type!");
1148  const MCExpr *Expr = MO.getExpr();
1150  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1151 
1152  ++MCNumCPRelocations;
1153  return (Rn << 9) | (1 << 13);
1154  }
1155  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1156  unsigned Imm = MO2.getImm();
1157  bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
1158  bool isImm = MO1.getReg() == 0;
1160  // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
1161  if (!isImm)
1162  Imm8 = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1163  return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
1164 }
1165 
1166 /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
1167 uint32_t ARMMCCodeEmitter::
1168 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
1169  SmallVectorImpl<MCFixup> &Fixups,
1170  const MCSubtargetInfo &STI) const {
1171  // [SP, #imm]
1172  // {7-0} = imm8
1173  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1174  assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
1175  "Unexpected base register!");
1176 
1177  // The immediate is already shifted for the implicit zeroes, so no change
1178  // here.
1179  return MO1.getImm() & 0xff;
1180 }
1181 
1182 /// getAddrModeISOpValue - Encode the t_addrmode_is# operands.
1183 uint32_t ARMMCCodeEmitter::
1184 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx,
1185  SmallVectorImpl<MCFixup> &Fixups,
1186  const MCSubtargetInfo &STI) const {
1187  // [Rn, #imm]
1188  // {7-3} = imm5
1189  // {2-0} = Rn
1190  const MCOperand &MO = MI.getOperand(OpIdx);
1191  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1192  unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1193  unsigned Imm5 = MO1.getImm();
1194  return ((Imm5 & 0x1f) << 3) | Rn;
1195 }
1196 
1197 /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
1198 uint32_t ARMMCCodeEmitter::
1199 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
1200  SmallVectorImpl<MCFixup> &Fixups,
1201  const MCSubtargetInfo &STI) const {
1202  const MCOperand MO = MI.getOperand(OpIdx);
1203  if (MO.isExpr())
1205  return (MO.getImm() >> 2);
1206 }
1207 
1208 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
1209 uint32_t ARMMCCodeEmitter::
1210 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
1211  SmallVectorImpl<MCFixup> &Fixups,
1212  const MCSubtargetInfo &STI) const {
1213  // {12-9} = reg
1214  // {8} = (U)nsigned (add == '1', sub == '0')
1215  // {7-0} = imm8
1216  unsigned Reg, Imm8;
1217  bool isAdd;
1218  // If The first operand isn't a register, we have a label reference.
1219  const MCOperand &MO = MI.getOperand(OpIdx);
1220  if (!MO.isReg()) {
1221  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1222  Imm8 = 0;
1223  isAdd = false; // 'U' bit is handled as part of the fixup.
1224 
1225  assert(MO.isExpr() && "Unexpected machine operand type!");
1226  const MCExpr *Expr = MO.getExpr();
1227  MCFixupKind Kind;
1228  if (isThumb2(STI))
1230  else
1232  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1233 
1234  ++MCNumCPRelocations;
1235  } else {
1236  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1237  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1238  }
1239 
1240  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1241  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1242  if (isAdd)
1243  Binary |= (1 << 8);
1244  Binary |= (Reg << 9);
1245  return Binary;
1246 }
1247 
1248 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
1249 uint32_t ARMMCCodeEmitter::
1250 getAddrMode5FP16OpValue(const MCInst &MI, unsigned OpIdx,
1251  SmallVectorImpl<MCFixup> &Fixups,
1252  const MCSubtargetInfo &STI) const {
1253  // {12-9} = reg
1254  // {8} = (U)nsigned (add == '1', sub == '0')
1255  // {7-0} = imm8
1256  unsigned Reg, Imm8;
1257  bool isAdd;
1258  // If The first operand isn't a register, we have a label reference.
1259  const MCOperand &MO = MI.getOperand(OpIdx);
1260  if (!MO.isReg()) {
1261  Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC.
1262  Imm8 = 0;
1263  isAdd = false; // 'U' bit is handled as part of the fixup.
1264 
1265  assert(MO.isExpr() && "Unexpected machine operand type!");
1266  const MCExpr *Expr = MO.getExpr();
1267  MCFixupKind Kind;
1268  if (isThumb2(STI))
1270  else
1272  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
1273 
1274  ++MCNumCPRelocations;
1275  } else {
1276  EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1277  isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add;
1278  }
1279 
1280  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
1281  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1282  if (isAdd)
1283  Binary |= (1 << 8);
1284  Binary |= (Reg << 9);
1285  return Binary;
1286 }
1287 
1288 unsigned ARMMCCodeEmitter::
1289 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
1290  SmallVectorImpl<MCFixup> &Fixups,
1291  const MCSubtargetInfo &STI) const {
1292  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
1293  // shifted. The second is Rs, the amount to shift by, and the third specifies
1294  // the type of the shift.
1295  //
1296  // {3-0} = Rm.
1297  // {4} = 1
1298  // {6-5} = type
1299  // {11-8} = Rs
1300  // {7} = 0
1301 
1302  const MCOperand &MO = MI.getOperand(OpIdx);
1303  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1304  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
1306 
1307  // Encode Rm.
1308  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1309 
1310  // Encode the shift opcode.
1311  unsigned SBits = 0;
1312  unsigned Rs = MO1.getReg();
1313  if (Rs) {
1314  // Set shift operand (bit[7:4]).
1315  // LSL - 0001
1316  // LSR - 0011
1317  // ASR - 0101
1318  // ROR - 0111
1319  switch (SOpc) {
1320  default: llvm_unreachable("Unknown shift opc!");
1321  case ARM_AM::lsl: SBits = 0x1; break;
1322  case ARM_AM::lsr: SBits = 0x3; break;
1323  case ARM_AM::asr: SBits = 0x5; break;
1324  case ARM_AM::ror: SBits = 0x7; break;
1325  }
1326  }
1327 
1328  Binary |= SBits << 4;
1329 
1330  // Encode the shift operation Rs.
1331  // Encode Rs bit[11:8].
1332  assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1333  return Binary | (CTX.getRegisterInfo()->getEncodingValue(Rs) << ARMII::RegRsShift);
1334 }
1335 
1336 unsigned ARMMCCodeEmitter::
1337 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
1338  SmallVectorImpl<MCFixup> &Fixups,
1339  const MCSubtargetInfo &STI) const {
1340  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1341  // shifted. The second is the amount to shift by.
1342  //
1343  // {3-0} = Rm.
1344  // {4} = 0
1345  // {6-5} = type
1346  // {11-7} = imm
1347 
1348  const MCOperand &MO = MI.getOperand(OpIdx);
1349  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1351 
1352  // Encode Rm.
1353  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1354 
1355  // Encode the shift opcode.
1356  unsigned SBits = 0;
1357 
1358  // Set shift operand (bit[6:4]).
1359  // LSL - 000
1360  // LSR - 010
1361  // ASR - 100
1362  // ROR - 110
1363  // RRX - 110 and bit[11:8] clear.
1364  switch (SOpc) {
1365  default: llvm_unreachable("Unknown shift opc!");
1366  case ARM_AM::lsl: SBits = 0x0; break;
1367  case ARM_AM::lsr: SBits = 0x2; break;
1368  case ARM_AM::asr: SBits = 0x4; break;
1369  case ARM_AM::ror: SBits = 0x6; break;
1370  case ARM_AM::rrx:
1371  Binary |= 0x60;
1372  return Binary;
1373  }
1374 
1375  // Encode shift_imm bit[11:7].
1376  Binary |= SBits << 4;
1377  unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm());
1378  assert(Offset < 32 && "Offset must be in range 0-31!");
1379  return Binary | (Offset << 7);
1380 }
1381 
1382 
1383 unsigned ARMMCCodeEmitter::
1384 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
1385  SmallVectorImpl<MCFixup> &Fixups,
1386  const MCSubtargetInfo &STI) const {
1387  const MCOperand &MO1 = MI.getOperand(OpNum);
1388  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1389  const MCOperand &MO3 = MI.getOperand(OpNum+2);
1390 
1391  // Encoded as [Rn, Rm, imm].
1392  // FIXME: Needs fixup support.
1393  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1394  Value <<= 4;
1395  Value |= CTX.getRegisterInfo()->getEncodingValue(MO2.getReg());
1396  Value <<= 2;
1397  Value |= MO3.getImm();
1398 
1399  return Value;
1400 }
1401 
1402 unsigned ARMMCCodeEmitter::
1403 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1404  SmallVectorImpl<MCFixup> &Fixups,
1405  const MCSubtargetInfo &STI) const {
1406  const MCOperand &MO1 = MI.getOperand(OpNum);
1407  const MCOperand &MO2 = MI.getOperand(OpNum+1);
1408 
1409  // FIXME: Needs fixup support.
1410  unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
1411 
1412  // Even though the immediate is 8 bits long, we need 9 bits in order
1413  // to represent the (inverse of the) sign bit.
1414  Value <<= 9;
1415  int32_t tmp = (int32_t)MO2.getImm();
1416  if (tmp < 0)
1417  tmp = abs(tmp);
1418  else
1419  Value |= 256; // Set the ADD bit
1420  Value |= tmp & 255;
1421  return Value;
1422 }
1423 
1424 unsigned ARMMCCodeEmitter::
1425 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
1426  SmallVectorImpl<MCFixup> &Fixups,
1427  const MCSubtargetInfo &STI) const {
1428  const MCOperand &MO1 = MI.getOperand(OpNum);
1429 
1430  // FIXME: Needs fixup support.
1431  unsigned Value = 0;
1432  int32_t tmp = (int32_t)MO1.getImm();
1433  if (tmp < 0)
1434  tmp = abs(tmp);
1435  else
1436  Value |= 256; // Set the ADD bit
1437  Value |= tmp & 255;
1438  return Value;
1439 }
1440 
1441 unsigned ARMMCCodeEmitter::
1442 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
1443  SmallVectorImpl<MCFixup> &Fixups,
1444  const MCSubtargetInfo &STI) const {
1445  // Sub-operands are [reg, imm]. The first register is Rm, the reg to be
1446  // shifted. The second is the amount to shift by.
1447  //
1448  // {3-0} = Rm.
1449  // {4} = 0
1450  // {6-5} = type
1451  // {11-7} = imm
1452 
1453  const MCOperand &MO = MI.getOperand(OpIdx);
1454  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1456 
1457  // Encode Rm.
1458  unsigned Binary = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1459 
1460  // Encode the shift opcode.
1461  unsigned SBits = 0;
1462  // Set shift operand (bit[6:4]).
1463  // LSL - 000
1464  // LSR - 010
1465  // ASR - 100
1466  // ROR - 110
1467  switch (SOpc) {
1468  default: llvm_unreachable("Unknown shift opc!");
1469  case ARM_AM::lsl: SBits = 0x0; break;
1470  case ARM_AM::lsr: SBits = 0x2; break;
1471  case ARM_AM::asr: SBits = 0x4; break;
1473  case ARM_AM::ror: SBits = 0x6; break;
1474  }
1475 
1476  Binary |= SBits << 4;
1477  if (SOpc == ARM_AM::rrx)
1478  return Binary;
1479 
1480  // Encode shift_imm bit[11:7].
1481  return Binary | ARM_AM::getSORegOffset(MO1.getImm()) << 7;
1482 }
1483 
1484 unsigned ARMMCCodeEmitter::
1485 getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
1486  SmallVectorImpl<MCFixup> &Fixups,
1487  const MCSubtargetInfo &STI) const {
1488  // 10 bits. lower 5 bits are the lsb of the mask, high five bits are the
1489  // msb of the mask.
1490  const MCOperand &MO = MI.getOperand(Op);
1491  uint32_t v = ~MO.getImm();
1492  uint32_t lsb = countTrailingZeros(v);
1493  uint32_t msb = (32 - countLeadingZeros (v)) - 1;
1494  assert(v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
1495  return lsb | (msb << 5);
1496 }
1497 
1498 unsigned ARMMCCodeEmitter::
1499 getRegisterListOpValue(const MCInst &MI, unsigned Op,
1500  SmallVectorImpl<MCFixup> &Fixups,
1501  const MCSubtargetInfo &STI) const {
1502  // VLDM/VSTM:
1503  // {12-8} = Vd
1504  // {7-0} = Number of registers
1505  //
1506  // LDM/STM:
1507  // {15-0} = Bitfield of GPRs.
1508  unsigned Reg = MI.getOperand(Op).getReg();
1509  bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1510  bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1511 
1512  unsigned Binary = 0;
1513 
1514  if (SPRRegs || DPRRegs) {
1515  // VLDM/VSTM
1516  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1517  unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
1518  Binary |= (RegNo & 0x1f) << 8;
1519  if (SPRRegs)
1520  Binary |= NumRegs;
1521  else
1522  Binary |= NumRegs * 2;
1523  } else {
1524  const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1525  assert(std::is_sorted(MI.begin() + Op, MI.end(),
1526  [&](const MCOperand &LHS, const MCOperand &RHS) {
1527  return MRI.getEncodingValue(LHS.getReg()) <
1528  MRI.getEncodingValue(RHS.getReg());
1529  }));
1530 
1531  for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1532  unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
1533  Binary |= 1 << RegNo;
1534  }
1535  }
1536 
1537  return Binary;
1538 }
1539 
1540 /// getAddrMode6AddressOpValue - Encode an addrmode6 register number along
1541 /// with the alignment operand.
1542 unsigned ARMMCCodeEmitter::
1543 getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
1544  SmallVectorImpl<MCFixup> &Fixups,
1545  const MCSubtargetInfo &STI) const {
1546  const MCOperand &Reg = MI.getOperand(Op);
1547  const MCOperand &Imm = MI.getOperand(Op + 1);
1548 
1549  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1550  unsigned Align = 0;
1551 
1552  switch (Imm.getImm()) {
1553  default: break;
1554  case 2:
1555  case 4:
1556  case 8: Align = 0x01; break;
1557  case 16: Align = 0x02; break;
1558  case 32: Align = 0x03; break;
1559  }
1560 
1561  return RegNo | (Align << 4);
1562 }
1563 
1564 /// getAddrMode6OneLane32AddressOpValue - Encode an addrmode6 register number
1565 /// along with the alignment operand for use in VST1 and VLD1 with size 32.
1566 unsigned ARMMCCodeEmitter::
1567 getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op,
1568  SmallVectorImpl<MCFixup> &Fixups,
1569  const MCSubtargetInfo &STI) const {
1570  const MCOperand &Reg = MI.getOperand(Op);
1571  const MCOperand &Imm = MI.getOperand(Op + 1);
1572 
1573  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1574  unsigned Align = 0;
1575 
1576  switch (Imm.getImm()) {
1577  default: break;
1578  case 8:
1579  case 16:
1580  case 32: // Default '0' value for invalid alignments of 8, 16, 32 bytes.
1581  case 2: Align = 0x00; break;
1582  case 4: Align = 0x03; break;
1583  }
1584 
1585  return RegNo | (Align << 4);
1586 }
1587 
1588 
1589 /// getAddrMode6DupAddressOpValue - Encode an addrmode6 register number and
1590 /// alignment operand for use in VLD-dup instructions. This is the same as
1591 /// getAddrMode6AddressOpValue except for the alignment encoding, which is
1592 /// different for VLD4-dup.
1593 unsigned ARMMCCodeEmitter::
1594 getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op,
1595  SmallVectorImpl<MCFixup> &Fixups,
1596  const MCSubtargetInfo &STI) const {
1597  const MCOperand &Reg = MI.getOperand(Op);
1598  const MCOperand &Imm = MI.getOperand(Op + 1);
1599 
1600  unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1601  unsigned Align = 0;
1602 
1603  switch (Imm.getImm()) {
1604  default: break;
1605  case 2:
1606  case 4:
1607  case 8: Align = 0x01; break;
1608  case 16: Align = 0x03; break;
1609  }
1610 
1611  return RegNo | (Align << 4);
1612 }
1613 
1614 unsigned ARMMCCodeEmitter::
1615 getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
1616  SmallVectorImpl<MCFixup> &Fixups,
1617  const MCSubtargetInfo &STI) const {
1618  const MCOperand &MO = MI.getOperand(Op);
1619  if (MO.getReg() == 0) return 0x0D;
1620  return CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
1621 }
1622 
1623 unsigned ARMMCCodeEmitter::
1624 getShiftRight8Imm(const MCInst &MI, unsigned Op,
1625  SmallVectorImpl<MCFixup> &Fixups,
1626  const MCSubtargetInfo &STI) const {
1627  return 8 - MI.getOperand(Op).getImm();
1628 }
1629 
1630 unsigned ARMMCCodeEmitter::
1631 getShiftRight16Imm(const MCInst &MI, unsigned Op,
1632  SmallVectorImpl<MCFixup> &Fixups,
1633  const MCSubtargetInfo &STI) const {
1634  return 16 - MI.getOperand(Op).getImm();
1635 }
1636 
1637 unsigned ARMMCCodeEmitter::
1638 getShiftRight32Imm(const MCInst &MI, unsigned Op,
1639  SmallVectorImpl<MCFixup> &Fixups,
1640  const MCSubtargetInfo &STI) const {
1641  return 32 - MI.getOperand(Op).getImm();
1642 }
1643 
1644 unsigned ARMMCCodeEmitter::
1645 getShiftRight64Imm(const MCInst &MI, unsigned Op,
1646  SmallVectorImpl<MCFixup> &Fixups,
1647  const MCSubtargetInfo &STI) const {
1648  return 64 - MI.getOperand(Op).getImm();
1649 }
1650 
1651 void ARMMCCodeEmitter::
1652 encodeInstruction(const MCInst &MI, raw_ostream &OS,
1653  SmallVectorImpl<MCFixup> &Fixups,
1654  const MCSubtargetInfo &STI) const {
1655  // Pseudo instructions don't get encoded.
1656  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
1657  uint64_t TSFlags = Desc.TSFlags;
1658  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
1659  return;
1660 
1661  int Size;
1662  if (Desc.getSize() == 2 || Desc.getSize() == 4)
1663  Size = Desc.getSize();
1664  else
1665  llvm_unreachable("Unexpected instruction size!");
1666 
1667  uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
1668  // Thumb 32-bit wide instructions need to emit the high order halfword
1669  // first.
1670  if (isThumb(STI) && Size == 4) {
1671  EmitConstant(Binary >> 16, 2, OS);
1672  EmitConstant(Binary & 0xffff, 2, OS);
1673  } else
1674  EmitConstant(Binary, Size, OS);
1675  ++MCNumEmitted; // Keep track of the # of mi's emitted.
1676 }
1677 
1678 #include "ARMGenMCCodeEmitter.inc"
1679 
1681  const MCRegisterInfo &MRI,
1682  MCContext &Ctx) {
1683  return new ARMMCCodeEmitter(MCII, Ctx, true);
1684 }
1685 
1687  const MCRegisterInfo &MRI,
1688  MCContext &Ctx) {
1689  return new ARMMCCodeEmitter(MCII, Ctx, false);
1690 }
static bool isReg(const MCInst &MI, unsigned OpNo)
uint64_t CallInst * C
iterator end()
Definition: MCInst.h:194
iterator begin()
Definition: MCInst.h:192
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
bool isImm() const
Definition: MCInst.h:58
SI Whole Quad Mode
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
VariantKind getKind() const
getOpcode - Get the kind of this expression.
Definition: ARMMCExpr.h:51
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
unsigned Reg
bool isReg() const
Definition: MCInst.h:57
STATISTIC(NumFunctions, "Total number of functions")
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:188
static Lanai::Fixups FixupKind(const MCExpr *Expr)
static bool isThumb(const MCSubtargetInfo &STI)
const Triple & getTargetTriple() const
ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
const FeatureBitset & getFeatureBits() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
Context object for machine code objects.
Definition: MCContext.h:62
unsigned char getAM3Offset(unsigned AM3Opc)
const MCExpr * getExpr() const
Definition: MCInst.h:95
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
AddrOpc getAM2Op(unsigned AM2Opc)
int64_t getImm() const
Definition: MCInst.h:75
unsigned char getAM5Offset(unsigned AM5Opc)
AddrOpc getAM3Op(unsigned AM3Opc)
unsigned const MachineRegisterInfo * MRI
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:119
unsigned getSORegOffset(unsigned Op)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool isFPImm() const
Definition: MCInst.h:59
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:22
This file declares a class to represent arbitrary precision floating point values and provide a varie...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
bool isExpr() const
Definition: MCInst.h:60
unsigned getNumOperands() const
Definition: MCInst.h:181
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:627
static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, SMLoc Loc=SMLoc())
Definition: MCFixup.h:90
static int32_t encodeThumbBLOffset(int32_t offset)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static bool HasConditionalBranch(const MCInst &MI)
Return true if this branch has a non-always predication.
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
ExprKind getKind() const
Definition: MCExpr.h:72
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
unsigned getAM2Offset(unsigned AM2Opc)
SMLoc getLoc() const
Definition: MCInst.h:177
ShiftOpc getSORegShOp(unsigned Op)
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
const MCExpr * getSubExpr() const
getSubExpr - Get the child of this expression.
Definition: ARMMCExpr.h:54
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
#define I(x, y, z)
Definition: MD5.cpp:58
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1212
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl< MCFixup > &Fixups, const MCSubtargetInfo &STI)
getBranchTargetOpValue - Helper function to get the branch target operand, which is either an immedia...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:294
LLVM Value Representation.
Definition: Value.h:72
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
Target specific expression.
Definition: MCExpr.h:42
AddrOpc getAM5Op(unsigned AM5Opc)
unsigned getOpcode() const
Definition: MCInst.h:171
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Function Alias Analysis false
double getFPImm() const
Definition: MCInst.h:85
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:580