LLVM 19.0.0git
ARMTargetTransformInfo.h
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1//===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file a TargetTransformInfo::Concept conforming object specific to the
11/// ARM target machine. It uses the target's detailed information to
12/// provide more precise answers to certain TTI queries, while letting the
13/// target independent and default TTI implementations handle the rest.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19
20#include "ARM.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/ADT/ArrayRef.h"
26#include "llvm/IR/Constant.h"
27#include "llvm/IR/Function.h"
29#include <optional>
30
31namespace llvm {
32
33class APInt;
34class ARMTargetLowering;
35class Instruction;
36class Loop;
37class SCEV;
38class ScalarEvolution;
39class Type;
40class Value;
41
42namespace TailPredication {
43 enum Mode {
49 };
50}
51
52// For controlling conversion of memcpy into Tail Predicated loop.
53namespace TPLoop {
55}
56
57class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
60
61 friend BaseT;
62
63 const ARMSubtarget *ST;
64 const ARMTargetLowering *TLI;
65
66 // Currently the following features are excluded from InlineFeaturesAllowed.
67 // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
68 // Depending on whether they are set or unset, different
69 // instructions/registers are available. For example, inlining a callee with
70 // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
71 // fail if the callee uses ARM only instructions, e.g. in inline asm.
72 const FeatureBitset InlineFeaturesAllowed = {
73 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
74 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
75 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
76 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
78 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
79 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
80 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
81 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
82 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
83 ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
84 ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
85 ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
86 ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
87 ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
88 ARM::FeatureHasSlowFPVMLx, ARM::FeatureHasSlowFPVFMx,
89 ARM::FeatureVMLxForwarding, ARM::FeaturePref32BitThumb,
90 ARM::FeatureAvoidPartialCPSR, ARM::FeatureCheapPredicableCPSR,
91 ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
92 ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
93 ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
94 ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
95 ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
96 ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
97 };
98
99 const ARMSubtarget *getST() const { return ST; }
100 const ARMTargetLowering *getTLI() const { return TLI; }
101
102public:
103 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
104 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
105 TLI(ST->getTargetLowering()) {}
106
107 bool areInlineCompatible(const Function *Caller,
108 const Function *Callee) const;
109
111
114
115 /// Floating-point computation using ARMv8 AArch32 Advanced
116 /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
117 /// and Arm MVE are IEEE-754 compliant.
119 return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
120 }
121
122 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
123 IntrinsicInst &II) const;
124 std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
125 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
126 APInt &UndefElts2, APInt &UndefElts3,
127 std::function<void(Instruction *, unsigned, APInt, APInt &)>
128 SimplifyAndSetOp) const;
129
130 /// \name Scalar TTI Implementations
131 /// @{
132
133 InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
134 const APInt &Imm, Type *Ty);
135
137 InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
139
140 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
141 const APInt &Imm, Type *Ty,
143 Instruction *Inst = nullptr);
144
145 /// @}
146
147 /// \name Vector TTI Implementations
148 /// @{
149
150 unsigned getNumberOfRegisters(unsigned ClassID) const {
151 bool Vector = (ClassID == 1);
152 if (Vector) {
153 if (ST->hasNEON())
154 return 16;
155 if (ST->hasMVEIntegerOps())
156 return 8;
157 return 0;
158 }
159
160 if (ST->isThumb1Only())
161 return 8;
162 return 13;
163 }
164
166 switch (K) {
168 return TypeSize::getFixed(32);
170 if (ST->hasNEON())
171 return TypeSize::getFixed(128);
172 if (ST->hasMVEIntegerOps())
173 return TypeSize::getFixed(128);
174 return TypeSize::getFixed(0);
176 return TypeSize::getScalable(0);
177 }
178 llvm_unreachable("Unsupported register kind");
179 }
180
182 return ST->getMaxInterleaveFactor();
183 }
184
186
187 bool isLegalMaskedLoad(Type *DataTy, Align Alignment);
188
189 bool isLegalMaskedStore(Type *DataTy, Align Alignment) {
190 return isLegalMaskedLoad(DataTy, Alignment);
191 }
192
194 // For MVE, we have a custom lowering pass that will already have custom
195 // legalised any gathers that we can lower to MVE intrinsics, and want to
196 // expand all the rest. The pass runs before the masked intrinsic lowering
197 // pass.
198 return true;
199 }
200
202 return forceScalarizeMaskedGather(VTy, Alignment);
203 }
204
205 bool isLegalMaskedGather(Type *Ty, Align Alignment);
206
207 bool isLegalMaskedScatter(Type *Ty, Align Alignment) {
208 return isLegalMaskedGather(Ty, Alignment);
209 }
210
212
214 return ST->getMaxInlineSizeThreshold();
215 }
216
217 int getNumMemOps(const IntrinsicInst *I) const;
218
220 ArrayRef<int> Mask,
222 VectorType *SubTp,
223 ArrayRef<const Value *> Args = std::nullopt);
224
225 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
226 TTI::ReductionFlags Flags) const;
227
228 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
229 TTI::ReductionFlags Flags) const;
230
231 bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
232
234 const Instruction *I = nullptr);
235
236 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
239 const Instruction *I = nullptr);
240
241 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
242 CmpInst::Predicate VecPred,
244 const Instruction *I = nullptr);
245
247 InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
249 unsigned Index, Value *Op0, Value *Op1);
250
252 const SCEV *Ptr);
253
255 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
257 TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
258 ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
259 const Instruction *CxtI = nullptr);
260
261 InstructionCost
262 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
264 TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
265 const Instruction *I = nullptr);
266
267 InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
268 Align Alignment, unsigned AddressSpace,
270
271 InstructionCost getInterleavedMemoryOpCost(
272 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
273 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
274 bool UseMaskForCond = false, bool UseMaskForGaps = false);
275
276 InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
277 const Value *Ptr, bool VariableMask,
278 Align Alignment,
280 const Instruction *I = nullptr);
281
282 InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
283 std::optional<FastMathFlags> FMF,
285 InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
286 Type *ResTy, VectorType *ValTy,
287 FastMathFlags FMF,
289 InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy,
290 VectorType *ValTy,
292
293 InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
294 FastMathFlags FMF,
296
297 InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
299
300 /// getScalingFactorCost - Return the cost of the scaling used in
301 /// addressing mode represented by AM.
302 /// If the AM is supported, the return value must be >= 0.
303 /// If the AM is not supported, the return value must be negative.
304 InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
305 int64_t BaseOffset, bool HasBaseReg,
306 int64_t Scale, unsigned AddrSpace) const;
307
308 bool maybeLoweredToCall(Instruction &I);
309 bool isLoweredToCall(const Function *F);
310 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
311 AssumptionCache &AC,
312 TargetLibraryInfo *LibInfo,
313 HardwareLoopInfo &HWLoopInfo);
314 bool preferPredicateOverEpilogue(TailFoldingInfo *TFI);
315 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
316 TTI::UnrollingPreferences &UP,
317 OptimizationRemarkEmitter *ORE);
318
320 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const;
321
322 void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
323 TTI::PeelingPreferences &PP);
325 // In the ROPI and RWPI relocation models we can't have pointers to global
326 // variables or functions in constant data, so don't convert switches to
327 // lookup tables if any of the values would need relocation.
328 if (ST->isROPI() || ST->isRWPI())
329 return !C->needsDynamicRelocation();
330
331 return true;
332 }
333
334 bool hasArmWideBranch(bool Thumb) const;
335
336 /// @}
337};
338
339/// isVREVMask - Check if a vector shuffle corresponds to a VREV
340/// instruction with the specified blocksize. (The order of the elements
341/// within each block of the vector is reversed.)
342inline bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
343 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
344 "Only possible block sizes for VREV are: 16, 32, 64");
345
346 unsigned EltSz = VT.getScalarSizeInBits();
347 if (EltSz != 8 && EltSz != 16 && EltSz != 32)
348 return false;
349
350 unsigned BlockElts = M[0] + 1;
351 // If the first shuffle index is UNDEF, be optimistic.
352 if (M[0] < 0)
353 BlockElts = BlockSize / EltSz;
354
355 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
356 return false;
357
358 for (unsigned i = 0, e = M.size(); i < e; ++i) {
359 if (M[i] < 0)
360 continue; // ignore UNDEF indices
361 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
362 return false;
363 }
364
365 return true;
366}
367
368} // end namespace llvm
369
370#endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
static const Function * getParent(const Value *V)
This file provides a helper that implements much of the TTI interface in terms of the target-independ...
RelocType Type
Definition: COFFYAML.cpp:391
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static const int BlockSize
Definition: TarWriter.cpp:33
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:76
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
bool maybeLoweredToCall(Instruction &I)
bool enableInterleavedAccessVectorization()
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
bool isLegalMaskedStore(Type *DataTy, Align Alignment)
bool isLegalMaskedLoad(Type *DataTy, Align Alignment)
InstructionCost getMemcpyCost(const Instruction *I)
bool shouldBuildLookupTablesForConstant(Constant *C) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
bool isLoweredToCall(const Function *F)
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *ValTy, TTI::TargetCostKind CostKind)
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
bool isFPVectorizationPotentiallyUnsafe()
Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv...
int getNumMemOps(const IntrinsicInst *I) const
Given a memcpy/memset/memmove instruction, return the number of memory operations performed,...
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
bool isLegalMaskedScatter(Type *Ty, Align Alignment)
bool shouldExpandReduction(const IntrinsicInst *II) const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool hasArmWideBranch(bool Thumb) const
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI)
ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isLegalMaskedGather(Type *Ty, Align Alignment)
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
unsigned getMaxInterleaveFactor(ElementCount VF)
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, FastMathFlags FMF, TTI::TargetCostKind CostKind)
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
unsigned getNumberOfRegisters(unsigned ClassID) const
bool isProfitableLSRChainElement(Instruction *I)
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:80
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:780
This is an important base class in LLVM.
Definition: Constant.h:41
Container class for subtarget features.
The core instruction combiner logic.
Definition: InstCombiner.h:47
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
This class represents an analyzed expression in the program.
The main scalar evolution driver.
const DataLayout & getDataLayout() const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
TargetCostKind
The kind of cost model.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
CastContextHint
Represents a hint about the context in which a cast is used.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:332
static constexpr TypeSize getScalable(ScalarTy MinimumSize)
Definition: TypeSize.h:335
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AddressSpace
Definition: NVPTXBaseInfo.h:21
bool isVREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:363
Flags describing the kind of vector reduction.