LLVM  16.0.0git
ARMTargetTransformInfo.h
Go to the documentation of this file.
1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
19 
20 #include "ARM.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/ADT/ArrayRef.h"
26 #include "llvm/IR/Constant.h"
27 #include "llvm/IR/Function.h"
29 #include <optional>
30 
31 namespace llvm {
32 
33 class APInt;
34 class ARMTargetLowering;
35 class Instruction;
36 class Loop;
37 class SCEV;
38 class ScalarEvolution;
39 class Type;
40 class Value;
41 
42 namespace TailPredication {
43  enum Mode {
44  Disabled = 0,
49  };
50 }
51 
52 // For controlling conversion of memcpy into Tail Predicated loop.
53 namespace TPLoop {
55 }
56 
57 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
59  using TTI = TargetTransformInfo;
60 
61  friend BaseT;
62 
63  const ARMSubtarget *ST;
64  const ARMTargetLowering *TLI;
65 
66  // Currently the following features are excluded from InlineFeaturesAllowed.
67  // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
68  // Depending on whether they are set or unset, different
69  // instructions/registers are available. For example, inlining a callee with
70  // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
71  // fail if the callee uses ARM only instructions, e.g. in inline asm.
72  const FeatureBitset InlineFeaturesAllowed = {
73  ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
74  ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
75  ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
76  ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
77  ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
78  ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
79  ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
80  ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
81  ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
82  ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
83  ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
84  ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
85  ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
86  ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
87  ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
88  ARM::FeatureHasSlowFPVMLx, ARM::FeatureHasSlowFPVFMx,
89  ARM::FeatureVMLxForwarding, ARM::FeaturePref32BitThumb,
90  ARM::FeatureAvoidPartialCPSR, ARM::FeatureCheapPredicableCPSR,
91  ARM::FeatureAvoidMOVsShOp, ARM::FeatureHasRetAddrStack,
92  ARM::FeatureHasNoBranchPredictor, ARM::FeatureDSP, ARM::FeatureMP,
93  ARM::FeatureVirtualization, ARM::FeatureMClass, ARM::FeatureRClass,
94  ARM::FeatureAClass, ARM::FeatureNaClTrap, ARM::FeatureStrictAlign,
95  ARM::FeatureLongCalls, ARM::FeatureExecuteOnly, ARM::FeatureReserveR9,
96  ARM::FeatureNoMovt, ARM::FeatureNoNegativeImmediates
97  };
98 
99  const ARMSubtarget *getST() const { return ST; }
100  const ARMTargetLowering *getTLI() const { return TLI; }
101 
102 public:
103  explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
104  : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
105  TLI(ST->getTargetLowering()) {}
106 
107  bool areInlineCompatible(const Function *Caller,
108  const Function *Callee) const;
109 
110  bool enableInterleavedAccessVectorization() { return true; }
111 
113  getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const;
114 
115  /// Floating-point computation using ARMv8 AArch32 Advanced
116  /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
117  /// and Arm MVE are IEEE-754 compliant.
119  return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
120  }
121 
122  std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
123  IntrinsicInst &II) const;
124  std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
125  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
126  APInt &UndefElts2, APInt &UndefElts3,
127  std::function<void(Instruction *, unsigned, APInt, APInt &)>
128  SimplifyAndSetOp) const;
129 
130  /// \name Scalar TTI Implementations
131  /// @{
132 
133  InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
134  const APInt &Imm, Type *Ty);
135 
136  using BaseT::getIntImmCost;
139 
140  InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
141  const APInt &Imm, Type *Ty,
143  Instruction *Inst = nullptr);
144 
145  /// @}
146 
147  /// \name Vector TTI Implementations
148  /// @{
149 
150  unsigned getNumberOfRegisters(unsigned ClassID) const {
151  bool Vector = (ClassID == 1);
152  if (Vector) {
153  if (ST->hasNEON())
154  return 16;
155  if (ST->hasMVEIntegerOps())
156  return 8;
157  return 0;
158  }
159 
160  if (ST->isThumb1Only())
161  return 8;
162  return 13;
163  }
164 
166  switch (K) {
168  return TypeSize::getFixed(32);
170  if (ST->hasNEON())
171  return TypeSize::getFixed(128);
172  if (ST->hasMVEIntegerOps())
173  return TypeSize::getFixed(128);
174  return TypeSize::getFixed(0);
176  return TypeSize::getScalable(0);
177  }
178  llvm_unreachable("Unsupported register kind");
179  }
180 
181  unsigned getMaxInterleaveFactor(unsigned VF) {
182  return ST->getMaxInterleaveFactor();
183  }
184 
186 
187  bool isLegalMaskedLoad(Type *DataTy, Align Alignment);
188 
189  bool isLegalMaskedStore(Type *DataTy, Align Alignment) {
190  return isLegalMaskedLoad(DataTy, Alignment);
191  }
192 
194  // For MVE, we have a custom lowering pass that will already have custom
195  // legalised any gathers that we can lower to MVE intrinsics, and want to
196  // expand all the rest. The pass runs before the masked intrinsic lowering
197  // pass.
198  return true;
199  }
200 
202  return forceScalarizeMaskedGather(VTy, Alignment);
203  }
204 
205  bool isLegalMaskedGather(Type *Ty, Align Alignment);
206 
207  bool isLegalMaskedScatter(Type *Ty, Align Alignment) {
208  return isLegalMaskedGather(Ty, Alignment);
209  }
210 
212 
213  int getNumMemOps(const IntrinsicInst *I) const;
214 
218  VectorType *SubTp,
219  ArrayRef<const Value *> Args = std::nullopt);
220 
221  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
222  TTI::ReductionFlags Flags) const;
223 
224  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
225  TTI::ReductionFlags Flags) const;
226 
227  bool shouldExpandReduction(const IntrinsicInst *II) const { return false; }
228 
230  const Instruction *I = nullptr);
231 
232  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
235  const Instruction *I = nullptr);
236 
237  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
238  CmpInst::Predicate VecPred,
240  const Instruction *I = nullptr);
241 
243  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
244  unsigned Index);
245 
247  const SCEV *Ptr);
248 
250  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
252  TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
253  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
254  const Instruction *CxtI = nullptr);
255 
256  InstructionCost
257  getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
259  TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
260  const Instruction *I = nullptr);
261 
262  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
263  Align Alignment, unsigned AddressSpace,
265 
266  InstructionCost getInterleavedMemoryOpCost(
267  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
268  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
269  bool UseMaskForCond = false, bool UseMaskForGaps = false);
270 
271  InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
272  const Value *Ptr, bool VariableMask,
273  Align Alignment,
275  const Instruction *I = nullptr);
276 
277  InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
278  std::optional<FastMathFlags> FMF,
280  InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
281  Type *ResTy, VectorType *ValTy,
282  std::optional<FastMathFlags> FMF,
284  InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy,
285  VectorType *ValTy,
287 
288  InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
290 
291  /// getScalingFactorCost - Return the cost of the scaling used in
292  /// addressing mode represented by AM.
293  /// If the AM is supported, the return value must be >= 0.
294  /// If the AM is not supported, the return value must be negative.
295  InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
296  int64_t BaseOffset, bool HasBaseReg,
297  int64_t Scale, unsigned AddrSpace) const;
298 
299  bool maybeLoweredToCall(Instruction &I);
300  bool isLoweredToCall(const Function *F);
301  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
302  AssumptionCache &AC,
303  TargetLibraryInfo *LibInfo,
304  HardwareLoopInfo &HWLoopInfo);
305  bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
306  AssumptionCache &AC, TargetLibraryInfo *TLI,
307  DominatorTree *DT,
308  LoopVectorizationLegality *LVL,
309  InterleavedAccessInfo *IAI);
310  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
311  TTI::UnrollingPreferences &UP,
312  OptimizationRemarkEmitter *ORE);
313 
315 
316  void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
317  TTI::PeelingPreferences &PP);
319  // In the ROPI and RWPI relocation models we can't have pointers to global
320  // variables or functions in constant data, so don't convert switches to
321  // lookup tables if any of the values would need relocation.
322  if (ST->isROPI() || ST->isRWPI())
323  return !C->needsDynamicRelocation();
324 
325  return true;
326  }
327  /// @}
328 };
329 
330 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
331 /// instruction with the specified blocksize. (The order of the elements
332 /// within each block of the vector is reversed.)
333 inline bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
334  assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
335  "Only possible block sizes for VREV are: 16, 32, 64");
336 
337  unsigned EltSz = VT.getScalarSizeInBits();
338  if (EltSz != 8 && EltSz != 16 && EltSz != 32)
339  return false;
340 
341  unsigned BlockElts = M[0] + 1;
342  // If the first shuffle index is UNDEF, be optimistic.
343  if (M[0] < 0)
344  BlockElts = BlockSize / EltSz;
345 
346  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
347  return false;
348 
349  for (unsigned i = 0, e = M.size(); i < e; ++i) {
350  if (M[i] < 0)
351  continue; // ignore UNDEF indices
352  if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
353  return false;
354  }
355 
356  return true;
357 }
358 
359 } // end namespace llvm
360 
361 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::ARMTTIImpl::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1680
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:218
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Definition: ARMTargetTransformInfo.h:318
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1457
BlockSize
static const int BlockSize
Definition: TarWriter.cpp:33
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMTTIImpl::getRegisterBitWidth
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
Definition: ARMTargetTransformInfo.h:165
llvm::TailPredication::Disabled
@ Disabled
Definition: ARMTargetTransformInfo.h:44
llvm::ARMTTIImpl::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: ARMTargetTransformInfo.cpp:1515
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::ARMTTIImpl::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: ARMTargetTransformInfo.cpp:87
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:967
llvm::ARMTTIImpl::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1556
llvm::ARMTTIImpl::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:458
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:391
llvm::ARMTTIImpl::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:193
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
llvm::FeatureBitset
Container class for subtarget features.
Definition: SubtargetFeature.h:40
llvm::TargetTransformInfoImplBase::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfoImpl.h:395
VectorType
Definition: ItaniumDemangle.h:1075
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:926
llvm::ARMTTIImpl::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
Definition: ARMTargetTransformInfo.cpp:2289
llvm::TailPredication::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:48
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ARMTTIImpl::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1095
llvm::ARMTTIImpl::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
Definition: ARMTargetTransformInfo.cpp:1995
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:57
llvm::TargetTransformInfoImplBase::getDataLayout
const DataLayout & getDataLayout() const
Definition: TargetTransformInfoImpl.h:47
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
SubtargetFeature.h
llvm::ARMTTIImpl::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Definition: ARMTargetTransformInfo.cpp:2279
llvm::ARMTTIImpl::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: ARMTargetTransformInfo.h:150
llvm::BasicTTIImplBase< ARMTTIImpl >::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:1187
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:918
llvm::ARMTTIImpl::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
Definition: ARMTargetTransformInfo.cpp:387
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:889
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1142
llvm::TailPredication::Enabled
@ Enabled
Definition: ARMTargetTransformInfo.h:46
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMTTIImpl::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:1450
llvm::ARMTTIImpl::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)
Definition: ARMTargetTransformInfo.cpp:2231
llvm::ARMTTIImpl::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
Definition: ARMTargetTransformInfo.cpp:330
llvm::dwarf::Index
Index
Definition: Dwarf.h:490
llvm::ARMTTIImpl::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
Definition: ARMTargetTransformInfo.cpp:1310
llvm::Instruction
Definition: Instruction.h:42
llvm::ARMTTIImpl::isLoweredToCall
bool isLoweredToCall(const Function *F)
Definition: ARMTargetTransformInfo.cpp:1847
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:967
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::isVREVMask
bool isVREVMask(ArrayRef< int > M, EVT VT, unsigned BlockSize)
isVREVMask - Check if a vector shuffle corresponds to a VREV instruction with the specified blocksize...
Definition: ARMTargetTransformInfo.h:333
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::ARMTTIImpl::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: ARMTargetTransformInfo.h:227
llvm::LinearPolySize< TypeSize >::getFixed
static TypeSize getFixed(ScalarTy MinVal)
Definition: TypeSize.h:283
llvm::ARMTTIImpl::getNumMemOps
int getNumMemOps(const IntrinsicInst *I) const
Given a memcpy/memset/memmove instruction, return the number of memory operations performed,...
Definition: ARMTargetTransformInfo.cpp:1127
llvm::ARMTTIImpl::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1078
llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe()
Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv...
Definition: ARMTargetTransformInfo.h:118
llvm::ARMTTIImpl::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:201
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Definition: ARMTargetTransformInfo.cpp:253
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TailPredication::Mode
Mode
Definition: ARMTargetTransformInfo.h:43
llvm::ARMTTIImpl::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1656
llvm::ARMTTIImpl::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I)
Definition: ARMTargetTransformInfo.cpp:1193
llvm::ARMTTIImpl::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
Definition: ARMTargetTransformInfo.cpp:1056
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:53
llvm::TPLoop::ForceDisabled
@ ForceDisabled
Definition: ARMTargetTransformInfo.h:54
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMTTIImpl::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1742
llvm::BasicTTIImplBase
Base class which can be used to help build a TTI implementation.
Definition: BasicTTIImpl.h:79
ArrayRef.h
TemplateParamKind::Type
@ Type
llvm::ARMTTIImpl::instCombineIntrinsic
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Definition: ARMTargetTransformInfo.cpp:122
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMTTIImpl::getShuffleCost
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
Definition: ARMTargetTransformInfo.cpp:1203
llvm::ARMTTIImpl::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1498
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::ARMTTIImpl::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2397
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
ARM.h
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::ARMTTIImpl::getPreferredAddressingMode
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Definition: ARMTargetTransformInfo.cpp:106
llvm::ArrayRef< int >
llvm::EVT::getScalarSizeInBits
uint64_t getScalarSizeInBits() const
Definition: ValueTypes.h:352
llvm::ARMTTIImpl::isLegalMaskedGather
bool isLegalMaskedGather(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.cpp:1115
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
getParent
static const Function * getParent(const Value *V)
Definition: BasicAliasAnalysis.cpp:805
llvm::ARMTTIImpl::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:912
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:632
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:910
Constant.h
llvm::TPLoop::ForceEnabled
@ ForceEnabled
Definition: ARMTargetTransformInfo.h:54
llvm::ARMTTIImpl::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization()
Definition: ARMTargetTransformInfo.h:110
llvm::ARMTTIImpl::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:295
llvm::TypeSize
Definition: TypeSize.h:435
Function.h
llvm::LinearPolySize< TypeSize >::getScalable
static TypeSize getScalable(ScalarTy MinVal)
Definition: TypeSize.h:286
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ARMTTIImpl::ARMTTIImpl
ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
Definition: ARMTargetTransformInfo.h:103
llvm::ARMTTIImpl::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *Ty, Align Alignment)
Definition: ARMTargetTransformInfo.h:207
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:166
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:967
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ARMTTIImpl::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
Definition: ARMTargetTransformInfo.cpp:2418
llvm::ARMTTIImpl::maybeLoweredToCall
bool maybeLoweredToCall(Instruction &I)
Definition: ARMTargetTransformInfo.cpp:1908
llvm::ARMTTIImpl::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
Definition: ARMTargetTransformInfo.cpp:472
llvm::TPLoop::MemTransfer
MemTransfer
Definition: ARMTargetTransformInfo.h:54
llvm::TargetTransformInfo::RegisterKind
RegisterKind
Definition: TargetTransformInfo.h:967
llvm::ARMTTIImpl::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *ValTy, TTI::TargetCostKind CostKind)
Definition: ARMTargetTransformInfo.cpp:1715
llvm::TailPredication::EnabledNoReductions
@ EnabledNoReductions
Definition: ARMTargetTransformInfo.h:45
llvm::TPLoop::Allow
@ Allow
Definition: ARMTargetTransformInfo.h:54
llvm::ARMTTIImpl::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataTy, Align Alignment)
Definition: ARMTargetTransformInfo.h:189
TargetTransformInfo.h
llvm::ARMTTIImpl::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
Definition: ARMTargetTransformInfo.cpp:2392
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::ARMTTIImpl::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
Definition: ARMTargetTransformInfo.cpp:2411
llvm::ARMTTIImpl::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: ARMTargetTransformInfo.cpp:876
llvm::ARMTTIImpl::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF)
Definition: ARMTargetTransformInfo.h:181
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
BasicTTIImpl.h
ARMTargetMachine.h
llvm::TailPredication::ForceEnabledNoReductions
@ ForceEnabledNoReductions
Definition: ARMTargetTransformInfo.h:47