LLVM  9.0.0svn
ARMTargetTransformInfo.cpp
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1 //===- ARMTargetTransformInfo.cpp - ARM specific TTI ----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
10 #include "ARMSubtarget.h"
12 #include "llvm/ADT/APInt.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/Analysis/LoopInfo.h"
15 #include "llvm/CodeGen/CostTable.h"
18 #include "llvm/IR/BasicBlock.h"
19 #include "llvm/IR/CallSite.h"
20 #include "llvm/IR/DataLayout.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Instruction.h"
23 #include "llvm/IR/Instructions.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/Type.h"
27 #include "llvm/Support/Casting.h"
30 #include <algorithm>
31 #include <cassert>
32 #include <cstdint>
33 #include <utility>
34 
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "armtti"
38 
40  "disable-arm-loloops", cl::Hidden, cl::init(true),
41  cl::desc("Disable the generation of low-overhead loops"));
42 
44  const Function *Callee) const {
45  const TargetMachine &TM = getTLI()->getTargetMachine();
46  const FeatureBitset &CallerBits =
47  TM.getSubtargetImpl(*Caller)->getFeatureBits();
48  const FeatureBitset &CalleeBits =
49  TM.getSubtargetImpl(*Callee)->getFeatureBits();
50 
51  // To inline a callee, all features not in the whitelist must match exactly.
52  bool MatchExact = (CallerBits & ~InlineFeatureWhitelist) ==
53  (CalleeBits & ~InlineFeatureWhitelist);
54  // For features in the whitelist, the callee's features must be a subset of
55  // the callers'.
56  bool MatchSubset = ((CallerBits & CalleeBits) & InlineFeatureWhitelist) ==
57  (CalleeBits & InlineFeatureWhitelist);
58  return MatchExact && MatchSubset;
59 }
60 
61 int ARMTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
62  assert(Ty->isIntegerTy());
63 
64  unsigned Bits = Ty->getPrimitiveSizeInBits();
65  if (Bits == 0 || Imm.getActiveBits() >= 64)
66  return 4;
67 
68  int64_t SImmVal = Imm.getSExtValue();
69  uint64_t ZImmVal = Imm.getZExtValue();
70  if (!ST->isThumb()) {
71  if ((SImmVal >= 0 && SImmVal < 65536) ||
72  (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
73  (ARM_AM::getSOImmVal(~ZImmVal) != -1))
74  return 1;
75  return ST->hasV6T2Ops() ? 2 : 3;
76  }
77  if (ST->isThumb2()) {
78  if ((SImmVal >= 0 && SImmVal < 65536) ||
79  (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
80  (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
81  return 1;
82  return ST->hasV6T2Ops() ? 2 : 3;
83  }
84  // Thumb1, any i8 imm cost 1.
85  if (Bits == 8 || (SImmVal >= 0 && SImmVal < 256))
86  return 1;
87  if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
88  return 2;
89  // Load from constantpool.
90  return 3;
91 }
92 
93 // Constants smaller than 256 fit in the immediate field of
94 // Thumb1 instructions so we return a zero cost and 1 otherwise.
95 int ARMTTIImpl::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
96  const APInt &Imm, Type *Ty) {
97  if (Imm.isNonNegative() && Imm.getLimitedValue() < 256)
98  return 0;
99 
100  return 1;
101 }
102 
103 int ARMTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
104  Type *Ty) {
105  // Division by a constant can be turned into multiplication, but only if we
106  // know it's constant. So it's not so much that the immediate is cheap (it's
107  // not), but that the alternative is worse.
108  // FIXME: this is probably unneeded with GlobalISel.
109  if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
110  Opcode == Instruction::SRem || Opcode == Instruction::URem) &&
111  Idx == 1)
112  return 0;
113 
114  if (Opcode == Instruction::And) {
115  // UXTB/UXTH
116  if (Imm == 255 || Imm == 65535)
117  return 0;
118  // Conversion to BIC is free, and means we can use ~Imm instead.
119  return std::min(getIntImmCost(Imm, Ty), getIntImmCost(~Imm, Ty));
120  }
121 
122  if (Opcode == Instruction::Add)
123  // Conversion to SUB is free, and means we can use -Imm instead.
124  return std::min(getIntImmCost(Imm, Ty), getIntImmCost(-Imm, Ty));
125 
126  if (Opcode == Instruction::ICmp && Imm.isNegative() &&
127  Ty->getIntegerBitWidth() == 32) {
128  int64_t NegImm = -Imm.getSExtValue();
129  if (ST->isThumb2() && NegImm < 1<<12)
130  // icmp X, #-C -> cmn X, #C
131  return 0;
132  if (ST->isThumb() && NegImm < 1<<8)
133  // icmp X, #-C -> adds X, #C
134  return 0;
135  }
136 
137  // xor a, -1 can always be folded to MVN
138  if (Opcode == Instruction::Xor && Imm.isAllOnesValue())
139  return 0;
140 
141  return getIntImmCost(Imm, Ty);
142 }
143 
144 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
145  const Instruction *I) {
146  int ISD = TLI->InstructionOpcodeToISD(Opcode);
147  assert(ISD && "Invalid opcode");
148 
149  // Single to/from double precision conversions.
150  static const CostTblEntry NEONFltDblTbl[] = {
151  // Vector fptrunc/fpext conversions.
152  { ISD::FP_ROUND, MVT::v2f64, 2 },
153  { ISD::FP_EXTEND, MVT::v2f32, 2 },
154  { ISD::FP_EXTEND, MVT::v4f32, 4 }
155  };
156 
157  if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
158  ISD == ISD::FP_EXTEND)) {
159  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
160  if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second))
161  return LT.first * Entry->Cost;
162  }
163 
164  EVT SrcTy = TLI->getValueType(DL, Src);
165  EVT DstTy = TLI->getValueType(DL, Dst);
166 
167  if (!SrcTy.isSimple() || !DstTy.isSimple())
168  return BaseT::getCastInstrCost(Opcode, Dst, Src);
169 
170  // Some arithmetic, load and store operations have specific instructions
171  // to cast up/down their types automatically at no extra cost.
172  // TODO: Get these tables to know at least what the related operations are.
173  static const TypeConversionCostTblEntry NEONVectorConversionTbl[] = {
180 
181  // The number of vmovl instructions for the extension.
192 
193  // Operations that we legalize using splitting.
196 
197  // Vector float <-> i32 conversions.
200 
221 
228 
229  // Vector double <-> i32 conversions.
232 
239 
246  };
247 
248  if (SrcTy.isVector() && ST->hasNEON()) {
249  if (const auto *Entry = ConvertCostTableLookup(NEONVectorConversionTbl, ISD,
250  DstTy.getSimpleVT(),
251  SrcTy.getSimpleVT()))
252  return Entry->Cost;
253  }
254 
255  // Scalar float to integer conversions.
256  static const TypeConversionCostTblEntry NEONFloatConversionTbl[] = {
277  };
278  if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
279  if (const auto *Entry = ConvertCostTableLookup(NEONFloatConversionTbl, ISD,
280  DstTy.getSimpleVT(),
281  SrcTy.getSimpleVT()))
282  return Entry->Cost;
283  }
284 
285  // Scalar integer to float conversions.
286  static const TypeConversionCostTblEntry NEONIntegerConversionTbl[] = {
307  };
308 
309  if (SrcTy.isInteger() && ST->hasNEON()) {
310  if (const auto *Entry = ConvertCostTableLookup(NEONIntegerConversionTbl,
311  ISD, DstTy.getSimpleVT(),
312  SrcTy.getSimpleVT()))
313  return Entry->Cost;
314  }
315 
316  // Scalar integer conversion costs.
317  static const TypeConversionCostTblEntry ARMIntegerConversionTbl[] = {
318  // i16 -> i64 requires two dependent operations.
320 
321  // Truncates on i64 are assumed to be free.
324  { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
326  };
327 
328  if (SrcTy.isInteger()) {
329  if (const auto *Entry = ConvertCostTableLookup(ARMIntegerConversionTbl, ISD,
330  DstTy.getSimpleVT(),
331  SrcTy.getSimpleVT()))
332  return Entry->Cost;
333  }
334 
335  return BaseT::getCastInstrCost(Opcode, Dst, Src);
336 }
337 
338 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
339  unsigned Index) {
340  // Penalize inserting into an D-subregister. We end up with a three times
341  // lower estimated throughput on swift.
342  if (ST->hasSlowLoadDSubregister() && Opcode == Instruction::InsertElement &&
343  ValTy->isVectorTy() && ValTy->getScalarSizeInBits() <= 32)
344  return 3;
345 
346  if ((Opcode == Instruction::InsertElement ||
347  Opcode == Instruction::ExtractElement)) {
348  // Cross-class copies are expensive on many microarchitectures,
349  // so assume they are expensive by default.
350  if (ValTy->getVectorElementType()->isIntegerTy())
351  return 3;
352 
353  // Even if it's not a cross class copy, this likely leads to mixing
354  // of NEON and VFP code and should be therefore penalized.
355  if (ValTy->isVectorTy() &&
356  ValTy->getScalarSizeInBits() <= 32)
357  return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U);
358  }
359 
360  return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
361 }
362 
363 int ARMTTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
364  const Instruction *I) {
365  int ISD = TLI->InstructionOpcodeToISD(Opcode);
366  // On NEON a vector select gets lowered to vbsl.
367  if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
368  // Lowering of some vector selects is currently far from perfect.
369  static const TypeConversionCostTblEntry NEONVectorSelectTbl[] = {
370  { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
371  { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
373  };
374 
375  EVT SelCondTy = TLI->getValueType(DL, CondTy);
376  EVT SelValTy = TLI->getValueType(DL, ValTy);
377  if (SelCondTy.isSimple() && SelValTy.isSimple()) {
378  if (const auto *Entry = ConvertCostTableLookup(NEONVectorSelectTbl, ISD,
379  SelCondTy.getSimpleVT(),
380  SelValTy.getSimpleVT()))
381  return Entry->Cost;
382  }
383 
384  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, ValTy);
385  return LT.first;
386  }
387 
388  return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
389 }
390 
392  const SCEV *Ptr) {
393  // Address computations in vectorized code with non-consecutive addresses will
394  // likely result in more instructions compared to scalar code where the
395  // computation can more often be merged into the index mode. The resulting
396  // extra micro-ops can significantly decrease throughput.
397  unsigned NumVectorInstToHideOverhead = 10;
398  int MaxMergeDistance = 64;
399 
400  if (Ty->isVectorTy() && SE &&
401  !BaseT::isConstantStridedAccessLessThan(SE, Ptr, MaxMergeDistance + 1))
402  return NumVectorInstToHideOverhead;
403 
404  // In many cases the address computation is not merged into the instruction
405  // addressing mode.
406  return 1;
407 }
408 
410  const MemCpyInst *MI = dyn_cast<MemCpyInst>(I);
411  assert(MI && "MemcpyInst expected");
413 
414  // To model the cost of a library call, we assume 1 for the call, and
415  // 3 for the argument setup.
416  const unsigned LibCallCost = 4;
417 
418  // If 'size' is not a constant, a library call will be generated.
419  if (!C)
420  return LibCallCost;
421 
422  const unsigned Size = C->getValue().getZExtValue();
423  const unsigned DstAlign = MI->getDestAlignment();
424  const unsigned SrcAlign = MI->getSourceAlignment();
425  const Function *F = I->getParent()->getParent();
426  const unsigned Limit = TLI->getMaxStoresPerMemmove(F->hasMinSize());
427  std::vector<EVT> MemOps;
428 
429  // MemOps will be poplulated with a list of data types that needs to be
430  // loaded and stored. That's why we multiply the number of elements by 2 to
431  // get the cost for this memcpy.
432  if (getTLI()->findOptimalMemOpLowering(
433  MemOps, Limit, Size, DstAlign, SrcAlign, false /*IsMemset*/,
434  false /*ZeroMemset*/, false /*MemcpyStrSrc*/, false /*AllowOverlap*/,
436  F->getAttributes()))
437  return MemOps.size() * 2;
438 
439  // If we can't find an optimal memop lowering, return the default cost
440  return LibCallCost;
441 }
442 
444  Type *SubTp) {
445  if (Kind == TTI::SK_Broadcast) {
446  static const CostTblEntry NEONDupTbl[] = {
447  // VDUP handles these cases.
454 
459 
460  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
461 
462  if (const auto *Entry = CostTableLookup(NEONDupTbl, ISD::VECTOR_SHUFFLE,
463  LT.second))
464  return LT.first * Entry->Cost;
465 
466  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
467  }
468  if (Kind == TTI::SK_Reverse) {
469  static const CostTblEntry NEONShuffleTbl[] = {
470  // Reverse shuffle cost one instruction if we are shuffling within a
471  // double word (vrev) or two if we shuffle a quad word (vrev, vext).
478 
483 
484  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
485 
486  if (const auto *Entry = CostTableLookup(NEONShuffleTbl, ISD::VECTOR_SHUFFLE,
487  LT.second))
488  return LT.first * Entry->Cost;
489 
490  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
491  }
492  if (Kind == TTI::SK_Select) {
493  static const CostTblEntry NEONSelShuffleTbl[] = {
494  // Select shuffle cost table for ARM. Cost is the number of instructions
495  // required to create the shuffled vector.
496 
501 
505 
507 
509 
510  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
511  if (const auto *Entry = CostTableLookup(NEONSelShuffleTbl,
512  ISD::VECTOR_SHUFFLE, LT.second))
513  return LT.first * Entry->Cost;
514  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
515  }
516  return BaseT::getShuffleCost(Kind, Tp, Index, SubTp);
517 }
518 
520  unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
522  TTI::OperandValueProperties Opd2PropInfo,
524  int ISDOpcode = TLI->InstructionOpcodeToISD(Opcode);
525  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
526 
527  const unsigned FunctionCallDivCost = 20;
528  const unsigned ReciprocalDivCost = 10;
529  static const CostTblEntry CostTbl[] = {
530  // Division.
531  // These costs are somewhat random. Choose a cost of 20 to indicate that
532  // vectorizing devision (added function call) is going to be very expensive.
533  // Double registers types.
534  { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
535  { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
536  { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
537  { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
538  { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
539  { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
540  { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
541  { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
542  { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
543  { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
544  { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
545  { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
546  { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
547  { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
548  { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
549  { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
550  // Quad register types.
551  { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
552  { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
553  { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
554  { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
555  { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
556  { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
557  { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
558  { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
559  { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
560  { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
561  { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
562  { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
563  { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
564  { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
565  { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
566  { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
567  // Multiplication.
568  };
569 
570  if (ST->hasNEON())
571  if (const auto *Entry = CostTableLookup(CostTbl, ISDOpcode, LT.second))
572  return LT.first * Entry->Cost;
573 
574  int Cost = BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info,
575  Opd1PropInfo, Opd2PropInfo);
576 
577  // This is somewhat of a hack. The problem that we are facing is that SROA
578  // creates a sequence of shift, and, or instructions to construct values.
579  // These sequences are recognized by the ISel and have zero-cost. Not so for
580  // the vectorized code. Because we have support for v2i64 but not i64 those
581  // sequences look particularly beneficial to vectorize.
582  // To work around this we increase the cost of v2i64 operations to make them
583  // seem less beneficial.
584  if (LT.second == MVT::v2i64 &&
586  Cost += 4;
587 
588  return Cost;
589 }
590 
591 int ARMTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
592  unsigned AddressSpace, const Instruction *I) {
593  std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
594 
595  if (Src->isVectorTy() && Alignment != 16 &&
596  Src->getVectorElementType()->isDoubleTy()) {
597  // Unaligned loads/stores are extremely inefficient.
598  // We need 4 uops for vst.1/vld.1 vs 1uop for vldr/vstr.
599  return LT.first * 4;
600  }
601  return LT.first;
602 }
603 
604 int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
605  unsigned Factor,
606  ArrayRef<unsigned> Indices,
607  unsigned Alignment,
608  unsigned AddressSpace,
609  bool UseMaskForCond,
610  bool UseMaskForGaps) {
611  assert(Factor >= 2 && "Invalid interleave factor");
612  assert(isa<VectorType>(VecTy) && "Expect a vector type");
613 
614  // vldN/vstN doesn't support vector types of i64/f64 element.
615  bool EltIs64Bits = DL.getTypeSizeInBits(VecTy->getScalarType()) == 64;
616 
617  if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits &&
618  !UseMaskForCond && !UseMaskForGaps) {
619  unsigned NumElts = VecTy->getVectorNumElements();
620  auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
621 
622  // vldN/vstN only support legal vector types of size 64 or 128 in bits.
623  // Accesses having vector types that are a multiple of 128 bits can be
624  // matched to more than one vldN/vstN instruction.
625  if (NumElts % Factor == 0 &&
626  TLI->isLegalInterleavedAccessType(SubVecTy, DL))
627  return Factor * TLI->getNumInterleavedAccesses(SubVecTy, DL);
628  }
629 
630  return BaseT::getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
631  Alignment, AddressSpace,
632  UseMaskForCond, UseMaskForGaps);
633 }
634 
636  if (!F->isIntrinsic())
638 
639  // Assume all Arm-specific intrinsics map to an instruction.
640  if (F->getName().startswith("llvm.arm"))
641  return false;
642 
643  switch (F->getIntrinsicID()) {
644  default: break;
645  case Intrinsic::powi:
646  case Intrinsic::sin:
647  case Intrinsic::cos:
648  case Intrinsic::pow:
649  case Intrinsic::log:
650  case Intrinsic::log10:
651  case Intrinsic::log2:
652  case Intrinsic::exp:
653  case Intrinsic::exp2:
654  return true;
655  case Intrinsic::sqrt:
656  case Intrinsic::fabs:
657  case Intrinsic::copysign:
658  case Intrinsic::floor:
659  case Intrinsic::ceil:
660  case Intrinsic::trunc:
661  case Intrinsic::rint:
662  case Intrinsic::nearbyint:
663  case Intrinsic::round:
664  case Intrinsic::canonicalize:
665  case Intrinsic::lround:
666  case Intrinsic::llround:
667  case Intrinsic::lrint:
668  case Intrinsic::llrint:
669  if (F->getReturnType()->isDoubleTy() && !ST->hasFP64())
670  return true;
671  if (F->getReturnType()->isHalfTy() && !ST->hasFullFP16())
672  return true;
673  // Some operations can be handled by vector instructions and assume
674  // unsupported vectors will be expanded into supported scalar ones.
675  // TODO Handle scalar operations properly.
676  return !ST->hasFPARMv8Base() && !ST->hasVFP2Base();
677  case Intrinsic::masked_store:
678  case Intrinsic::masked_load:
679  case Intrinsic::masked_gather:
680  case Intrinsic::masked_scatter:
681  return !ST->hasMVEIntegerOps();
682  case Intrinsic::sadd_with_overflow:
683  case Intrinsic::uadd_with_overflow:
684  case Intrinsic::ssub_with_overflow:
685  case Intrinsic::usub_with_overflow:
686  case Intrinsic::sadd_sat:
687  case Intrinsic::uadd_sat:
688  case Intrinsic::ssub_sat:
689  case Intrinsic::usub_sat:
690  return false;
691  }
692 
693  return BaseT::isLoweredToCall(F);
694 }
695 
697  AssumptionCache &AC,
698  TargetLibraryInfo *LibInfo,
699  HardwareLoopInfo &HWLoopInfo) {
700  // Low-overhead branches are only supported in the 'low-overhead branch'
701  // extension of v8.1-m.
702  if (!ST->hasLOB() || DisableLowOverheadLoops)
703  return false;
704 
706  return false;
707 
708  const SCEV *BackedgeTakenCount = SE.getBackedgeTakenCount(L);
709  if (isa<SCEVCouldNotCompute>(BackedgeTakenCount))
710  return false;
711 
712  const SCEV *TripCountSCEV =
713  SE.getAddExpr(BackedgeTakenCount,
714  SE.getOne(BackedgeTakenCount->getType()));
715 
716  // We need to store the trip count in LR, a 32-bit register.
717  if (SE.getUnsignedRangeMax(TripCountSCEV).getBitWidth() > 32)
718  return false;
719 
720  // Making a call will trash LR and clear LO_BRANCH_INFO, so there's little
721  // point in generating a hardware loop if that's going to happen.
722  auto MaybeCall = [this](Instruction &I) {
723  const ARMTargetLowering *TLI = getTLI();
724  unsigned ISD = TLI->InstructionOpcodeToISD(I.getOpcode());
725  EVT VT = TLI->getValueType(DL, I.getType(), true);
726  if (TLI->getOperationAction(ISD, VT) == TargetLowering::LibCall)
727  return true;
728 
729  // Check if an intrinsic will be lowered to a call and assume that any
730  // other CallInst will generate a bl.
731  if (auto *Call = dyn_cast<CallInst>(&I)) {
732  if (isa<IntrinsicInst>(Call)) {
733  if (const Function *F = Call->getCalledFunction())
734  return isLoweredToCall(F);
735  }
736  return true;
737  }
738 
739  // FPv5 provides conversions between integer, double-precision,
740  // single-precision, and half-precision formats.
741  switch (I.getOpcode()) {
742  default:
743  break;
744  case Instruction::FPToSI:
745  case Instruction::FPToUI:
746  case Instruction::SIToFP:
747  case Instruction::UIToFP:
748  case Instruction::FPTrunc:
749  case Instruction::FPExt:
750  return !ST->hasFPARMv8Base();
751  }
752 
753  // FIXME: Unfortunately the approach of checking the Operation Action does
754  // not catch all cases of Legalization that use library calls. Our
755  // Legalization step categorizes some transformations into library calls as
756  // Custom, Expand or even Legal when doing type legalization. So for now
757  // we have to special case for instance the SDIV of 64bit integers and the
758  // use of floating point emulation.
759  if (VT.isInteger() && VT.getSizeInBits() >= 64) {
760  switch (ISD) {
761  default:
762  break;
763  case ISD::SDIV:
764  case ISD::UDIV:
765  case ISD::SREM:
766  case ISD::UREM:
767  case ISD::SDIVREM:
768  case ISD::UDIVREM:
769  return true;
770  }
771  }
772 
773  // Assume all other non-float operations are supported.
774  if (!VT.isFloatingPoint())
775  return false;
776 
777  // We'll need a library call to handle most floats when using soft.
778  if (TLI->useSoftFloat()) {
779  switch (I.getOpcode()) {
780  default:
781  return true;
782  case Instruction::Alloca:
783  case Instruction::Load:
784  case Instruction::Store:
785  case Instruction::Select:
786  case Instruction::PHI:
787  return false;
788  }
789  }
790 
791  // We'll need a libcall to perform double precision operations on a single
792  // precision only FPU.
793  if (I.getType()->isDoubleTy() && !ST->hasFP64())
794  return true;
795 
796  // Likewise for half precision arithmetic.
797  if (I.getType()->isHalfTy() && !ST->hasFullFP16())
798  return true;
799 
800  return false;
801  };
802 
803  auto IsHardwareLoopIntrinsic = [](Instruction &I) {
804  if (auto *Call = dyn_cast<IntrinsicInst>(&I)) {
805  switch (Call->getIntrinsicID()) {
806  default:
807  break;
808  case Intrinsic::set_loop_iterations:
809  case Intrinsic::loop_decrement:
810  case Intrinsic::loop_decrement_reg:
811  return true;
812  }
813  }
814  return false;
815  };
816 
817  // Scan the instructions to see if there's any that we know will turn into a
818  // call or if this loop is already a low-overhead loop.
819  auto ScanLoop = [&](Loop *L) {
820  for (auto *BB : L->getBlocks()) {
821  for (auto &I : *BB) {
822  if (MaybeCall(I) || IsHardwareLoopIntrinsic(I))
823  return false;
824  }
825  }
826  return true;
827  };
828 
829  // Visit inner loops.
830  for (auto Inner : *L)
831  if (!ScanLoop(Inner))
832  return false;
833 
834  if (!ScanLoop(L))
835  return false;
836 
837  // TODO: Check whether the trip count calculation is expensive. If L is the
838  // inner loop but we know it has a low trip count, calculating that trip
839  // count (in the parent loop) may be detrimental.
840 
841  LLVMContext &C = L->getHeader()->getContext();
842  HWLoopInfo.CounterInReg = true;
843  HWLoopInfo.IsNestingLegal = false;
844  HWLoopInfo.CountType = Type::getInt32Ty(C);
845  HWLoopInfo.LoopDecrement = ConstantInt::get(HWLoopInfo.CountType, 1);
846  return true;
847 }
848 
851  // Only currently enable these preferences for M-Class cores.
852  if (!ST->isMClass())
854 
855  // Disable loop unrolling for Oz and Os.
856  UP.OptSizeThreshold = 0;
858  if (L->getHeader()->getParent()->hasOptSize())
859  return;
860 
861  // Only enable on Thumb-2 targets.
862  if (!ST->isThumb2())
863  return;
864 
865  SmallVector<BasicBlock*, 4> ExitingBlocks;
866  L->getExitingBlocks(ExitingBlocks);
867  LLVM_DEBUG(dbgs() << "Loop has:\n"
868  << "Blocks: " << L->getNumBlocks() << "\n"
869  << "Exit blocks: " << ExitingBlocks.size() << "\n");
870 
871  // Only allow another exit other than the latch. This acts as an early exit
872  // as it mirrors the profitability calculation of the runtime unroller.
873  if (ExitingBlocks.size() > 2)
874  return;
875 
876  // Limit the CFG of the loop body for targets with a branch predictor.
877  // Allowing 4 blocks permits if-then-else diamonds in the body.
878  if (ST->hasBranchPredictor() && L->getNumBlocks() > 4)
879  return;
880 
881  // Scan the loop: don't unroll loops with calls as this could prevent
882  // inlining.
883  unsigned Cost = 0;
884  for (auto *BB : L->getBlocks()) {
885  for (auto &I : *BB) {
886  if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
887  ImmutableCallSite CS(&I);
888  if (const Function *F = CS.getCalledFunction()) {
889  if (!isLoweredToCall(F))
890  continue;
891  }
892  return;
893  }
894  SmallVector<const Value*, 4> Operands(I.value_op_begin(),
895  I.value_op_end());
896  Cost += getUserCost(&I, Operands);
897  }
898  }
899 
900  LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
901 
902  UP.Partial = true;
903  UP.Runtime = true;
904  UP.UpperBound = true;
905  UP.UnrollRemainder = true;
907  UP.UnrollAndJam = true;
909 
910  // Force unrolling small loops can be very useful because of the branch
911  // taken cost of the backedge.
912  if (Cost < 12)
913  UP.Force = true;
914 }
Type * getVectorElementType() const
Definition: Type.h:371
uint64_t CallInst * C
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
bool isIntrinsic() const
isIntrinsic - Returns true if the function&#39;s name starts with "llvm.".
Definition: Function.h:198
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I=nullptr)
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >())
Definition: BasicTTIImpl.h:581
static cl::opt< bool > DisableLowOverheadLoops("disable-arm-loloops", cl::Hidden, cl::init(true), cl::desc("Disable the generation of low-overhead loops"))
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1562
GCNRegPressure max(const GCNRegPressure &P1, const GCNRegPressure &P2)
bool isThumb() const
Definition: ARMSubtarget.h:749
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Cost tables and simple lookup functions.
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:391
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:614
unsigned getNumInterleavedAccesses(VectorType *VecTy, const DataLayout &DL) const
Returns the number of interleaved accesses that will be generated when lowering accesses of the given...
int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I=nullptr)
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:256
bool hasBranchPredictor() const
Definition: ARMSubtarget.h:663
int getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info=TTI::OK_AnyValue, TTI::OperandValueKind Op2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value *> Args=ArrayRef< const Value *>())
The main scalar evolution driver.
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold, but used for partial/runtime unrolling (set to UINT_MAX to disable).
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
unsigned getSourceAlignment() const
static uint64_t round(uint64_t Acc, uint64_t Input)
Definition: xxhash.cpp:57
A cache of @llvm.assume calls within a function.
unsigned getSourceAddressSpace() const
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:720
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
Type Conversion Cost Table.
Definition: CostTable.h:44
FunTy * getCalledFunction() const
Return the function being called if this is a direct call, otherwise return null (if it&#39;s an indirect...
Definition: CallSite.h:111
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:229
Value * getLength() const
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Cost Table Entry.
Definition: CostTable.h:24
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1508
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, bool AllowOverlap, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
bool isLoweredToCall(const Function *F)
bool isLegalInterleavedAccessType(VectorType *VecTy, const DataLayout &DL) const
Returns true if VecTy is a legal interleaved access type.
const FeatureBitset & getFeatureBits() const
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
Definition: APInt.h:368
APInt getUnsignedRangeMax(const SCEV *S)
Determine the max of the unsigned range for a particular SCEV.
int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace, const Instruction *I=nullptr)
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:196
unsigned getDestAlignment() const
const TypeConversionCostTblEntry * ConvertCostTableLookup(ArrayRef< TypeConversionCostTblEntry > Tbl, int ISD, MVT Dst, MVT Src)
Find in type conversion cost table, TypeTy must be comparable to CompareTy by ==. ...
Definition: CostTable.h:54
This file implements a class to represent arbitrary precision integral constant values and operations...
BlockT * getHeader() const
Definition: LoopInfo.h:102
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1532
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I)
Definition: BasicTTIImpl.h:785
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine...
int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1574
unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, const Instruction *I=nullptr)
Definition: BasicTTIImpl.h:647
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
bool hasV6T2Ops() const
Definition: ARMSubtarget.h:569
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
Selects elements from the corresponding lane of either source operand.
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:137
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:223
Reverse the order of the vector.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return &#39;this&#39;.
Definition: Type.h:303
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:363
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
Definition: BasicTTIImpl.h:430
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:168
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:395
const SCEV * getOne(Type *Ty)
Return a SCEV for the constant 1 of a specific type.
bool useSoftFloat() const override
Container class for subtarget features.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond=false, bool UseMaskForGaps=false)
Definition: BasicTTIImpl.h:863
bool isMClass() const
Definition: ARMSubtarget.h:754
bool isThumbImmShiftedVal(unsigned V)
isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit im...
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
const SCEV * getAddExpr(SmallVectorImpl< const SCEV *> &Ops, SCEV::NoWrapFlags Flags=SCEV::FlagAnyWrap, unsigned Depth=0)
Get a canonical add expression, or something simpler if possible.
unsigned getUserCost(const User *U, ArrayRef< const Value * > Operands)
bool isHalfTy() const
Return true if this is &#39;half&#39;, a 16-bit IEEE fp type.
Definition: Type.h:143
bool hasSlowLoadDSubregister() const
Definition: ARMSubtarget.h:650
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
bool hasVFP2Base() const
Definition: ARMSubtarget.h:603
Attributes of a target dependent hardware loop.
static double log2(double V)
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
void getExitingBlocks(SmallVectorImpl< BlockT *> &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
Definition: LoopInfoImpl.h:34
Extended Value Type.
Definition: ValueTypes.h:33
size_t size() const
Definition: SmallVector.h:52
const TargetMachine & getTargetMachine() const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
OperandValueProperties
Additional properties of an operand&#39;s values.
unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp)
Definition: BasicTTIImpl.h:628
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
This is the shared class of boolean and integer constants.
Definition: Constants.h:83
Type * getType() const
Return the LLVM type of this SCEV expression.
bool hasFP64() const
Definition: ARMSubtarget.h:636
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:606
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type...
Definition: Type.cpp:129
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Provides information about what library functions are available for the current target.
AddressSpace
Definition: NVPTXBaseInfo.h:21
int getAddressComputationCost(Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
bool hasNEON() const
Definition: ARMSubtarget.h:607
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
unsigned DefaultUnrollRuntimeCount
Default unroll count for loops with run-time trip count.
This class wraps the llvm.memcpy intrinsic.
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:631
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
Definition: Function.h:193
virtual const TargetSubtargetInfo * getSubtargetImpl(const Function &) const
Virtual method implemented by subclasses that returns a reference to that target&#39;s TargetSubtargetInf...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
unsigned getVectorNumElements() const
Definition: DerivedTypes.h:535
Class for arbitrary precision integers.
Definition: APInt.h:69
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
uint64_t getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:601
const CostTblEntry * CostTableLookup(ArrayRef< CostTblEntry > Tbl, int ISD, MVT Ty)
Find in cost table, TypeTy must be comparable to CompareTy by ==.
Definition: CostTable.h:31
bool isThumb2() const
Definition: ARMSubtarget.h:752
unsigned getNumBlocks() const
Get the number of blocks in this loop in constant time.
Definition: LoopInfo.h:165
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
int getMemcpyCost(const Instruction *I)
unsigned getDestAddressSpace() const
This class represents an analyzed expression in the program.
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:175
unsigned getIntegerBitWidth() const
Definition: DerivedTypes.h:97
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:467
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value...
Definition: APInt.h:481
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:151
Parameters that control the generic loop unrolling transformation.
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable)...
static VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
Definition: Type.cpp:605
StringRef getName() const
Return a constant reference to the value&#39;s name.
Definition: Value.cpp:214
Establish a view to a call site for examination.
Definition: CallSite.h:897
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
int getIntImmCost(const APInt &Imm, Type *Ty)
#define I(x, y, z)
Definition: MD5.cpp:58
bool hasLOB() const
Definition: ARMSubtarget.h:614
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:611
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:332
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Definition: BasicTTIImpl.h:825
uint32_t Size
Definition: Profile.cpp:46
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP)
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
const SCEV * getBackedgeTakenCount(const Loop *L)
If the specified loop has a predictable backedge-taken count, return it, otherwise return a SCEVCould...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Definition: Type.cpp:114
int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
bool hasMVEIntegerOps() const
Definition: ARMSubtarget.h:580
Broadcast element 0 to all other elements.
int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
bool UpperBound
Allow using trip count upper bound to unroll loops.
IRTranslator LLVM IR MI
OperandValueKind
Additional information about an operand&#39;s possible values.
Conversion operators.
Definition: ISDOpcodes.h:489
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
#define LLVM_DEBUG(X)
Definition: Debug.h:122
bool isDoubleTy() const
Return true if this is &#39;double&#39;, a 64-bit IEEE fp type.
Definition: Type.h:149
bool hasLoopInvariantBackedgeTakenCount(const Loop *L)
Return true if the specified loop has an analyzable loop-invariant backedge-taken count...
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
const BasicBlock * getParent() const
Definition: Instruction.h:66
ShuffleKind
The various kinds of shuffle patterns for vector queries.
bool hasFullFP16() const
Definition: ARMSubtarget.h:674