LLVM 17.0.0git
Public Member Functions | List of all members
llvm::ARMTTIImpl Class Reference

#include "Target/ARM/ARMTargetTransformInfo.h"

Inheritance diagram for llvm::ARMTTIImpl:
Inheritance graph
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Public Member Functions

 ARMTTIImpl (const ARMBaseTargetMachine *TM, const Function &F)
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
bool enableInterleavedAccessVectorization ()
 
TTI::AddressingModeKind getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
 
bool isFPVectorizationPotentiallyUnsafe ()
 Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv7.
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
Scalar TTI Implementations
InstructionCost getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty)
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
 
Vector TTI Implementations
unsigned getNumberOfRegisters (unsigned ClassID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMaxInterleaveFactor (ElementCount VF)
 
bool isProfitableLSRChainElement (Instruction *I)
 
bool isLegalMaskedLoad (Type *DataTy, Align Alignment)
 
bool isLegalMaskedStore (Type *DataTy, Align Alignment)
 
bool forceScalarizeMaskedGather (VectorType *VTy, Align Alignment)
 
bool forceScalarizeMaskedScatter (VectorType *VTy, Align Alignment)
 
bool isLegalMaskedGather (Type *Ty, Align Alignment)
 
bool isLegalMaskedScatter (Type *Ty, Align Alignment)
 
InstructionCost getMemcpyCost (const Instruction *I)
 
int getNumMemOps (const IntrinsicInst *I) const
 Given a memcpy/memset/memmove instruction, return the number of memory operations performed, via querying findOptimalMemOpLowering.
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
 
bool preferInLoopReduction (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
 
InstructionCost getAddressComputationCost (Type *Val, ScalarEvolution *SE, const SCEV *Ptr)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *ValTy, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *ValTy, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMulAccReductionCost (bool IsUnsigned, Type *ResTy, VectorType *ValTy, TTI::TargetCostKind CostKind)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
 getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.
 
bool maybeLoweredToCall (Instruction &I)
 
bool isLoweredToCall (const Function *F)
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
 
bool preferPredicateOverEpilogue (TailFoldingInfo *TFI)
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
TailFoldingStyle getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true) const
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
bool shouldBuildLookupTablesForConstant (Constant *C) const
 
bool hasArmWideBranch (bool Thumb) const
 
- Public Member Functions inherited from llvm::BasicTTIImplBase< ARMTTIImpl >
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
 
bool hasBranchDivergence ()
 
bool isSourceOfDivergence (const Value *V)
 
bool isAlwaysUniform (const Value *V)
 
bool isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getFlatAddressSpace ()
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
bool isSingleThreaded () const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLegalAddImmediate (int64_t imm)
 
bool isLegalICmpImmediate (int64_t imm)
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr)
 
unsigned getStoreMinimumVF (unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode M, Type *Ty, const DataLayout &DL) const
 
bool isLSRCostLess (TTI::LSRCost C1, TTI::LSRCost C2)
 
bool isNumRegsMajorCostOfLSR ()
 
bool isProfitableLSRChainElement (Instruction *I)
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)
 
bool isTruncateFree (Type *Ty1, Type *Ty2)
 
bool isProfitableToHoist (Instruction *I)
 
bool useAA () const
 
bool isTypeLegal (Type *Ty)
 
unsigned getRegUsageForType (Type *Ty)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JumpTableSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)
 
bool shouldBuildLookupTables ()
 
bool shouldBuildRelLookupTables () const
 
bool haveFastSqrt (Type *Ty)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty)
 
InstructionCost getFPOpCost (Type *Ty)
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB)
 
int getInlinerVectorBonusPercent () const
 
void getUnrollingPreferences (Loop *L, ScalarEvolution &SE, TTI::UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)
 
void getPeelingPreferences (Loop *L, ScalarEvolution &SE, TTI::PeelingPreferences &PP)
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)
 
bool preferPredicateOverEpilogue (TailFoldingInfo *TFI)
 
TailFoldingStyle getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true)
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II)
 
std::optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)
 
virtual std::optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
virtual std::optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
virtual unsigned getCacheLineSize () const
 
virtual unsigned getPrefetchDistance () const
 
virtual unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
virtual unsigned getMaxPrefetchIterationsAhead () const
 
virtual bool enableWritePrefetching () const
 
virtual bool shouldPrefetchAddressSpace (unsigned AS) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
std::optional< unsigned > getMaxVScale () const
 
std::optional< unsigned > getVScaleForTuning () const
 
bool isVScaleKnownToBeAPowerOfTwo () const
 
InstructionCost getScalarizationOverhead (VectorType *InTy, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
 Estimate the overhead of scalarizing an instruction.
 
InstructionCost getScalarizationOverhead (VectorType *InTy, bool Insert, bool Extract, TTI::TargetCostKind CostKind)
 Helper wrapper for the DemandedElts variant of getScalarizationOverhead.
 
InstructionCost getScalarizationOverhead (VectorType *RetTy, ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Estimate the overhead of scalarizing the inputs and outputs of an instruction, with return type RetTy and arguments Args of type Tys.
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Estimate the overhead of scalarizing an instructions unique non-constant operands.
 
std::pair< InstructionCost, MVT > getTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type.
 
unsigned getMaxInterleaveFactor (ElementCount VF)
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
 
TTI::ShuffleKind improveShuffleKindFromMask (TTI::ShuffleKind Kind, ArrayRef< int > Mask) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt)
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1)
 
InstructionCost getVectorInstrCost (const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index)
 
InstructionCost getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo={TTI::OK_AnyValue, TTI::OP_None}, const Instruction *I=nullptr)
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *DataTy, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
 
InstructionCost getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on arguments.
 
InstructionCost getTypeBasedIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
 Get intrinsic cost based on argument types.
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)
 Compute a cost of the given call instruction.
 
unsigned getNumberOfParts (Type *Tp)
 
InstructionCost getAddressComputationCost (Type *Ty, ScalarEvolution *, const SCEV *)
 
InstructionCost getTreeReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate arithmetic and shuffle op costs for reduction intrinsics.
 
InstructionCost getOrderedReductionCost (unsigned Opcode, VectorType *Ty, TTI::TargetCostKind CostKind)
 Try to calculate the cost of performing strict (in-order) reductions, which involves doing a sequence of floating point additions in lane order, starting with an initial value.
 
InstructionCost getArithmeticReductionCost (unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMinMaxReductionCost (VectorType *Ty, VectorType *CondTy, bool IsUnsigned, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 Try to calculate op costs for min/max reduction operations.
 
InstructionCost getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind)
 
InstructionCost getMulAccReductionCost (bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind)
 
InstructionCost getVectorSplitCost ()
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
InstructionCost getPointersChainCost (ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
 
InstructionCost getInstructionCost (const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
 
bool isExpensiveToSpeculativelyExecute (const Instruction *I)
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
- Public Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const TargetTransformInfoImplBase &Arg)=default
 
 TargetTransformInfoImplBase (TargetTransformInfoImplBase &&Arg)
 
const DataLayout & getDataLayout () const
 
InstructionCost getGEPCost (Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind) const
 
unsigned getEstimatedNumberOfCaseClusters (const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
 
unsigned getInliningThresholdMultiplier () const
 
unsigned adjustInliningThreshold (const CallBase *CB) const
 
int getInlinerVectorBonusPercent () const
 
InstructionCost getMemcpyCost (const Instruction *I) const
 
BranchProbability getPredictableBranchThreshold () const
 
bool hasBranchDivergence () const
 
bool isSourceOfDivergence (const Value *V) const
 
bool isAlwaysUniform (const Value *V) const
 
bool isValidAddrSpaceCast (unsigned FromAS, unsigned ToAS) const
 
unsigned getFlatAddressSpace () const
 
bool collectFlatAddressOperands (SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
 
bool isNoopAddrSpaceCast (unsigned, unsigned) const
 
bool canHaveNonUndefGlobalInitializerInAddressSpace (unsigned AS) const
 
unsigned getAssumedAddrSpace (const Value *V) const
 
bool isSingleThreaded () const
 
std::pair< const Value *, unsigned > getPredicatedAddrSpace (const Value *V) const
 
Value * rewriteIntrinsicWithAddressSpace (IntrinsicInst *II, Value *OldV, Value *NewV) const
 
bool isLoweredToCall (const Function *F) const
 
bool isHardwareLoopProfitable (Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
 
bool preferPredicateOverEpilogue (TailFoldingInfo *TFI) const
 
TailFoldingStyle getPreferredTailFoldingStyle (bool IVUpdateMayOverflow=true) const
 
std::optional< Instruction * > instCombineIntrinsic (InstCombiner &IC, IntrinsicInst &II) const
 
std::optional< Value * > simplifyDemandedUseBitsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
 
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic (InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
 
void getUnrollingPreferences (Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
 
void getPeelingPreferences (Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
 
bool isLegalAddImmediate (int64_t Imm) const
 
bool isLegalICmpImmediate (int64_t Imm) const
 
bool isLegalAddressingMode (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr) const
 
bool isLSRCostLess (const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
 
bool isNumRegsMajorCostOfLSR () const
 
bool isProfitableLSRChainElement (Instruction *I) const
 
bool canMacroFuseCmp () const
 
bool canSaveCmp (Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
 
TTI::AddressingModeKind getPreferredAddressingMode (const Loop *L, ScalarEvolution *SE) const
 
bool isLegalMaskedStore (Type *DataType, Align Alignment) const
 
bool isLegalMaskedLoad (Type *DataType, Align Alignment) const
 
bool isLegalNTStore (Type *DataType, Align Alignment) const
 
bool isLegalNTLoad (Type *DataType, Align Alignment) const
 
bool isLegalBroadcastLoad (Type *ElementTy, ElementCount NumElements) const
 
bool isLegalMaskedScatter (Type *DataType, Align Alignment) const
 
bool isLegalMaskedGather (Type *DataType, Align Alignment) const
 
bool forceScalarizeMaskedGather (VectorType *DataType, Align Alignment) const
 
bool forceScalarizeMaskedScatter (VectorType *DataType, Align Alignment) const
 
bool isLegalMaskedCompressStore (Type *DataType) const
 
bool isLegalAltInstr (VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
 
bool isLegalMaskedExpandLoad (Type *DataType) const
 
bool enableOrderedReductions () const
 
bool hasDivRemOp (Type *DataType, bool IsSigned) const
 
bool hasVolatileVariant (Instruction *I, unsigned AddrSpace) const
 
bool prefersVectorizedAddressing () const
 
InstructionCost getScalingFactorCost (Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
 
bool LSRWithInstrQueries () const
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const
 
bool isProfitableToHoist (Instruction *I) const
 
bool useAA () const
 
bool isTypeLegal (Type *Ty) const
 
unsigned getRegUsageForType (Type *Ty) const
 
bool shouldBuildLookupTables () const
 
bool shouldBuildLookupTablesForConstant (Constant *C) const
 
bool shouldBuildRelLookupTables () const
 
bool useColdCCForColdCall (Function &F) const
 
InstructionCost getScalarizationOverhead (VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
 
InstructionCost getOperandsScalarizationOverhead (ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
bool supportsEfficientVectorElementLoadStore () const
 
bool supportsTailCalls () const
 
bool supportsTailCallFor (const CallBase *CB) const
 
bool enableAggressiveInterleaving (bool LoopHasReductions) const
 
TTI::MemCmpExpansionOptions enableMemCmpExpansion (bool OptSize, bool IsZeroCmp) const
 
bool enableSelectOptimize () const
 
bool enableInterleavedAccessVectorization () const
 
bool enableMaskedInterleavedAccessVectorization () const
 
bool isFPVectorizationPotentiallyUnsafe () const
 
bool allowsMisalignedMemoryAccesses (LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
 
TTI::PopcntSupportKind getPopcntSupport (unsigned IntTyWidthInBit) const
 
bool haveFastSqrt (Type *Ty) const
 
bool isExpensiveToSpeculativelyExecute (const Instruction *I)
 
bool isFCmpOrdCheaperThanFCmpZero (Type *Ty) const
 
InstructionCost getFPOpCost (Type *Ty) const
 
InstructionCost getIntImmCodeSizeCost (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
 
InstructionCost getIntImmCost (const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getIntImmCostInst (unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
 
InstructionCost getIntImmCostIntrin (Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfRegisters (unsigned ClassID) const
 
unsigned getRegisterClassForType (bool Vector, Type *Ty=nullptr) const
 
const char * getRegisterClassName (unsigned ClassID) const
 
TypeSize getRegisterBitWidth (TargetTransformInfo::RegisterKind K) const
 
unsigned getMinVectorRegisterBitWidth () const
 
std::optional< unsigned > getMaxVScale () const
 
std::optional< unsigned > getVScaleForTuning () const
 
bool isVScaleKnownToBeAPowerOfTwo () const
 
bool shouldMaximizeVectorBandwidth (TargetTransformInfo::RegisterKind K) const
 
ElementCount getMinimumVF (unsigned ElemWidth, bool IsScalable) const
 
unsigned getMaximumVF (unsigned ElemWidth, unsigned Opcode) const
 
unsigned getStoreMinimumVF (unsigned VF, Type *, Type *) const
 
bool shouldConsiderAddressTypePromotion (const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
 
unsigned getCacheLineSize () const
 
std::optional< unsigned > getCacheSize (TargetTransformInfo::CacheLevel Level) const
 
std::optional< unsigned > getCacheAssociativity (TargetTransformInfo::CacheLevel Level) const
 
unsigned getPrefetchDistance () const
 
unsigned getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
 
unsigned getMaxPrefetchIterationsAhead () const
 
bool enableWritePrefetching () const
 
bool shouldPrefetchAddressSpace (unsigned AS) const
 
unsigned getMaxInterleaveFactor (ElementCount VF) const
 
InstructionCost getArithmeticInstrCost (unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
 
InstructionCost getShuffleCost (TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt) const
 
InstructionCost getCastInstrCost (unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getExtractWithExtendCost (unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
 
InstructionCost getCFInstrCost (unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
InstructionCost getCmpSelInstrCost (unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getVectorInstrCost (unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1) const
 
InstructionCost getVectorInstrCost (const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
 
unsigned getReplicationShuffleCost (Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
 
InstructionCost getMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
 
InstructionCost getVPMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
 
InstructionCost getMaskedMemoryOpCost (unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
 
InstructionCost getGatherScatterOpCost (unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
 
unsigned getInterleavedMemoryOpCost (unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
 
InstructionCost getIntrinsicInstrCost (const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
 
InstructionCost getCallInstrCost (Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
 
unsigned getNumberOfParts (Type *Tp) const
 
InstructionCost getAddressComputationCost (Type *Tp, ScalarEvolution *, const SCEV *) const
 
InstructionCost getArithmeticReductionCost (unsigned, VectorType *, std::optional< FastMathFlags > FMF, TTI::TargetCostKind) const
 
InstructionCost getMinMaxReductionCost (VectorType *, VectorType *, bool, FastMathFlags, TTI::TargetCostKind) const
 
InstructionCost getExtendedReductionCost (unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
 
InstructionCost getMulAccReductionCost (bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
 
InstructionCost getCostOfKeepingLiveOverCall (ArrayRef< Type * > Tys) const
 
bool getTgtMemIntrinsic (IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
 
unsigned getAtomicMemIntrinsicMaxElementSize () const
 
Value * getOrCreateResultFromMemIntrinsic (IntrinsicInst *Inst, Type *ExpectedType) const
 
Type * getMemcpyLoopLoweringType (LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize) const
 
void getMemcpyLoopResidualLoweringType (SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize) const
 
bool areInlineCompatible (const Function *Caller, const Function *Callee) const
 
bool areTypesABICompatible (const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
 
bool isIndexedLoadLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
bool isIndexedStoreLegal (TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
 
unsigned getLoadStoreVecRegBitWidth (unsigned AddrSpace) const
 
bool isLegalToVectorizeLoad (LoadInst *LI) const
 
bool isLegalToVectorizeStore (StoreInst *SI) const
 
bool isLegalToVectorizeLoadChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeStoreChain (unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
 
bool isLegalToVectorizeReduction (const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
 
bool isElementTypeLegalForScalableVector (Type *Ty) const
 
unsigned getLoadVectorFactor (unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
unsigned getStoreVectorFactor (unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
 
bool preferInLoopReduction (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferPredicatedReductionSelect (unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
 
bool preferEpilogueVectorization () const
 
bool shouldExpandReduction (const IntrinsicInst *II) const
 
unsigned getGISelRematGlobalCost () const
 
unsigned getMinTripCountTailFoldingThreshold () const
 
bool supportsScalableVectors () const
 
bool enableScalableVectorization () const
 
bool hasActiveVectorLength (unsigned Opcode, Type *DataType, Align Alignment) const
 
TargetTransformInfo::VPLegalization getVPLegalizationStrategy (const VPIntrinsic &PI) const
 
bool hasArmWideBranch (bool) const
 
unsigned getMaxNumArgs () const
 

Additional Inherited Members

- Protected Types inherited from llvm::TargetTransformInfoImplBase
typedef TargetTransformInfo TTI
 
- Protected Member Functions inherited from llvm::BasicTTIImplBase< ARMTTIImpl >
 BasicTTIImplBase (const TargetMachine *TM, const DataLayout &DL)
 
virtual ~BasicTTIImplBase ()=default
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplCRTPBase< T >
 TargetTransformInfoImplCRTPBase (const DataLayout &DL)
 
- Protected Member Functions inherited from llvm::TargetTransformInfoImplBase
 TargetTransformInfoImplBase (const DataLayout &DL)
 
unsigned minRequiredElementSize (const Value *Val, bool &isSigned) const
 
bool isStridedAccess (const SCEV *Ptr) const
 
const SCEVConstant * getConstantStrideStep (ScalarEvolution *SE, const SCEV *Ptr) const
 
bool isConstantStridedAccessLessThan (ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
 
- Protected Attributes inherited from llvm::BasicTTIImplBase< ARMTTIImpl >
const DataLayout & DL
 
- Protected Attributes inherited from llvm::TargetTransformInfoImplBase
const DataLayout & DL
 

Detailed Description

Definition at line 57 of file ARMTargetTransformInfo.h.

Constructor & Destructor Documentation

◆ ARMTTIImpl()

llvm::ARMTTIImpl::ARMTTIImpl ( const ARMBaseTargetMachine *  TM,
const Function &  F 
)
inlineexplicit

Definition at line 103 of file ARMTargetTransformInfo.h.

Member Function Documentation

◆ areInlineCompatible()

bool ARMTTIImpl::areInlineCompatible ( const Function *  Caller,
const Function *  Callee 
) const

Definition at line 87 of file ARMTargetTransformInfo.cpp.

References llvm::TargetLoweringBase::getTargetMachine(), and TM.

◆ enableInterleavedAccessVectorization()

bool llvm::ARMTTIImpl::enableInterleavedAccessVectorization ( )
inline

Definition at line 110 of file ARMTargetTransformInfo.h.

◆ forceScalarizeMaskedGather()

bool llvm::ARMTTIImpl::forceScalarizeMaskedGather ( VectorType *  VTy,
Align  Alignment 
)
inline

Definition at line 193 of file ARMTargetTransformInfo.h.

Referenced by forceScalarizeMaskedScatter().

◆ forceScalarizeMaskedScatter()

bool llvm::ARMTTIImpl::forceScalarizeMaskedScatter ( VectorType *  VTy,
Align  Alignment 
)
inline

Definition at line 201 of file ARMTargetTransformInfo.h.

References forceScalarizeMaskedGather().

◆ getAddressComputationCost()

InstructionCost ARMTTIImpl::getAddressComputationCost ( Type *  Val,
ScalarEvolution *  SE,
const SCEV *  Ptr 
)

Definition at line 1062 of file ARMTargetTransformInfo.cpp.

References llvm::BasicTTIImplBase< ARMTTIImpl >::getAddressComputationCost(), llvm::TargetTransformInfoImplBase::isConstantStridedAccessLessThan(), llvm::Type::isVectorTy(), and Ptr.

◆ getArithmeticInstrCost()

InstructionCost ARMTTIImpl::getArithmeticInstrCost ( unsigned  Opcode,
Type *  Ty,
TTI::TargetCostKind  CostKind,
TTI::OperandValueInfo  Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo  Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef< const Value * >  Args = ArrayRef<const Value *>(),
const Instruction *  CxtI = nullptr 
)

Definition at line 1316 of file ARMTargetTransformInfo.cpp.

References llvm::ISD::AND, CostKind, llvm::CostTableLookup(), getArithmeticInstrCost(), llvm::BasicTTIImplBase< ARMTTIImpl >::getArithmeticInstrCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::BasicTTIImplBase< ARMTTIImpl >::getScalarizationOverhead(), llvm::Type::getScalarType(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::Value::hasOneUse(), if(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::TargetTransformInfo::OperandValueInfo::isConstant(), llvm::Type::isIntegerTy(), llvm::TargetLoweringBase::isOperationLegalOrCustomOrPromote(), llvm::Instruction::isShift(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetTransformInfo::OperandValueInfo::isUniform(), llvm::Type::isVectorTy(), llvm::ISD::OR, llvm::ISD::SDIV, llvm::ISD::SREM, llvm::TargetTransformInfo::TCK_CodeSize, llvm::ISD::UDIV, llvm::ISD::UREM, llvm::Instruction::user_back(), and llvm::ISD::XOR.

Referenced by getArithmeticInstrCost().

◆ getArithmeticReductionCost()

InstructionCost ARMTTIImpl::getArithmeticReductionCost ( unsigned  Opcode,
VectorType *  ValTy,
std::optional< FastMathFlags >  FMF,
TTI::TargetCostKind  CostKind 
)

Definition at line 1668 of file ARMTargetTransformInfo.cpp.

References llvm::ISD::ADD, CostKind, llvm::CostTableLookup(), llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::BasicTTIImplBase< ARMTTIImpl >::getArithmeticReductionCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::EVT::isSimple(), and llvm::TargetTransformInfo::requiresOrderedReduction().

◆ getCastInstrCost()

InstructionCost ARMTTIImpl::getCastInstrCost ( unsigned  Opcode,
Type *  Dst,
Type *  Src,
TTI::CastContextHint  CCH,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 472 of file ARMTargetTransformInfo.cpp.

References llvm::ISD::ADD, assert(), llvm::ConvertCostTableLookup(), CostKind, llvm::CostTableLookup(), llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::BasicTTIImplBase< ARMTTIImpl >::getCallInstrCost(), llvm::BasicTTIImplBase< ARMTTIImpl >::getCastInstrCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ARMSubtarget::hasVFP2Base(), I, llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::TargetTransformInfo::Masked, llvm::ISD::MUL, llvm::TargetTransformInfo::Normal, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::SUB, llvm::TargetTransformInfo::TCK_RecipThroughput, llvm::ISD::TRUNCATE, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.

◆ getCFInstrCost()

InstructionCost ARMTTIImpl::getCFInstrCost ( unsigned  Opcode,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 458 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::getCFInstrCost(), I, and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getCmpSelInstrCost()

InstructionCost ARMTTIImpl::getCmpSelInstrCost ( unsigned  Opcode,
Type *  ValTy,
Type *  CondTy,
CmpInst::Predicate  VecPred,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 915 of file ARMTargetTransformInfo.cpp.

References llvm::ConvertCostTableLookup(), CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::SelectPatternResult::Flavor, llvm::BasicTTIImplBase< ARMTTIImpl >::getCmpSelInstrCost(), getCmpSelInstrCost(), getIntrinsicInstrCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::FixedVectorType::getNumElements(), llvm::BasicTTIImplBase< ARMTTIImpl >::getScalarizationOverhead(), llvm::Type::getScalarType(), llvm::EVT::getSimpleVT(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::Value::hasOneUse(), I, llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::Type::isFPOrFPVectorTy(), llvm::Type::isIntegerTy(), llvm::Type::isIntOrIntVectorTy(), llvm::EVT::isSimple(), llvm::Type::isVectorTy(), LHS, llvm::CmpInst::makeCmpResultType(), llvm::matchSelectPattern(), RHS, llvm::ISD::SELECT, llvm::SPF_ABS, llvm::SPF_FMAXNUM, llvm::SPF_FMINNUM, llvm::SPF_SMAX, llvm::SPF_SMIN, llvm::SPF_UMAX, llvm::SPF_UMIN, llvm::TargetTransformInfo::TCC_Expensive, llvm::TargetTransformInfo::TCK_CodeSize, and llvm::Instruction::user_back().

Referenced by getCmpSelInstrCost().

◆ getExtendedReductionCost()

InstructionCost ARMTTIImpl::getExtendedReductionCost ( unsigned  Opcode,
bool  IsUnsigned,
Type *  ResTy,
VectorType *  ValTy,
FastMathFlags  FMF,
TTI::TargetCostKind  CostKind 
)

Definition at line 1692 of file ARMTargetTransformInfo.cpp.

References llvm::ISD::ADD, CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::BasicTTIImplBase< ARMTTIImpl >::getExtendedReductionCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::EVT::getSizeInBits(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), llvm::TargetLoweringBase::InstructionOpcodeToISD(), and llvm::EVT::isSimple().

◆ getGatherScatterOpCost()

InstructionCost ARMTTIImpl::getGatherScatterOpCost ( unsigned  Opcode,
Type *  DataTy,
const Value *  Ptr,
bool  VariableMask,
Align  Alignment,
TTI::TargetCostKind  CostKind,
const Instruction *  I = nullptr 
)

Definition at line 1563 of file ARMTargetTransformInfo.cpp.

References assert(), CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, EnableMaskedGatherScatters, GEP, llvm::BasicTTIImplBase< ARMTTIImpl >::getGatherScatterOpCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::BasicTTIImplBase< ARMTTIImpl >::getScalarizationOverhead(), llvm::DataLayout::getTypeAllocSize(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), I, llvm::Type::isVectorTy(), llvm::PatternMatch::match(), and Ptr.

◆ getInterleavedMemoryOpCost()

InstructionCost ARMTTIImpl::getInterleavedMemoryOpCost ( unsigned  Opcode,
Type *  VecTy,
unsigned  Factor,
ArrayRef< unsigned >  Indices,
Align  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind,
bool  UseMaskForCond = false,
bool  UseMaskForGaps = false 
)

Definition at line 1522 of file ARMTargetTransformInfo.cpp.

References assert(), CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::FixedVectorType::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::BasicTTIImplBase< ARMTTIImpl >::getInterleavedMemoryOpCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::ARMTargetLowering::getNumInterleavedAccesses(), llvm::Type::getScalarType(), llvm::DataLayout::getTypeSizeInBits(), llvm::Type::isIntOrIntVectorTy(), and llvm::ARMTargetLowering::isLegalInterleavedAccessType().

◆ getIntImmCodeSizeCost()

InstructionCost ARMTTIImpl::getIntImmCodeSizeCost ( unsigned  Opcode,
unsigned  Idx,
const APInt &  Imm,
Type *  Ty 
)

Definition at line 330 of file ARMTargetTransformInfo.cpp.

◆ getIntImmCost()

InstructionCost ARMTTIImpl::getIntImmCost ( const APInt &  Imm,
Type *  Ty,
TTI::TargetCostKind  CostKind 
)

Definition at line 295 of file ARMTargetTransformInfo.cpp.

References assert(), llvm::Type::getPrimitiveSizeInBits(), llvm::ARM_AM::getSOImmVal(), llvm::ARM_AM::getT2SOImmVal(), llvm::Type::isIntegerTy(), llvm::ARMSubtarget::isThumb2(), and llvm::ARM_AM::isThumbImmShiftedVal().

Referenced by getIntImmCostInst().

◆ getIntImmCostInst()

InstructionCost ARMTTIImpl::getIntImmCostInst ( unsigned  Opcode,
unsigned  Idx,
const APInt &  Imm,
Type *  Ty,
TTI::TargetCostKind  CostKind,
Instruction *  Inst = nullptr 
)

Definition at line 387 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::Type::getIntegerBitWidth(), getIntImmCost(), llvm::Value::hasOneUse(), llvm::ARMSubtarget::hasVFP2Base(), llvm::CmpInst::ICMP_SGT, llvm::CmpInst::ICMP_SLE, Idx, isFPSatMinMaxPattern(), isSSATMinMaxPattern(), llvm::ARMSubtarget::isThumb2(), and llvm::Value::user_begin().

◆ getIntrinsicInstrCost()

InstructionCost ARMTTIImpl::getIntrinsicInstrCost ( const IntrinsicCostAttributes &  ICA,
TTI::TargetCostKind  CostKind 
)

Definition at line 1754 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::IntrinsicCostAttributes::getArgTypes(), llvm::Type::getContext(), llvm::IntrinsicCostAttributes::getID(), llvm::Type::getIntNTy(), llvm::BasicTTIImplBase< ARMTTIImpl >::getIntrinsicInstrCost(), getIntrinsicInstrCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::IntrinsicCostAttributes::getReturnType(), llvm::EVT::getScalarSizeInBits(), llvm::Type::getScalarSizeInBits(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), and llvm::ARMSubtarget::hasVFP2Base().

Referenced by getCmpSelInstrCost(), and getIntrinsicInstrCost().

◆ getMaskedMemoryOpCost()

InstructionCost ARMTTIImpl::getMaskedMemoryOpCost ( unsigned  Opcode,
Type *  Src,
Align  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind 
)

Definition at line 1505 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::getMaskedMemoryOpCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), isLegalMaskedLoad(), and isLegalMaskedStore().

◆ getMaxInterleaveFactor()

unsigned llvm::ARMTTIImpl::getMaxInterleaveFactor ( ElementCount  VF)
inline

Definition at line 181 of file ARMTargetTransformInfo.h.

◆ getMemcpyCost()

InstructionCost ARMTTIImpl::getMemcpyCost ( const Instruction *  I)

Definition at line 1199 of file ARMTargetTransformInfo.cpp.

References getNumMemOps(), and I.

◆ getMemoryOpCost()

InstructionCost ARMTTIImpl::getMemoryOpCost ( unsigned  Opcode,
Type *  Src,
MaybeAlign  Alignment,
unsigned  AddressSpace,
TTI::TargetCostKind  CostKind,
TTI::OperandValueInfo  OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
const Instruction *  I = nullptr 
)

Definition at line 1457 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::BasicTTIImplBase< ARMTTIImpl >::getMemoryOpCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::FixedVectorType::getNumElements(), llvm::Type::getScalarType(), getType(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), I, llvm::Type::isFloatTy(), llvm::Type::isHalfTy(), and llvm::TargetTransformInfo::TCK_RecipThroughput.

◆ getMulAccReductionCost()

InstructionCost ARMTTIImpl::getMulAccReductionCost ( bool  IsUnsigned,
Type *  ResTy,
VectorType *  ValTy,
TTI::TargetCostKind  CostKind 
)

Definition at line 1727 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::BasicTTIImplBase< ARMTTIImpl >::getMulAccReductionCost(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::EVT::getSizeInBits(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::TargetLoweringBase::getValueType(), and llvm::EVT::isSimple().

◆ getNumberOfRegisters()

unsigned llvm::ARMTTIImpl::getNumberOfRegisters ( unsigned  ClassID) const
inline

Definition at line 150 of file ARMTargetTransformInfo.h.

References llvm::Vector.

◆ getNumMemOps()

int ARMTTIImpl::getNumMemOps ( const IntrinsicInst *  I) const

Given a memcpy/memset/memmove instruction, return the number of memory operations performed, via querying findOptimalMemOpLowering.

Returns -1 if a call is used.

Definition at line 1133 of file ARMTargetTransformInfo.cpp.

References llvm::CallingConv::C, llvm::MemOp::Copy(), F, llvm::TargetLoweringBase::getMaxStoresPerMemcpy(), llvm::TargetLoweringBase::getMaxStoresPerMemmove(), llvm::TargetLoweringBase::getMaxStoresPerMemset(), I, llvm_unreachable, llvm::MemOp::Set(), and Size.

Referenced by getMemcpyCost(), and maybeLoweredToCall().

◆ getPeelingPreferences()

void ARMTTIImpl::getPeelingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::PeelingPreferences &  PP 
)

Definition at line 2410 of file ARMTargetTransformInfo.cpp.

References llvm::BasicTTIImplBase< ARMTTIImpl >::getPeelingPreferences().

◆ getPreferredAddressingMode()

TTI::AddressingModeKind ARMTTIImpl::getPreferredAddressingMode ( const Loop *  L,
ScalarEvolution *  SE 
) const

Definition at line 106 of file ARMTargetTransformInfo.cpp.

References llvm::TargetTransformInfo::AMK_None, llvm::TargetTransformInfo::AMK_PostIndexed, llvm::TargetTransformInfo::AMK_PreIndexed, llvm::ARMSubtarget::isMClass(), and llvm::ARMSubtarget::isThumb2().

◆ getPreferredTailFoldingStyle()

TailFoldingStyle ARMTTIImpl::getPreferredTailFoldingStyle ( bool  IVUpdateMayOverflow = true) const

Definition at line 2297 of file ARMTargetTransformInfo.cpp.

References llvm::Data, llvm::DataWithoutLaneMask, and EnableTailPredication.

◆ getRegisterBitWidth()

TypeSize llvm::ARMTTIImpl::getRegisterBitWidth ( TargetTransformInfo::RegisterKind  K) const
inline

Definition at line 165 of file ARMTargetTransformInfo.h.

References llvm::TypeSize::getFixed(), llvm::TypeSize::getScalable(), llvm_unreachable, llvm::TargetTransformInfo::RGK_FixedWidthVector, llvm::TargetTransformInfo::RGK_ScalableVector, and llvm::TargetTransformInfo::RGK_Scalar.

◆ getScalingFactorCost()

InstructionCost ARMTTIImpl::getScalingFactorCost ( Type *  Ty,
GlobalValue *  BaseGV,
int64_t  BaseOffset,
bool  HasBaseReg,
int64_t  Scale,
unsigned  AddrSpace 
) const

getScalingFactorCost - Return the cost of the scaling used in addressing mode represented by AM.

If the AM is supported, the return value must be >= 0. If the AM is not supported, the return value must be negative.

Definition at line 2436 of file ARMTargetTransformInfo.cpp.

References llvm::TargetLoweringBase::AddrMode::BaseGV, llvm::TargetLoweringBase::AddrMode::BaseOffs, llvm::BasicTTIImplBase< ARMTTIImpl >::DL, llvm::TargetLoweringBase::AddrMode::HasBaseReg, llvm::BasicTTIImplBase< ARMTTIImpl >::isLegalAddressingMode(), and llvm::TargetLoweringBase::AddrMode::Scale.

◆ getShuffleCost()

InstructionCost ARMTTIImpl::getShuffleCost ( TTI::ShuffleKind  Kind,
VectorType *  Tp,
ArrayRef< int >  Mask,
TTI::TargetCostKind  CostKind,
int  Index,
VectorType *  SubTp,
ArrayRef< const Value * >  Args = std::nullopt 
)

Definition at line 1209 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::CostTableLookup(), llvm::ARMSubtarget::getMVEVectorCostFactor(), llvm::BasicTTIImplBase< ARMTTIImpl >::getShuffleCost(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::BasicTTIImplBase< ARMTTIImpl >::improveShuffleKindFromMask(), llvm::Type::isVectorTy(), llvm::isVREVMask(), llvm::TargetTransformInfo::SK_Broadcast, llvm::TargetTransformInfo::SK_Reverse, llvm::TargetTransformInfo::SK_Select, llvm::TargetTransformInfo::TCK_RecipThroughput, and llvm::ISD::VECTOR_SHUFFLE.

◆ getUnrollingPreferences()

void ARMTTIImpl::getUnrollingPreferences ( Loop *  L,
ScalarEvolution &  SE,
TTI::UnrollingPreferences &  UP,
OptimizationRemarkEmitter *  ORE 
)

Definition at line 2307 of file ARMTargetTransformInfo.cpp.

References llvm::count_if(), llvm::dbgs(), llvm::TargetTransformInfo::UnrollingPreferences::DefaultUnrollRuntimeCount, F, llvm::TargetTransformInfo::UnrollingPreferences::Force, llvm::getBooleanLoopAttribute(), getCalledFunction(), llvm::TargetTransformInfoImplCRTPBase< T >::getInstructionCost(), llvm::BasicTTIImplBase< T >::getUnrollingPreferences(), I, isLoweredToCall(), llvm::ARMSubtarget::isMClass(), llvm::ARMSubtarget::isThumb1Only(), LLVM_DEBUG, Operands, llvm::TargetTransformInfo::UnrollingPreferences::OptSizeThreshold, llvm::TargetTransformInfo::UnrollingPreferences::Partial, llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold, llvm::TargetTransformInfo::UnrollingPreferences::Runtime, llvm::SmallVectorBase< Size_T >::size(), llvm::TargetTransformInfo::TCK_SizeAndLatency, llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam, llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold, UnrollCount, llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder, and llvm::TargetTransformInfo::UnrollingPreferences::UpperBound.

◆ getVectorInstrCost()

InstructionCost ARMTTIImpl::getVectorInstrCost ( unsigned  Opcode,
Type *  Val,
TTI::TargetCostKind  CostKind,
unsigned  Index,
Value *  Op0,
Value *  Op1 
)

Definition at line 876 of file ARMTargetTransformInfo.cpp.

References CostKind, llvm::Type::getScalarSizeInBits(), llvm::Type::getScalarType(), llvm::BasicTTIImplBase< ARMTTIImpl >::getTypeLegalizationCost(), llvm::BasicTTIImplBase< ARMTTIImpl >::getVectorInstrCost(), llvm::Type::isIntegerTy(), and llvm::Type::isVectorTy().

◆ hasArmWideBranch()

bool ARMTTIImpl::hasArmWideBranch ( bool  Thumb) const

Definition at line 2453 of file ARMTargetTransformInfo.cpp.

References llvm::ARMSubtarget::hasARMOps(), and llvm::ARMSubtarget::isThumb2().

◆ instCombineIntrinsic()

std::optional< Instruction * > ARMTTIImpl::instCombineIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II 
) const

Definition at line 122 of file ARMTargetTransformInfo.cpp.

References Arg, llvm::CallBase::arg_size(), assert(), llvm::InstCombiner::Builder, llvm::BinaryOperator::Create(), llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateVectorSplat(), llvm::InstCombiner::eraseInstFromFunction(), llvm::ConstantAsMetadata::get(), llvm::MDNode::get(), llvm::ConstantInt::get(), llvm::CallBase::getArgOperand(), llvm::InstCombiner::getAssumptionCache(), llvm::Value::getContext(), llvm::InstCombiner::getDataLayout(), llvm::InstCombiner::getDominatorTree(), llvm::Type::getInt32Ty(), llvm::IntrinsicInst::getIntrinsicID(), llvm::getKnownAlignment(), llvm::APInt::getLowBitsSet(), llvm::Instruction::getMetadata(), llvm::APInt::getOneBitSet(), llvm::Type::getScalarSizeInBits(), llvm::IRBuilderBase::getTrue(), llvm::Value::getType(), I, llvm::PatternMatch::m_c_Add(), llvm::PatternMatch::m_Constant(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), llvm::PatternMatch::m_Zero(), llvm::PatternMatch::match(), llvm::InstCombiner::replaceInstUsesWith(), llvm::InstCombiner::replaceOperand(), llvm::IRBuilderBase::SetInsertPoint(), llvm::Instruction::setMetadata(), llvm::InstCombiner::SimplifyDemandedBits(), simplifyNeonVld1(), and llvm::Align::value().

◆ isFPVectorizationPotentiallyUnsafe()

bool llvm::ARMTTIImpl::isFPVectorizationPotentiallyUnsafe ( )
inline

Floating-point computation using ARMv8 AArch32 Advanced SIMD instructions remains unchanged from ARMv7.

Only AArch64 SIMD and Arm MVE are IEEE-754 compliant.

Definition at line 118 of file ARMTargetTransformInfo.h.

◆ isHardwareLoopProfitable()

bool ARMTTIImpl::isHardwareLoopProfitable ( Loop *  L,
ScalarEvolution &  SE,
AssumptionCache &  AC,
TargetLibraryInfo *  LibInfo,
HardwareLoopInfo &  HWLoopInfo 
)

Definition at line 2007 of file ARMTargetTransformInfo.cpp.

References AllowWLSLoops, llvm::CallingConv::C, llvm::HardwareLoopInfo::CounterInReg, llvm::HardwareLoopInfo::CountType, llvm::dbgs(), DisableLowOverheadLoops, llvm::ConstantInt::get(), llvm::ScalarEvolution::getAddExpr(), llvm::ScalarEvolution::getBackedgeTakenCount(), llvm::APInt::getBitWidth(), llvm::Type::getInt32Ty(), llvm::IntrinsicInst::getIntrinsicID(), llvm::ScalarEvolution::getOne(), llvm::SCEV::getType(), llvm::ScalarEvolution::getUnsignedRangeMax(), llvm::ScalarEvolution::hasLoopInvariantBackedgeTakenCount(), I, llvm::HardwareLoopInfo::IsNestingLegal, LLVM_DEBUG, llvm::HardwareLoopInfo::LoopDecrement, maybeLoweredToCall(), and llvm::HardwareLoopInfo::PerformEntryTest.

Referenced by preferPredicateOverEpilogue().

◆ isLegalMaskedGather()

bool ARMTTIImpl::isLegalMaskedGather ( Type *  Ty,
Align  Alignment 
)

Definition at line 1121 of file ARMTargetTransformInfo.cpp.

References EnableMaskedGatherScatters, and llvm::Type::getScalarSizeInBits().

Referenced by isLegalMaskedScatter().

◆ isLegalMaskedLoad()

bool ARMTTIImpl::isLegalMaskedLoad ( Type *  DataTy,
Align  Alignment 
)

Definition at line 1101 of file ARMTargetTransformInfo.cpp.

References EnableMaskedLoadStores, llvm::Type::getPrimitiveSizeInBits(), and llvm::Type::getScalarSizeInBits().

Referenced by getMaskedMemoryOpCost(), and isLegalMaskedStore().

◆ isLegalMaskedScatter()

bool llvm::ARMTTIImpl::isLegalMaskedScatter ( Type *  Ty,
Align  Alignment 
)
inline

Definition at line 207 of file ARMTargetTransformInfo.h.

References isLegalMaskedGather().

◆ isLegalMaskedStore()

bool llvm::ARMTTIImpl::isLegalMaskedStore ( Type *  DataTy,
Align  Alignment 
)
inline

Definition at line 189 of file ARMTargetTransformInfo.h.

References isLegalMaskedLoad().

Referenced by getMaskedMemoryOpCost().

◆ isLoweredToCall()

bool ARMTTIImpl::isLoweredToCall ( const Function *  F)

Definition at line 1859 of file ARMTargetTransformInfo.cpp.

References F, llvm::ARMSubtarget::hasFPARMv8Base(), llvm::ARMSubtarget::hasVFP2Base(), and llvm::TargetTransformInfoImplBase::isLoweredToCall().

Referenced by getUnrollingPreferences(), and maybeLoweredToCall().

◆ isProfitableLSRChainElement()

bool ARMTTIImpl::isProfitableLSRChainElement ( Instruction *  I)

Definition at line 1084 of file ARMTargetTransformInfo.cpp.

References llvm::IntrinsicInst::getIntrinsicID(), and I.

◆ maybeLoweredToCall()

bool ARMTTIImpl::maybeLoweredToCall ( Instruction &  I)

Definition at line 1920 of file ARMTargetTransformInfo.cpp.

References llvm::BasicTTIImplBase< ARMTTIImpl >::DL, F, llvm::IntrinsicInst::getIntrinsicID(), getNumMemOps(), llvm::TargetLoweringBase::getOperationAction(), llvm::EVT::getSizeInBits(), llvm::TargetLoweringBase::getValueType(), llvm::ARMSubtarget::hasFPARMv8Base(), I, llvm::TargetLoweringBase::InstructionOpcodeToISD(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), isLoweredToCall(), llvm::TargetLoweringBase::LibCall, llvm::ISD::SDIV, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIV, llvm::ISD::UDIVREM, llvm::ISD::UREM, and llvm::ARMTargetLowering::useSoftFloat().

Referenced by isHardwareLoopProfitable().

◆ preferInLoopReduction()

bool ARMTTIImpl::preferInLoopReduction ( unsigned  Opcode,
Type *  Ty,
TTI::ReductionFlags  Flags 
) const

Definition at line 2415 of file ARMTargetTransformInfo.cpp.

References llvm::Type::getScalarSizeInBits().

◆ preferPredicatedReductionSelect()

bool ARMTTIImpl::preferPredicatedReductionSelect ( unsigned  Opcode,
Type *  Ty,
TTI::ReductionFlags  Flags 
) const

Definition at line 2429 of file ARMTargetTransformInfo.cpp.

◆ preferPredicateOverEpilogue()

bool ARMTTIImpl::preferPredicateOverEpilogue ( TailFoldingInfo *  TFI)

Definition at line 2243 of file ARMTargetTransformInfo.cpp.

References assert(), llvm::HardwareLoopInfo::canAnalyze(), canTailPredicateLoop(), llvm::dbgs(), llvm::BasicTTIImplBase< ARMTTIImpl >::DL, EnableTailPredication, llvm::LoopVectorizationLegality::getAssumptionCache(), llvm::LoopVectorizationLegality::getDominatorTree(), llvm::LoopVectorizationLegality::getLAI(), llvm::LoopVectorizationLegality::getLoop(), llvm::LoopVectorizationLegality::getLoopInfo(), llvm::LoopVectorizationLegality::getScalarEvolution(), llvm::HardwareLoopInfo::isHardwareLoopCandidate(), isHardwareLoopProfitable(), LLVM_DEBUG, llvm::TailFoldingInfo::LVL, and llvm::TailFoldingInfo::TLI.

◆ shouldBuildLookupTablesForConstant()

bool llvm::ARMTTIImpl::shouldBuildLookupTablesForConstant ( Constant *  C) const
inline

Definition at line 316 of file ARMTargetTransformInfo.h.

References llvm::CallingConv::C.

◆ shouldExpandReduction()

bool llvm::ARMTTIImpl::shouldExpandReduction ( const IntrinsicInst *  II) const
inline

Definition at line 227 of file ARMTargetTransformInfo.h.

◆ simplifyDemandedVectorEltsIntrinsic()

std::optional< Value * > ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic ( InstCombiner &  IC,
IntrinsicInst &  II,
APInt  DemandedElts,
APInt &  UndefElts,
APInt &  UndefElts2,
APInt &  UndefElts3,
std::function< void(Instruction *, unsigned, APInt, APInt &)>  SimplifyAndSetOp 
) const

Definition at line 253 of file ARMTargetTransformInfo.cpp.

References llvm::APInt::getHighBitsSet(), llvm::IntrinsicInst::getIntrinsicID(), llvm::APInt::getLowBitsSet(), llvm::User::getOperand(), llvm::APInt::getSplat(), and llvm::Value::getType().

The documentation for this class was generated from the following files:
Generated on Wed Jun 7 2023 05:31:10 for LLVM by doxygen 1.9.6