LLVM 17.0.0git
ARMSubtarget.h
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1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
14#define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
15
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
19#include "ARMFrameLowering.h"
20#include "ARMISelLowering.h"
22#include "ARMSelectionDAGInfo.h"
23#include "llvm/ADT/Triple.h"
32#include "llvm/MC/MCSchedule.h"
35#include <memory>
36#include <string>
37
38#define GET_SUBTARGETINFO_HEADER
39#include "ARMGenSubtargetInfo.inc"
40
41namespace llvm {
42
43class ARMBaseTargetMachine;
44class GlobalValue;
45class StringRef;
46
48protected:
51
87 Swift
88 };
91
94 RClass
95 };
133 };
134
135public:
136 /// What kind of timing do load multiple/store multiple instructions have.
138 /// Can load/store 2 registers/cycle.
140 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
141 /// is not 64-bit aligned.
143 /// Can load/store 1 register/cycle.
145 /// Can load/store 1 register/cycle, but needs an extra cycle for address
146 /// computation and potentially also for register writeback.
148 };
149
150protected:
151// Bool members corresponding to the SubtargetFeatures defined in tablegen
152#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
153 bool ATTRIBUTE = DEFAULT;
154#include "ARMGenSubtargetInfo.inc"
155
156 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
158
159 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
161
162 /// ARMArch - ARM architecture
164
165 /// UseMulOps - True if non-microcoded fused integer multiply-add and
166 /// multiply-subtract instructions should be used.
167 bool UseMulOps = false;
168
169 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
170 /// must be able to synthesize call stubs for interworking between ARM and
171 /// Thumb.
172 bool SupportsTailCall = false;
173
174 /// RestrictIT - If true, the subtarget disallows generation of complex IT
175 /// blocks.
176 bool RestrictIT = false;
177
178 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
179 bool UseSjLjEH = false;
180
181 /// stackAlignment - The minimum alignment known to hold of the stack frame on
182 /// entry to the function and which must be maintained by every function.
184
185 /// CPUString - String name of used CPU.
186 std::string CPUString;
187
189
190 /// Clearance before partial register updates (in number of instructions)
192
193 /// What kind of timing do load multiple/store multiple have (double issue,
194 /// single issue etc).
196
197 /// The adjustment that we need to apply to get the operand latency from the
198 /// operand cycle returned by the itinerary data for pre-ISel operands.
200
201 /// What alignment is preferred for loop bodies, in log2(bytes).
203
204 /// The cost factor for MVE instructions, representing the multiple beats an
205 // instruction can take. The default is 2, (set in initSubtargetFeatures so
206 // that we can use subtarget features less than 2).
208
209 /// OptMinSize - True if we're optimising for minimum code size, equal to
210 /// the function attribute.
211 bool OptMinSize = false;
212
213 /// IsLittle - The target is Little Endian
215
216 /// TargetTriple - What processor and OS we're targeting.
218
219 /// SchedModel - Processor specific instruction costs.
221
222 /// Selected instruction itineraries (one entry per itinerary class.)
224
225 /// Options passed via command line that could influence the target
227
229
230public:
231 /// This constructor initializes the data members to match that
232 /// of the specified triple.
233 ///
234 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
235 const ARMBaseTargetMachine &TM, bool IsLittle,
236 bool MinSize = false);
237
238 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
239 /// that still makes it profitable to inline the call.
240 unsigned getMaxInlineSizeThreshold() const {
241 return 64;
242 }
243
244 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size
245 /// that still makes it profitable to inline a llvm.memcpy as a Tail
246 /// Predicated loop.
247 /// This threshold should only be used for constant size inputs.
248 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; }
249
250 /// ParseSubtargetFeatures - Parses features string setting specified
251 /// subtarget options. Definition of function is auto generated by tblgen.
253
254 /// initializeSubtargetDependencies - Initializes using a CPU and feature string
255 /// so that we can use initializer lists for subtarget initialization.
257
258 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
259 return &TSInfo;
260 }
261
262 const ARMBaseInstrInfo *getInstrInfo() const override {
263 return InstrInfo.get();
264 }
265
266 const ARMTargetLowering *getTargetLowering() const override {
267 return &TLInfo;
268 }
269
270 const ARMFrameLowering *getFrameLowering() const override {
271 return FrameLowering.get();
272 }
273
274 const ARMBaseRegisterInfo *getRegisterInfo() const override {
275 return &InstrInfo->getRegisterInfo();
276 }
277
278 const CallLowering *getCallLowering() const override;
280 const LegalizerInfo *getLegalizerInfo() const override;
281 const RegisterBankInfo *getRegBankInfo() const override;
282
283private:
284 ARMSelectionDAGInfo TSInfo;
285 // Either Thumb1FrameLowering or ARMFrameLowering.
286 std::unique_ptr<ARMFrameLowering> FrameLowering;
287 // Either Thumb1InstrInfo or Thumb2InstrInfo.
288 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
289 ARMTargetLowering TLInfo;
290
291 /// GlobalISel related APIs.
292 std::unique_ptr<CallLowering> CallLoweringInfo;
293 std::unique_ptr<InstructionSelector> InstSelector;
294 std::unique_ptr<LegalizerInfo> Legalizer;
295 std::unique_ptr<RegisterBankInfo> RegBankInfo;
296
297 void initializeEnvironment();
298 void initSubtargetFeatures(StringRef CPU, StringRef FS);
299 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
300
301 std::bitset<8> CoprocCDE = {};
302public:
303// Getters for SubtargetFeatures defined in tablegen
304#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
305 bool GETTER() const { return ATTRIBUTE; }
306#include "ARMGenSubtargetInfo.inc"
307
309
310 /// @{
311 /// These functions are obsolete, please consider adding subtarget features
312 /// or properties instead of calling them.
313 bool isCortexA5() const { return ARMProcFamily == CortexA5; }
314 bool isCortexA7() const { return ARMProcFamily == CortexA7; }
315 bool isCortexA8() const { return ARMProcFamily == CortexA8; }
316 bool isCortexA9() const { return ARMProcFamily == CortexA9; }
317 bool isCortexA15() const { return ARMProcFamily == CortexA15; }
318 bool isSwift() const { return ARMProcFamily == Swift; }
319 bool isCortexM3() const { return ARMProcFamily == CortexM3; }
320 bool isCortexM7() const { return ARMProcFamily == CortexM7; }
321 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
322 bool isCortexR5() const { return ARMProcFamily == CortexR5; }
323 bool isKrait() const { return ARMProcFamily == Krait; }
324 /// @}
325
326 bool hasARMOps() const { return !NoARM; }
327
329 return hasNEON() && hasNEONForFP();
330 }
331
332 bool hasVFP2Base() const { return hasVFPv2SP(); }
333 bool hasVFP3Base() const { return hasVFPv3D16SP(); }
334 bool hasVFP4Base() const { return hasVFPv4D16SP(); }
335 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); }
336
337 bool hasAnyDataBarrier() const {
338 return HasDataBarrier || (hasV6Ops() && !isThumb());
339 }
340
341 bool useMulOps() const { return UseMulOps; }
342 bool useFPVMLx() const { return !SlowFPVMLx; }
343 bool useFPVFMx() const {
344 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx;
345 }
346 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); }
347 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); }
348 bool useSjLjEH() const { return UseSjLjEH; }
349 bool hasBaseDSP() const {
350 if (isThumb())
351 return hasDSP();
352 else
353 return hasV5TEOps();
354 }
355
356 /// Return true if the CPU supports any kind of instruction fusion.
357 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); }
358
359 const Triple &getTargetTriple() const { return TargetTriple; }
360
361 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
362 bool isTargetIOS() const { return TargetTriple.isiOS(); }
363 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
364 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
365 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); }
366 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
367 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
368 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
369 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
370
371 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
372 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
374
375 // ARM EABI is the bare-metal EABI described in ARM ABI documents and
376 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
377 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
378 // even for GNUEABI, so we can make a distinction here and still conform to
379 // the EABI on GNU (and Android) mode. This requires change in Clang, too.
380 // FIXME: The Darwin exception is temporary, while we move users to
381 // "*-*-*-macho" triples as quickly as possible.
382 bool isTargetAEABI() const {
386 }
387 bool isTargetGNUAEABI() const {
391 }
392 bool isTargetMuslAEABI() const {
396 }
397
398 // ARM Targets that support EHABI exception handling standard
399 // Darwin uses SjLj. Other targets might need more checks.
402 }
403
404 bool isTargetHardFloat() const;
405
406 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
407
408 bool isXRaySupported() const override;
409
410 bool isAPCS_ABI() const;
411 bool isAAPCS_ABI() const;
412 bool isAAPCS16_ABI() const;
413
414 bool isROPI() const;
415 bool isRWPI() const;
416
417 bool useMachineScheduler() const { return UseMISched; }
418 bool useMachinePipeliner() const { return UseMIPipeliner; }
419 bool hasMinSize() const { return OptMinSize; }
420 bool isThumb1Only() const { return isThumb() && !hasThumb2(); }
421 bool isThumb2() const { return isThumb() && hasThumb2(); }
422 bool isMClass() const { return ARMProcClass == MClass; }
423 bool isRClass() const { return ARMProcClass == RClass; }
424 bool isAClass() const { return ARMProcClass == AClass; }
425
426 bool isR9Reserved() const {
427 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
428 }
429
431 if (isTargetDarwin() ||
432 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain()))
433 return ARM::R7;
434 return ARM::R11;
435 }
436
437 /// Returns true if the frame setup is split into two separate pushes (first
438 /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
439 /// to lr. This is always required on Thumb1-only targets, as the push and
440 /// pop instructions can't access the high registers.
441 bool splitFramePushPop(const MachineFunction &MF) const {
443 return true;
444 return (getFramePointerReg() == ARM::R7 &&
446 isThumb1Only();
447 }
448
449 bool splitFramePointerPush(const MachineFunction &MF) const;
450
451 bool useStride4VFPs() const;
452
453 bool useMovt() const;
454
455 bool supportsTailCall() const { return SupportsTailCall; }
456
457 bool allowsUnalignedMem() const { return !StrictAlign; }
458
459 bool restrictIT() const { return RestrictIT; }
460
461 const std::string & getCPUString() const { return CPUString; }
462
463 bool isLittle() const { return IsLittle; }
464
465 unsigned getMispredictionPenalty() const;
466
467 /// Returns true if machine scheduler should be enabled.
468 bool enableMachineScheduler() const override;
469
470 /// Returns true if machine pipeliner should be enabled.
471 bool enableMachinePipeliner() const override;
472 bool useDFAforSMS() const override;
473
474 /// True for some subtargets at > -O0.
475 bool enablePostRAScheduler() const override;
476
477 /// True for some subtargets at > -O0.
478 bool enablePostRAMachineScheduler() const override;
479
480 /// Check whether this subtarget wants to use subregister liveness.
481 bool enableSubRegLiveness() const override;
482
483 /// Enable use of alias analysis during code generation (during MI
484 /// scheduling, DAGCombine, etc.).
485 bool useAA() const override { return true; }
486
487 /// getInstrItins - Return the instruction itineraries based on subtarget
488 /// selection.
490 return &InstrItins;
491 }
492
493 /// getStackAlignment - Returns the minimum alignment known to hold of the
494 /// stack frame on entry to the function and which must be maintained by every
495 /// function for this subtarget.
497
498 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
499
501
503 return LdStMultipleTiming;
504 }
505
508 }
509
510 /// True if the GV will be accessed via an indirect symbol.
511 bool isGVIndirectSymbol(const GlobalValue *GV) const;
512
513 /// Returns the constant pool modifier needed to access the GV.
514 bool isGVInGOT(const GlobalValue *GV) const;
515
516 /// True if fast-isel is used.
517 bool useFastISel() const;
518
519 /// Returns the correct return opcode for the current feature set.
520 /// Use BX if available to allow mixing thumb/arm code, but fall back
521 /// to plain mov pc,lr on ARMv4.
522 unsigned getReturnOpcode() const {
523 if (isThumb())
524 return ARM::tBX_RET;
525 if (hasV4TOps())
526 return ARM::BX_RET;
527 return ARM::MOVPCLR;
528 }
529
530 /// Allow movt+movw for PIC global address calculation.
531 /// ELF does not have GOT relocations for movt+movw.
532 /// ROPI does not use GOT.
534 return isROPI() || !isTargetELF();
535 }
536
538
539 unsigned
542 return 1;
543 return MVEVectorCostFactor;
544 }
545
547 unsigned PhysReg) const override;
548 unsigned getGPRAllocationOrder(const MachineFunction &MF) const;
549};
550
551} // end namespace llvm
552
553#endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
This header is deprecated in favour of llvm/TargetParser/Triple.h.
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
Interface for Targets to specify which operations they can successfully select and how the others sho...
This pass exposes codegen information to IR-level passes.
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
Definition: ARMSubtarget.h:373
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
Definition: ARMSubtarget.h:357
bool isCortexA7() const
Definition: ARMSubtarget.h:314
bool IsLittle
IsLittle - The target is Little Endian.
Definition: ARMSubtarget.h:214
bool useMovt() const
bool isSwift() const
Definition: ARMSubtarget.h:318
bool isTargetAEABI() const
Definition: ARMSubtarget.h:382
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:195
bool hasARMOps() const
Definition: ARMSubtarget.h:326
bool supportsTailCall() const
Definition: ARMSubtarget.h:455
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:359
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:179
bool hasVFP4Base() const
Definition: ARMSubtarget.h:334
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:188
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:228
bool isRClass() const
Definition: ARMSubtarget.h:423
ARMLdStMultipleTiming getLdStMultipleTiming() const
Definition: ARMSubtarget.h:502
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:262
bool useFPVMLx() const
Definition: ARMSubtarget.h:342
bool isThumb1Only() const
Definition: ARMSubtarget.h:420
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:157
bool useFPVFMx() const
Definition: ARMSubtarget.h:343
ARMArchEnum ARMArch
ARMArch - ARM architecture.
Definition: ARMSubtarget.h:163
bool isCortexM7() const
Definition: ARMSubtarget.h:320
bool hasFPARMv8Base() const
Definition: ARMSubtarget.h:335
bool isAClass() const
Definition: ARMSubtarget.h:424
bool isThumb2() const
Definition: ARMSubtarget.h:421
bool useDFAforSMS() const override
ARMProcClassEnum ARMProcClass
ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
Definition: ARMSubtarget.h:160
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:430
bool isTargetWindows() const
Definition: ARMSubtarget.h:369
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:400
bool isCortexR5() const
Definition: ARMSubtarget.h:322
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:207
bool hasBaseDSP() const
Definition: ARMSubtarget.h:349
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:266
bool useSjLjEH() const
Definition: ARMSubtarget.h:348
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:220
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:186
unsigned getMispredictionPenalty() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:217
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isLikeA9() const
Definition: ARMSubtarget.h:321
bool isTargetDarwin() const
Definition: ARMSubtarget.h:361
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:274
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:223
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:211
unsigned getReturnOpcode() const
Returns the correct return opcode for the current feature set.
Definition: ARMSubtarget.h:522
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:176
Align getStackAlignment() const
getStackAlignment - Returns the minimum alignment known to hold of the stack frame on entry to the fu...
Definition: ARMSubtarget.h:496
bool isKrait() const
Definition: ARMSubtarget.h:323
bool isCortexA5() const
Definition: ARMSubtarget.h:313
bool hasVFP2Base() const
Definition: ARMSubtarget.h:332
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:202
bool useAA() const override
Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...
Definition: ARMSubtarget.h:485
bool isTargetAndroid() const
Definition: ARMSubtarget.h:406
bool isROPI() const
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:183
unsigned getMaxMemcpyTPInlineSizeThreshold() const
getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size that still makes it profitable to inline...
Definition: ARMSubtarget.h:248
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:191
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
bool isTargetCOFF() const
Definition: ARMSubtarget.h:371
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:441
unsigned getMaxInlineSizeThreshold() const
getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size that still makes it profitable t...
Definition: ARMSubtarget.h:240
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:387
const ARMSelectionDAGInfo * getSelectionDAGInfo() const override
Definition: ARMSubtarget.h:258
const std::string & getCPUString() const
Definition: ARMSubtarget.h:461
InstructionSelector * getInstructionSelector() const override
unsigned getMaxInterleaveFactor() const
Definition: ARMSubtarget.h:498
bool hasVFP3Base() const
Definition: ARMSubtarget.h:333
bool isR9Reserved() const
Definition: ARMSubtarget.h:426
bool isAPCS_ABI() const
bool useFPVFMx64() const
Definition: ARMSubtarget.h:347
unsigned getPartialUpdateClearance() const
Definition: ARMSubtarget.h:500
bool isTargetNetBSD() const
Definition: ARMSubtarget.h:368
bool isTargetWatchOS() const
Definition: ARMSubtarget.h:363
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
bool hasMinSize() const
Definition: ARMSubtarget.h:419
bool splitFramePointerPush(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isTargetIOS() const
Definition: ARMSubtarget.h:362
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool useNEONForSinglePrecisionFP() const
Definition: ARMSubtarget.h:328
bool isTargetNaCl() const
Definition: ARMSubtarget.h:367
const InstrItineraryData * getInstrItineraryData() const override
getInstrItins - Return the instruction itineraries based on subtarget selection.
Definition: ARMSubtarget.h:489
bool isCortexM3() const
Definition: ARMSubtarget.h:319
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:364
bool allowPositionIndependentMovt() const
Allow movt+movw for PIC global address calculation.
Definition: ARMSubtarget.h:533
bool isCortexA8() const
Definition: ARMSubtarget.h:315
bool UseMulOps
UseMulOps - True if non-microcoded fused integer multiply-add and multiply-subtract instructions shou...
Definition: ARMSubtarget.h:167
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:226
ARMLdStMultipleTiming
What kind of timing do load multiple/store multiple instructions have.
Definition: ARMSubtarget.h:137
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:142
@ SingleIssue
Can load/store 1 register/cycle.
Definition: ARMSubtarget.h:144
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:139
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:147
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool hasAnyDataBarrier() const
Definition: ARMSubtarget.h:337
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:418
bool isTargetDriverKit() const
Definition: ARMSubtarget.h:365
int getPreISelOperandLatencyAdjustment() const
Definition: ARMSubtarget.h:506
bool isAAPCS_ABI() const
bool useMachineScheduler() const
Definition: ARMSubtarget.h:417
bool isCortexA15() const
Definition: ARMSubtarget.h:317
bool isRWPI() const
bool isLittle() const
Definition: ARMSubtarget.h:463
bool allowsUnalignedMem() const
Definition: ARMSubtarget.h:457
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:392
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
Definition: ARMSubtarget.h:366
bool isCortexA9() const
Definition: ARMSubtarget.h:316
bool useFPVFMx16() const
Definition: ARMSubtarget.h:346
bool isMClass() const
Definition: ARMSubtarget.h:422
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:172
unsigned getPrefLoopLogAlignment() const
Definition: ARMSubtarget.h:537
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:199
bool isTargetHardFloat() const
bool useMulOps() const
Definition: ARMSubtarget.h:341
bool isTargetELF() const
Definition: ARMSubtarget.h:372
bool restrictIT() const
Definition: ARMSubtarget.h:459
unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const
Definition: ARMSubtarget.h:540
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:270
Itinerary data supplied by a subtarget to be used by a target.
Provides the logic to select generic machine instructions.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetCostKind
The kind of cost model.
@ TCK_CodeSize
Instruction code size.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:632
bool isWatchABI() const
Definition: Triple.h:508
@ MuslEABIHF
Definition: Triple.h:247
bool isDriverKit() const
Is this an Apple DriverKit triple.
Definition: Triple.h:513
bool isTargetEHABICompatible() const
Tests whether the target supports the EHABI exception handling standard.
Definition: Triple.h:785
bool isOSNetBSD() const
Definition: Triple.h:536
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:724
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:687
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:679
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:372
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:583
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:637
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:518
bool isWatchOS() const
Is this an Apple watchOS triple.
Definition: Triple.h:504
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:494
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:674
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244