LLVM 20.0.0git
Classes | Namespaces | Macros | Functions
ARMBaseInstrInfo.h File Reference
#include "ARMBaseRegisterInfo.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/Support/ErrorHandling.h"
#include <array>
#include <cstdint>
#include "ARMGenInstrInfo.inc"

Go to the source code of this file.

Classes

class  llvm::ARMBaseInstrInfo
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 

Macros

#define GET_INSTRINFO_HEADER
 

Functions

static std::array< MachineOperand, 2 > llvm::predOps (ARMCC::CondCodes Pred, unsigned PredReg=0)
 Get the operands corresponding to the given Pred value.
 
static MachineOperand llvm::condCodeOp (unsigned CCReg=0)
 Get the operand corresponding to the conditional code result.
 
static MachineOperand llvm::t1CondCodeOp (bool isDead=false)
 Get the operand corresponding to the conditional code result for Thumb1.
 
static bool llvm::isUncondBranchOpcode (int Opc)
 
static bool llvm::isVPTOpcode (int Opc)
 
static unsigned llvm::VCMPOpcodeToVPT (unsigned Opcode)
 
static bool llvm::isCondBranchOpcode (int Opc)
 
static bool llvm::isJumpTableBranchOpcode (int Opc)
 
static bool llvm::isIndirectBranchOpcode (int Opc)
 
static bool llvm::isIndirectCall (const MachineInstr &MI)
 
static bool llvm::isIndirectControlFlowNotComingBack (const MachineInstr &MI)
 
static bool llvm::isSpeculationBarrierEndBBOpcode (int Opc)
 
static bool llvm::isPopOpcode (int Opc)
 
static bool llvm::isPushOpcode (int Opc)
 
static bool llvm::isSubImmOpcode (int Opc)
 
static bool llvm::isMovRegOpcode (int Opc)
 
static bool llvm::isValidCoprocessorNumber (unsigned Num, const FeatureBitset &featureBits)
 isValidCoprocessorNumber - decide whether an explicit coprocessor number is legal in generic instructions like CDP.
 
static bool llvm::isSEHInstruction (const MachineInstr &MI)
 
ARMCC::CondCodes llvm::getInstrPredicate (const MachineInstr &MI, Register &PredReg)
 getInstrPredicate - If instruction is predicated, returns its predicate condition, otherwise returns AL.
 
unsigned llvm::getMatchingCondBranchOpcode (unsigned Opc)
 
unsigned llvm::convertAddSubFlagsOpcode (unsigned OldOpc)
 Map pseudo instructions that imply an 'S' bit onto real opcodes.
 
void llvm::emitARMRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
 emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea destreg = basereg + immediate in ARM / Thumb2 code.
 
void llvm::emitT2RegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
 
void llvm::emitThumbRegPlusImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo &MRI, unsigned MIFlags=0)
 emitThumbRegPlusImmediate - Emits a series of instructions to materialize a destreg = basereg + immediate in Thumb code.
 
bool llvm::tryFoldSPUpdateIntoPushPop (const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
 Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the stack by an additional NumBytes.
 
bool llvm::rewriteARMFrameIndex (MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII)
 rewriteARMFrameIndex / rewriteT2FrameIndex - Rewrite MI to access 'Offset' bytes from the FP.
 
bool llvm::rewriteT2FrameIndex (MachineInstr &MI, unsigned FrameRegIdx, Register FrameReg, int &Offset, const ARMBaseInstrInfo &TII, const TargetRegisterInfo *TRI)
 
bool llvm::registerDefinedBetween (unsigned Reg, MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI)
 Return true if Reg is defd between From and To.
 
MachineInstrllvm::findCMPToFoldIntoCBZ (MachineInstr *Br, const TargetRegisterInfo *TRI)
 Search backwards from a tBcc to find a tCMPi8 against 0, meaning we can convert them to a tCBZ or tCBNZ.
 
void llvm::addUnpredicatedMveVpredNOp (MachineInstrBuilder &MIB)
 
void llvm::addUnpredicatedMveVpredROp (MachineInstrBuilder &MIB, Register DestReg)
 
void llvm::addPredicatedMveVpredNOp (MachineInstrBuilder &MIB, unsigned Cond)
 
void llvm::addPredicatedMveVpredROp (MachineInstrBuilder &MIB, unsigned Cond, unsigned Inactive)
 
unsigned llvm::ConstantMaterializationCost (unsigned Val, const ARMSubtarget *Subtarget, bool ForCodesize=false)
 Returns the number of instructions required to materialize the given constant in a register, or 3 if a literal pool load is needed.
 
bool llvm::HasLowerConstantMaterializationCost (unsigned Val1, unsigned Val2, const ARMSubtarget *Subtarget, bool ForCodesize=false)
 Returns true if Val1 has a lower Constant Materialization Cost than Val2.
 
int llvm::getAddSubImmediate (MachineInstr &MI)
 
bool llvm::isLegalAddressImm (unsigned Opcode, int Imm, const TargetInstrInfo *TII)
 
bool llvm::isGather (IntrinsicInst *IntInst)
 
bool llvm::isScatter (IntrinsicInst *IntInst)
 
bool llvm::isGatherScatter (IntrinsicInst *IntInst)
 
unsigned llvm::getBLXOpcode (const MachineFunction &MF)
 
unsigned llvm::gettBLXrOpcode (const MachineFunction &MF)
 
unsigned llvm::getBLXpredOpcode (const MachineFunction &MF)
 

Macro Definition Documentation

◆ GET_INSTRINFO_HEADER

#define GET_INSTRINFO_HEADER

Definition at line 34 of file ARMBaseInstrInfo.h.