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ARMMCTargetDesc.h
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1 //===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
14 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include <memory>
19 #include <string>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInstrInfo;
27 class MCInstPrinter;
28 class MCObjectTargetWriter;
29 class MCObjectWriter;
30 class MCRegisterInfo;
31 class MCSubtargetInfo;
32 class MCStreamer;
33 class MCTargetOptions;
34 class MCRelocationInfo;
35 class MCTargetStreamer;
36 class StringRef;
37 class Target;
38 class Triple;
39 
40 namespace ARM_MC {
41 std::string ParseARMTriple(const Triple &TT, StringRef CPU);
43 
44 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
45 bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII);
46 
47 template<class Inst>
48 bool isLDMBaseRegInList(const Inst &MI) {
49  auto BaseReg = MI.getOperand(0).getReg();
50  for (unsigned I = 1, E = MI.getNumOperands(); I < E; ++I) {
51  const auto &Op = MI.getOperand(I);
52  if (Op.isReg() && Op.getReg() == BaseReg)
53  return true;
54  }
55  return false;
56 }
57 
59  int64_t Imm);
60 
61 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
62 /// do not need to go through TargetRegistry.
64  StringRef FS);
65 }
66 
67 MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
68 MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
69  formatted_raw_ostream &OS,
70  MCInstPrinter *InstPrint,
71  bool isVerboseAsm);
72 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
73  const MCSubtargetInfo &STI);
74 
75 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
76  MCContext &Ctx);
77 
78 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
79  MCContext &Ctx);
80 
81 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
82  const MCRegisterInfo &MRI,
83  const MCTargetOptions &Options);
84 
85 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
86  const MCRegisterInfo &MRI,
87  const MCTargetOptions &Options);
88 
89 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
90 // object file.
91 MCStreamer *createARMWinCOFFStreamer(MCContext &Context,
92  std::unique_ptr<MCAsmBackend> &&MAB,
93  std::unique_ptr<MCObjectWriter> &&OW,
94  std::unique_ptr<MCCodeEmitter> &&Emitter,
95  bool RelaxAll,
96  bool IncrementalLinkerCompatible);
97 
98 /// Construct an ELF Mach-O object writer.
99 std::unique_ptr<MCObjectTargetWriter> createARMELFObjectWriter(uint8_t OSABI);
100 
101 /// Construct an ARM Mach-O object writer.
102 std::unique_ptr<MCObjectTargetWriter>
104  uint32_t CPUSubtype);
105 
106 /// Construct an ARM PE/COFF object writer.
107 std::unique_ptr<MCObjectTargetWriter>
109 
110 /// Construct ARM Mach-O relocation info.
111 MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
112 
113 namespace ARM {
117 };
118 inline bool isVpred(OperandType op) {
119  return op == OPERAND_VPRED_R || op == OPERAND_VPRED_N;
120 }
121 inline bool isVpred(uint8_t op) {
122  return isVpred(static_cast<OperandType>(op));
123 }
124 
125 bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI);
126 
127 } // end namespace ARM
128 
129 } // End llvm namespace
130 
131 // Defines symbolic names for ARM registers. This defines a mapping from
132 // register name to register number.
133 //
134 #define GET_REGINFO_ENUM
135 #include "ARMGenRegisterInfo.inc"
136 
137 // Defines symbolic names for the ARM instructions.
138 //
139 #define GET_INSTRINFO_ENUM
140 #include "ARMGenInstrInfo.inc"
141 
142 #define GET_SUBTARGETINFO_ENUM
143 #include "ARMGenSubtargetInfo.inc"
144 
145 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARM::isVpred
bool isVpred(OperandType op)
Definition: ARMMCTargetDesc.h:118
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2008
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:141
MCInstrDesc.h
llvm::createARMObjectTargetStreamer
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: ARMELFStreamer.cpp:1372
op
#define op(i)
llvm::createARMNullTargetStreamer
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
Definition: ARMELFStreamer.cpp:1368
llvm::createARMBEAsmBackend
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1320
llvm::createARMLEAsmBackend
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1313
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ARM_MC::isCPSRDefined
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:175
llvm::MachO::CPUType
CPUType
Definition: MachO.h:1441
llvm::AMDGPU::Exp::Target
Target
Definition: SIDefines.h:836
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::ARM_MC::evaluateBranchTarget
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
Definition: ARMMCTargetDesc.cpp:186
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:169
llvm::createARMMachObjectWriter
std::unique_ptr< MCObjectTargetWriter > createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an ARM Mach-O object writer.
Definition: ARMMachObjectWriter.cpp:507
llvm::ARM_MC::isLDMBaseRegInList
bool isLDMBaseRegInList(const Inst &MI)
Definition: ARMMCTargetDesc.h:48
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
uint64_t
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::createARMTargetAsmStreamer
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: ARMELFStreamer.cpp:1361
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:223
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
uint32_t
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::createARMMachORelocationInfo
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
Definition: ARMMachORelocationInfo.cpp:40
llvm::ARM::OperandType
OperandType
Definition: ARMMCTargetDesc.h:114
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::createARMWinCOFFStreamer
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: ARMWinCOFFStreamer.cpp:41
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:326
llvm::createARMWinCOFFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createARMWinCOFFObjectWriter()
Construct an ARM PE/COFF object writer.
Definition: ARMWinCOFFObjectWriter.cpp:103
llvm::ARM_MC::createARMMCSubtargetInfo
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Definition: ARMMCTargetDesc.cpp:204
llvm::MCOI::OPERAND_FIRST_TARGET
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:77
DataTypes.h
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2013
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:633
llvm::ARM::OPERAND_VPRED_R
@ OPERAND_VPRED_R
Definition: ARMMCTargetDesc.h:115
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ARM::OPERAND_VPRED_N
@ OPERAND_VPRED_N
Definition: ARMMCTargetDesc.h:116
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::createARMELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createARMELFObjectWriter(uint8_t OSABI)
Construct an ELF Mach-O object writer.
Definition: ARMELFObjectWriter.cpp:290