LLVM  15.0.0git
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/TargetRegistry.h"
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38 
40  std::string &Info) {
41  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44  // Checks for the deprecated CP15ISB encoding:
45  // mcr p15, #0, rX, c7, c5, #4
46  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49  Info = "deprecated since v7, use 'isb'";
50  return true;
51  }
52 
53  // Checks for the deprecated CP15DSB encoding:
54  // mcr p15, #0, rX, c7, c10, #4
55  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56  Info = "deprecated since v7, use 'dsb'";
57  return true;
58  }
59  }
60  // Checks for the deprecated CP15DMB encoding:
61  // mcr p15, #0, rX, c7, c10, #5
62  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64  Info = "deprecated since v7, use 'dmb'";
65  return true;
66  }
67  }
68  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72  "point instructions";
73  return true;
74  }
75  return false;
76 }
77 
79  std::string &Info) {
80  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84  "point instructions";
85  return true;
86  }
87  return false;
88 }
89 
91  std::string &Info) {
92  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
93  "cannot predicate thumb instructions");
94 
95  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
96  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
97  assert(MI.getOperand(OI).isReg() && "expected register");
98  if (MI.getOperand(OI).getReg() == ARM::PC) {
99  Info = "use of PC in the list is deprecated";
100  return true;
101  }
102  }
103  return false;
104 }
105 
107  std::string &Info) {
108  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
109  "cannot predicate thumb instructions");
110 
111  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
112  bool ListContainsPC = false, ListContainsLR = false;
113  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
114  assert(MI.getOperand(OI).isReg() && "expected register");
115  switch (MI.getOperand(OI).getReg()) {
116  default:
117  break;
118  case ARM::LR:
119  ListContainsLR = true;
120  break;
121  case ARM::PC:
122  ListContainsPC = true;
123  break;
124  }
125  }
126 
127  if (ListContainsPC && ListContainsLR) {
128  Info = "use of LR and PC simultaneously in the list is deprecated";
129  return true;
130  }
131 
132  return false;
133 }
134 
135 #define GET_INSTRINFO_MC_DESC
136 #include "ARMGenInstrInfo.inc"
137 
138 #define GET_SUBTARGETINFO_MC_DESC
139 #include "ARMGenSubtargetInfo.inc"
140 
141 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
142  std::string ARMArchFeature;
143 
144  ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
145  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
146  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
147 
148  if (TT.isThumb()) {
149  if (!ARMArchFeature.empty())
150  ARMArchFeature += ",";
151  ARMArchFeature += "+thumb-mode,+v4t";
152  }
153 
154  if (TT.isOSNaCl()) {
155  if (!ARMArchFeature.empty())
156  ARMArchFeature += ",";
157  ARMArchFeature += "+nacl-trap";
158  }
159 
160  if (TT.isOSWindows()) {
161  if (!ARMArchFeature.empty())
162  ARMArchFeature += ",";
163  ARMArchFeature += "+noarm";
164  }
165 
166  return ARMArchFeature;
167 }
168 
169 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
170  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
171  int PredOpIdx = Desc.findFirstPredOperandIdx();
172  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
173 }
174 
175 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
176  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
177  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
178  const MCOperand &MO = MI.getOperand(I);
179  if (MO.isReg() && MO.getReg() == ARM::CPSR &&
180  Desc.OpInfo[I].isOptionalDef())
181  return true;
182  }
183  return false;
184 }
185 
187  uint64_t Addr, int64_t Imm) {
188  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
189  // is 4 bytes.
190  uint64_t Offset =
191  ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
192 
193  // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
194  // which is 32-bit aligned. The target address for the case is calculated as
195  // targetAddress = Align(PC,4) + imm32;
196  // where
197  // Align(x, y) = y * (x DIV y);
198  if (InstDesc.getOpcode() == ARM::tBLXi)
199  Addr &= ~0x3;
200 
201  return Addr + Imm + Offset;
202 }
203 
205  StringRef CPU, StringRef FS) {
206  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
207  if (!FS.empty()) {
208  if (!ArchFS.empty())
209  ArchFS = (Twine(ArchFS) + "," + FS).str();
210  else
211  ArchFS = std::string(FS);
212  }
213 
214  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
215 }
216 
218  MCInstrInfo *X = new MCInstrInfo();
219  InitARMMCInstrInfo(X);
220  return X;
221 }
222 
224  // Mapping from CodeView to MC register id.
225  static const struct {
226  codeview::RegisterId CVReg;
227  MCPhysReg Reg;
228  } RegMap[] = {
229  {codeview::RegisterId::ARM_R0, ARM::R0},
230  {codeview::RegisterId::ARM_R1, ARM::R1},
231  {codeview::RegisterId::ARM_R2, ARM::R2},
232  {codeview::RegisterId::ARM_R3, ARM::R3},
233  {codeview::RegisterId::ARM_R4, ARM::R4},
234  {codeview::RegisterId::ARM_R5, ARM::R5},
235  {codeview::RegisterId::ARM_R6, ARM::R6},
236  {codeview::RegisterId::ARM_R7, ARM::R7},
237  {codeview::RegisterId::ARM_R8, ARM::R8},
238  {codeview::RegisterId::ARM_R9, ARM::R9},
239  {codeview::RegisterId::ARM_R10, ARM::R10},
240  {codeview::RegisterId::ARM_R11, ARM::R11},
241  {codeview::RegisterId::ARM_R12, ARM::R12},
242  {codeview::RegisterId::ARM_SP, ARM::SP},
243  {codeview::RegisterId::ARM_LR, ARM::LR},
244  {codeview::RegisterId::ARM_PC, ARM::PC},
245  {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
246  {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
247  {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
248  {codeview::RegisterId::ARM_FS0, ARM::S0},
249  {codeview::RegisterId::ARM_FS1, ARM::S1},
250  {codeview::RegisterId::ARM_FS2, ARM::S2},
251  {codeview::RegisterId::ARM_FS3, ARM::S3},
252  {codeview::RegisterId::ARM_FS4, ARM::S4},
253  {codeview::RegisterId::ARM_FS5, ARM::S5},
254  {codeview::RegisterId::ARM_FS6, ARM::S6},
255  {codeview::RegisterId::ARM_FS7, ARM::S7},
256  {codeview::RegisterId::ARM_FS8, ARM::S8},
257  {codeview::RegisterId::ARM_FS9, ARM::S9},
258  {codeview::RegisterId::ARM_FS10, ARM::S10},
259  {codeview::RegisterId::ARM_FS11, ARM::S11},
260  {codeview::RegisterId::ARM_FS12, ARM::S12},
261  {codeview::RegisterId::ARM_FS13, ARM::S13},
262  {codeview::RegisterId::ARM_FS14, ARM::S14},
263  {codeview::RegisterId::ARM_FS15, ARM::S15},
264  {codeview::RegisterId::ARM_FS16, ARM::S16},
265  {codeview::RegisterId::ARM_FS17, ARM::S17},
266  {codeview::RegisterId::ARM_FS18, ARM::S18},
267  {codeview::RegisterId::ARM_FS19, ARM::S19},
268  {codeview::RegisterId::ARM_FS20, ARM::S20},
269  {codeview::RegisterId::ARM_FS21, ARM::S21},
270  {codeview::RegisterId::ARM_FS22, ARM::S22},
271  {codeview::RegisterId::ARM_FS23, ARM::S23},
272  {codeview::RegisterId::ARM_FS24, ARM::S24},
273  {codeview::RegisterId::ARM_FS25, ARM::S25},
274  {codeview::RegisterId::ARM_FS26, ARM::S26},
275  {codeview::RegisterId::ARM_FS27, ARM::S27},
276  {codeview::RegisterId::ARM_FS28, ARM::S28},
277  {codeview::RegisterId::ARM_FS29, ARM::S29},
278  {codeview::RegisterId::ARM_FS30, ARM::S30},
279  {codeview::RegisterId::ARM_FS31, ARM::S31},
280  {codeview::RegisterId::ARM_ND0, ARM::D0},
281  {codeview::RegisterId::ARM_ND1, ARM::D1},
282  {codeview::RegisterId::ARM_ND2, ARM::D2},
283  {codeview::RegisterId::ARM_ND3, ARM::D3},
284  {codeview::RegisterId::ARM_ND4, ARM::D4},
285  {codeview::RegisterId::ARM_ND5, ARM::D5},
286  {codeview::RegisterId::ARM_ND6, ARM::D6},
287  {codeview::RegisterId::ARM_ND7, ARM::D7},
288  {codeview::RegisterId::ARM_ND8, ARM::D8},
289  {codeview::RegisterId::ARM_ND9, ARM::D9},
290  {codeview::RegisterId::ARM_ND10, ARM::D10},
291  {codeview::RegisterId::ARM_ND11, ARM::D11},
292  {codeview::RegisterId::ARM_ND12, ARM::D12},
293  {codeview::RegisterId::ARM_ND13, ARM::D13},
294  {codeview::RegisterId::ARM_ND14, ARM::D14},
295  {codeview::RegisterId::ARM_ND15, ARM::D15},
296  {codeview::RegisterId::ARM_ND16, ARM::D16},
297  {codeview::RegisterId::ARM_ND17, ARM::D17},
298  {codeview::RegisterId::ARM_ND18, ARM::D18},
299  {codeview::RegisterId::ARM_ND19, ARM::D19},
300  {codeview::RegisterId::ARM_ND20, ARM::D20},
301  {codeview::RegisterId::ARM_ND21, ARM::D21},
302  {codeview::RegisterId::ARM_ND22, ARM::D22},
303  {codeview::RegisterId::ARM_ND23, ARM::D23},
304  {codeview::RegisterId::ARM_ND24, ARM::D24},
305  {codeview::RegisterId::ARM_ND25, ARM::D25},
306  {codeview::RegisterId::ARM_ND26, ARM::D26},
307  {codeview::RegisterId::ARM_ND27, ARM::D27},
308  {codeview::RegisterId::ARM_ND28, ARM::D28},
309  {codeview::RegisterId::ARM_ND29, ARM::D29},
310  {codeview::RegisterId::ARM_ND30, ARM::D30},
311  {codeview::RegisterId::ARM_ND31, ARM::D31},
312  {codeview::RegisterId::ARM_NQ0, ARM::Q0},
313  {codeview::RegisterId::ARM_NQ1, ARM::Q1},
314  {codeview::RegisterId::ARM_NQ2, ARM::Q2},
315  {codeview::RegisterId::ARM_NQ3, ARM::Q3},
316  {codeview::RegisterId::ARM_NQ4, ARM::Q4},
317  {codeview::RegisterId::ARM_NQ5, ARM::Q5},
318  {codeview::RegisterId::ARM_NQ6, ARM::Q6},
319  {codeview::RegisterId::ARM_NQ7, ARM::Q7},
320  {codeview::RegisterId::ARM_NQ8, ARM::Q8},
321  {codeview::RegisterId::ARM_NQ9, ARM::Q9},
322  {codeview::RegisterId::ARM_NQ10, ARM::Q10},
323  {codeview::RegisterId::ARM_NQ11, ARM::Q11},
324  {codeview::RegisterId::ARM_NQ12, ARM::Q12},
325  {codeview::RegisterId::ARM_NQ13, ARM::Q13},
326  {codeview::RegisterId::ARM_NQ14, ARM::Q14},
327  {codeview::RegisterId::ARM_NQ15, ARM::Q15},
328  };
329  for (const auto &I : RegMap)
330  MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
331 }
332 
335  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
337  return X;
338 }
339 
341  const Triple &TheTriple,
342  const MCTargetOptions &Options) {
343  MCAsmInfo *MAI;
344  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
345  MAI = new ARMMCAsmInfoDarwin(TheTriple);
346  else if (TheTriple.isWindowsMSVCEnvironment())
347  MAI = new ARMCOFFMCAsmInfoMicrosoft();
348  else if (TheTriple.isOSWindows())
349  MAI = new ARMCOFFMCAsmInfoGNU();
350  else
351  MAI = new ARMELFMCAsmInfo(TheTriple);
352 
353  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
355 
356  return MAI;
357 }
358 
360  std::unique_ptr<MCAsmBackend> &&MAB,
361  std::unique_ptr<MCObjectWriter> &&OW,
362  std::unique_ptr<MCCodeEmitter> &&Emitter,
363  bool RelaxAll) {
364  return createARMELFStreamer(
365  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
366  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
367  T.isAndroid());
368 }
369 
370 static MCStreamer *
371 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
372  std::unique_ptr<MCObjectWriter> &&OW,
373  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
374  bool DWARFMustBeAtTheEnd) {
375  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
376  std::move(Emitter), false, DWARFMustBeAtTheEnd);
377 }
378 
380  unsigned SyntaxVariant,
381  const MCAsmInfo &MAI,
382  const MCInstrInfo &MII,
383  const MCRegisterInfo &MRI) {
384  if (SyntaxVariant == 0)
385  return new ARMInstPrinter(MAI, MII, MRI);
386  return nullptr;
387 }
388 
390  MCContext &Ctx) {
391  if (TT.isOSBinFormatMachO())
392  return createARMMachORelocationInfo(Ctx);
393  // Default to the stock relocation info.
394  return llvm::createMCRelocationInfo(TT, Ctx);
395 }
396 
397 namespace {
398 
399 class ARMMCInstrAnalysis : public MCInstrAnalysis {
400 public:
401  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
402 
403  bool isUnconditionalBranch(const MCInst &Inst) const override {
404  // BCCs with the "always" predicate are unconditional branches.
405  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
406  return true;
408  }
409 
410  bool isConditionalBranch(const MCInst &Inst) const override {
411  // BCCs with the "always" predicate are unconditional branches.
412  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
413  return false;
415  }
416 
417  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
418  uint64_t &Target) const override {
419  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
420 
421  // Find the PC-relative immediate operand in the instruction.
422  for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
423  if (Inst.getOperand(OpNum).isImm() &&
424  Desc.OpInfo[OpNum].OperandType == MCOI::OPERAND_PCREL) {
425  int64_t Imm = Inst.getOperand(OpNum).getImm();
427  return true;
428  }
429  }
430  return false;
431  }
432 
433  Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
434  const MCSubtargetInfo *STI,
435  uint64_t Addr,
436  uint64_t Size) const override;
437 };
438 
439 } // namespace
440 
441 static Optional<uint64_t>
442 // NOLINTNEXTLINE(readability-identifier-naming)
444  unsigned MemOpIndex, uint64_t Addr) {
445  if (MemOpIndex + 1 >= Desc.getNumOperands())
446  return None;
447 
448  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
449  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
450  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
451  return None;
452 
453  int32_t OffImm = (int32_t)MO2.getImm();
454  // Special value for #-0. All others are normal.
455  if (OffImm == INT32_MIN)
456  OffImm = 0;
457  return Addr + OffImm;
458 }
459 
461  const MCInstrDesc &Desc,
462  unsigned MemOpIndex,
463  uint64_t Addr) {
464  if (MemOpIndex + 2 >= Desc.getNumOperands())
465  return None;
466 
467  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
468  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
469  const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
470  if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
471  return None;
472 
473  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
475 
476  if (Op == ARM_AM::sub)
477  return Addr - ImmOffs;
478  return Addr + ImmOffs;
479 }
480 
482  const MCInstrDesc &Desc,
483  unsigned MemOpIndex,
484  uint64_t Addr) {
485  if (MemOpIndex + 1 >= Desc.getNumOperands())
486  return None;
487 
488  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
489  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
490  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
491  return None;
492 
493  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
495 
496  if (Op == ARM_AM::sub)
497  return Addr - ImmOffs * 4;
498  return Addr + ImmOffs * 4;
499 }
500 
501 static Optional<uint64_t>
503  unsigned MemOpIndex, uint64_t Addr) {
504  if (MemOpIndex + 1 >= Desc.getNumOperands())
505  return None;
506 
507  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
508  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
509  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
510  return None;
511 
512  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
514 
515  if (Op == ARM_AM::sub)
516  return Addr - ImmOffs * 2;
517  return Addr + ImmOffs * 2;
518 }
519 
520 static Optional<uint64_t>
521 // NOLINTNEXTLINE(readability-identifier-naming)
523  unsigned MemOpIndex, uint64_t Addr) {
524  if (MemOpIndex + 1 >= Desc.getNumOperands())
525  return None;
526 
527  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
528  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
529  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
530  return None;
531 
532  int32_t OffImm = (int32_t)MO2.getImm();
533  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
534 
535  // Special value for #-0. All others are normal.
536  if (OffImm == INT32_MIN)
537  OffImm = 0;
538  return Addr + OffImm;
539 }
540 
541 static Optional<uint64_t>
542 // NOLINTNEXTLINE(readability-identifier-naming)
544  unsigned MemOpIndex, uint64_t Addr) {
545  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
546  if (!MO1.isImm())
547  return None;
548 
549  int32_t OffImm = (int32_t)MO1.getImm();
550 
551  // Special value for #-0. All others are normal.
552  if (OffImm == INT32_MIN)
553  OffImm = 0;
554  return Addr + OffImm;
555 }
556 
557 static Optional<uint64_t>
558 // NOLINTNEXTLINE(readability-identifier-naming)
560  unsigned MemOpIndex, uint64_t Addr) {
561  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
562 }
563 
564 Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
565  const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
566  uint64_t Size) const {
567  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
568 
569  // Only load instructions can have PC-relative memory addressing.
570  if (!Desc.mayLoad())
571  return None;
572 
573  // PC-relative addressing does not update the base register.
574  uint64_t TSFlags = Desc.TSFlags;
575  unsigned IndexMode =
578  return None;
579 
580  // Find the memory addressing operand in the instruction.
581  unsigned OpIndex = Desc.NumDefs;
582  while (OpIndex < Desc.getNumOperands() &&
584  ++OpIndex;
585  if (OpIndex == Desc.getNumOperands())
586  return None;
587 
588  // Base address for PC-relative addressing is always 32-bit aligned.
589  Addr &= ~0x3;
590 
591  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
592  // is 4 bytes.
593  switch (Desc.TSFlags & ARMII::FormMask) {
594  default:
595  Addr += 8;
596  break;
597  case ARMII::ThumbFrm:
598  Addr += 4;
599  break;
600  // VLDR* instructions share the same opcode (and thus the same form) for Arm
601  // and Thumb. Use a bit longer route through STI in that case.
602  case ARMII::VFPLdStFrm:
603  Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8;
604  break;
605  }
606 
607  // Eveluate the address depending on the addressing mode
608  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
609  switch (AddrMode) {
610  default:
611  return None;
612  case ARMII::AddrMode_i12:
613  return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
614  case ARMII::AddrMode3:
615  return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
616  case ARMII::AddrMode5:
617  return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
619  return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr);
621  return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
623  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
624  case ARMII::AddrModeT1_s:
625  return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
626  }
627 }
628 
630  return new ARMMCInstrAnalysis(Info);
631 }
632 
633 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
634  // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
635  // to rely on feature bits.
636  if (Coproc >= 8)
637  return false;
638  return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
639 }
640 
641 // Force static initialization.
645  // Register the MC asm info.
647 
648  // Register the MC instruction info.
650 
651  // Register the MC register info.
653 
654  // Register the MC subtarget info.
657 
661 
662  // Register the obj target streamer.
665 
666  // Register the asm streamer.
668 
669  // Register the null TargetStreamer.
671 
672  // Register the MCInstPrinter.
674 
675  // Register the MC relocation info.
677  }
678 
679  // Register the MC instruction analyzer.
683 
684  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
687  }
688  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
691  }
692 }
getARMStoreDeprecationInfo
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:90
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:223
llvm::ARMMCAsmInfoDarwin
Definition: ARMMCAsmInfo.h:23
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
evaluateMemOpAddrForAddrMode5
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:481
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
ARMTargetInfo.h
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2008
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:141
createARMMachOStreamer
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
Definition: ARMMCTargetDesc.cpp:371
llvm::ARMII::IndexModeMask
@ IndexModeMask
Definition: ARMBaseInfo.h:309
ARMMCTargetDesc.h
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::ARM::getArchName
StringRef getArchName(ArchKind AK)
Definition: ARMTargetParser.cpp:444
llvm::ARMII::AddrModeT2_pc
@ AddrModeT2_pc
Definition: ARMBaseInfo.h:202
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
ARMInstPrinter.h
MCCodeEmitter.h
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:61
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::createARMObjectTargetStreamer
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: ARMTargetStreamer.cpp:323
llvm::createARMNullTargetStreamer
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
Definition: ARMELFStreamer.cpp:1474
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition: MCRelocationInfo.h:24
ErrorHandling.h
llvm::createARMBEAsmBackend
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1320
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::createARMLEAsmBackend
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1313
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1015
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:858
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
llvm::ARM_MC::isCPSRDefined
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:175
R4
#define R4(n)
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:315
llvm::createMachOStreamer
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition: MCMachOStreamer.cpp:567
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:205
llvm::ARM_AM::getAM5FP16Op
AddrOpc getAM5FP16Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:517
llvm::Optional< uint64_t >
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:627
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:965
createARMMCInstPrinter
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: ARMMCTargetDesc.cpp:379
llvm::ARMII::IndexMode
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:177
OpIndex
unsigned OpIndex
Definition: SPIRVModuleAnalysis.cpp:41
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:982
MCELFStreamer.h
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:581
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:201
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:204
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
R2
#define R2(n)
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:205
llvm::ARM_AM::AddrOpc
AddrOpc
Definition: ARMAddressingModes.h:37
llvm::ARM_MC::evaluateBranchTarget
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
Definition: ARMMCTargetDesc.cpp:186
ARMBaseInfo.h
MCAsmBackend.h
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:169
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:508
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:669
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:48
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
createARMMCRelocationInfo
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: ARMMCTargetDesc.cpp:389
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
evaluateMemOpAddrForAddrModeT2_i8s4
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:522
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
getMRCDeprecationInfo
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:78
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:28
CodeView.h
llvm::ARMCOFFMCAsmInfoMicrosoft
Definition: ARMMCAsmInfo.h:39
llvm::None
const NoneType None
Definition: None.h:24
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1140
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
createARMMCInstrInfo
static MCInstrInfo * createARMMCInstrInfo()
Definition: ARMMCTargetDesc.cpp:217
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:435
evaluateMemOpAddrForAddrMode3
static Optional< uint64_t > evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:460
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:912
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:986
evaluateMemOpAddrForAddrMode5FP16
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:502
uint64_t
getARMLoadDeprecationInfo
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:106
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:44
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::ARMELFMCAsmInfo
Definition: ARMMCAsmInfo.h:30
evaluateMemOpAddrForAddrModeT1_s
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:559
llvm::createARMTargetAsmStreamer
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: ARMELFStreamer.cpp:1467
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::ARMII::AddrModeT1_s
@ AddrModeT1_s
Definition: ARMBaseInfo.h:196
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMII::ThumbFrm
@ ThumbFrm
Definition: ARMBaseInfo.h:360
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1021
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
MCRegisterInfo.h
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:223
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:519
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:526
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
evaluateMemOpAddrForAddrModeT2_pc
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:543
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:885
R6
#define R6(n)
llvm::MCTargetOptions
Definition: MCTargetOptions.h:42
Triple.h
llvm::createARMELFStreamer
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb, bool IsAndroid)
Definition: ARMELFStreamer.cpp:1482
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
MCInstrAnalysis.h
ARMAddressingModes.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::ARMII::VFPLdStFrm
@ VFPLdStFrm
Definition: ARMBaseInfo.h:355
llvm::Triple::thumb
@ thumb
Definition: Triple.h:83
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::createARMMachORelocationInfo
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
Definition: ARMMachORelocationInfo.cpp:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:210
llvm::createARMWinCOFFStreamer
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: ARMWinCOFFStreamer.cpp:69
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:571
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:886
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:852
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:978
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:103
createARMMCAsmInfo
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: ARMMCTargetDesc.cpp:340
uint16_t
llvm::ARMII::IndexModeNone
@ IndexModeNone
Definition: ARMBaseInfo.h:178
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:872
llvm::ARMInstPrinter
Definition: ARMInstPrinter.h:21
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:990
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
llvm::ARM_MC::createARMMCSubtargetInfo
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Definition: ARMMCTargetDesc.cpp:204
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::ARMII::IndexModeShift
@ IndexModeShift
Definition: ARMBaseInfo.h:308
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:1010
evaluateMemOpAddrForAddrMode_i12
static Optional< uint64_t > evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:443
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::ARM_AM::getAM5FP16Offset
unsigned char getAM5FP16Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:514
getMCRDeprecationInfo
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:39
LLVMInitializeARMTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()
Definition: ARMMCTargetDesc.cpp:642
llvm::Triple::thumbeb
@ thumbeb
Definition: Triple.h:84
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ARMCOFFMCAsmInfoGNU
Definition: ARMMCAsmInfo.h:46
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2013
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:633
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
createARMMCRegisterInfo
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Definition: ARMMCTargetDesc.cpp:333
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition: TargetRegistry.h:1035
createARMMCInstrAnalysis
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
Definition: ARMMCTargetDesc.cpp:629
ARMMCAsmInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69