LLVM  14.0.0git
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38 
40  std::string &Info) {
41  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44  // Checks for the deprecated CP15ISB encoding:
45  // mcr p15, #0, rX, c7, c5, #4
46  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49  Info = "deprecated since v7, use 'isb'";
50  return true;
51  }
52 
53  // Checks for the deprecated CP15DSB encoding:
54  // mcr p15, #0, rX, c7, c10, #4
55  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56  Info = "deprecated since v7, use 'dsb'";
57  return true;
58  }
59  }
60  // Checks for the deprecated CP15DMB encoding:
61  // mcr p15, #0, rX, c7, c10, #5
62  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64  Info = "deprecated since v7, use 'dmb'";
65  return true;
66  }
67  }
68  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72  "point instructions";
73  return true;
74  }
75  return false;
76 }
77 
79  std::string &Info) {
80  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84  "point instructions";
85  return true;
86  }
87  return false;
88 }
89 
90 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91  std::string &Info) {
92  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
93  MI.getOperand(1).getImm() != 8) {
94  Info = "applying IT instruction to more than one subsequent instruction is "
95  "deprecated";
96  return true;
97  }
98 
99  return false;
100 }
101 
103  std::string &Info) {
104  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
105  "cannot predicate thumb instructions");
106 
107  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
108  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
109  assert(MI.getOperand(OI).isReg() && "expected register");
110  if (MI.getOperand(OI).getReg() == ARM::PC) {
111  Info = "use of PC in the list is deprecated";
112  return true;
113  }
114  }
115  return false;
116 }
117 
119  std::string &Info) {
120  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
121  "cannot predicate thumb instructions");
122 
123  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
124  bool ListContainsPC = false, ListContainsLR = false;
125  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
126  assert(MI.getOperand(OI).isReg() && "expected register");
127  switch (MI.getOperand(OI).getReg()) {
128  default:
129  break;
130  case ARM::LR:
131  ListContainsLR = true;
132  break;
133  case ARM::PC:
134  ListContainsPC = true;
135  break;
136  }
137  }
138 
139  if (ListContainsPC && ListContainsLR) {
140  Info = "use of LR and PC simultaneously in the list is deprecated";
141  return true;
142  }
143 
144  return false;
145 }
146 
147 #define GET_INSTRINFO_MC_DESC
148 #include "ARMGenInstrInfo.inc"
149 
150 #define GET_SUBTARGETINFO_MC_DESC
151 #include "ARMGenSubtargetInfo.inc"
152 
153 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
154  std::string ARMArchFeature;
155 
156  ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
157  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
158  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
159 
160  if (TT.isThumb()) {
161  if (!ARMArchFeature.empty())
162  ARMArchFeature += ",";
163  ARMArchFeature += "+thumb-mode,+v4t";
164  }
165 
166  if (TT.isOSNaCl()) {
167  if (!ARMArchFeature.empty())
168  ARMArchFeature += ",";
169  ARMArchFeature += "+nacl-trap";
170  }
171 
172  if (TT.isOSWindows()) {
173  if (!ARMArchFeature.empty())
174  ARMArchFeature += ",";
175  ARMArchFeature += "+noarm";
176  }
177 
178  return ARMArchFeature;
179 }
180 
181 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
182  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
183  int PredOpIdx = Desc.findFirstPredOperandIdx();
184  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
185 }
186 
187 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
188  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
189  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
190  const MCOperand &MO = MI.getOperand(I);
191  if (MO.isReg() && MO.getReg() == ARM::CPSR &&
192  Desc.OpInfo[I].isOptionalDef())
193  return true;
194  }
195  return false;
196 }
197 
199  uint64_t Addr, int64_t Imm) {
200  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
201  // is 4 bytes.
202  uint64_t Offset =
203  ((InstDesc.TSFlags & ARMII::FormMask) == ARMII::ThumbFrm) ? 4 : 8;
204 
205  // A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
206  // which is 32-bit aligned. The target address for the case is calculated as
207  // targetAddress = Align(PC,4) + imm32;
208  // where
209  // Align(x, y) = y * (x DIV y);
210  if (InstDesc.getOpcode() == ARM::tBLXi)
211  Addr &= ~0x3;
212 
213  return Addr + Imm + Offset;
214 }
215 
217  StringRef CPU, StringRef FS) {
218  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
219  if (!FS.empty()) {
220  if (!ArchFS.empty())
221  ArchFS = (Twine(ArchFS) + "," + FS).str();
222  else
223  ArchFS = std::string(FS);
224  }
225 
226  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
227 }
228 
230  MCInstrInfo *X = new MCInstrInfo();
231  InitARMMCInstrInfo(X);
232  return X;
233 }
234 
236  // Mapping from CodeView to MC register id.
237  static const struct {
238  codeview::RegisterId CVReg;
239  MCPhysReg Reg;
240  } RegMap[] = {
241  {codeview::RegisterId::ARM_R0, ARM::R0},
242  {codeview::RegisterId::ARM_R1, ARM::R1},
243  {codeview::RegisterId::ARM_R2, ARM::R2},
244  {codeview::RegisterId::ARM_R3, ARM::R3},
245  {codeview::RegisterId::ARM_R4, ARM::R4},
246  {codeview::RegisterId::ARM_R5, ARM::R5},
247  {codeview::RegisterId::ARM_R6, ARM::R6},
248  {codeview::RegisterId::ARM_R7, ARM::R7},
249  {codeview::RegisterId::ARM_R8, ARM::R8},
250  {codeview::RegisterId::ARM_R9, ARM::R9},
251  {codeview::RegisterId::ARM_R10, ARM::R10},
252  {codeview::RegisterId::ARM_R11, ARM::R11},
253  {codeview::RegisterId::ARM_R12, ARM::R12},
254  {codeview::RegisterId::ARM_SP, ARM::SP},
255  {codeview::RegisterId::ARM_LR, ARM::LR},
256  {codeview::RegisterId::ARM_PC, ARM::PC},
257  {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
258  {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
259  {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
260  {codeview::RegisterId::ARM_FS0, ARM::S0},
261  {codeview::RegisterId::ARM_FS1, ARM::S1},
262  {codeview::RegisterId::ARM_FS2, ARM::S2},
263  {codeview::RegisterId::ARM_FS3, ARM::S3},
264  {codeview::RegisterId::ARM_FS4, ARM::S4},
265  {codeview::RegisterId::ARM_FS5, ARM::S5},
266  {codeview::RegisterId::ARM_FS6, ARM::S6},
267  {codeview::RegisterId::ARM_FS7, ARM::S7},
268  {codeview::RegisterId::ARM_FS8, ARM::S8},
269  {codeview::RegisterId::ARM_FS9, ARM::S9},
270  {codeview::RegisterId::ARM_FS10, ARM::S10},
271  {codeview::RegisterId::ARM_FS11, ARM::S11},
272  {codeview::RegisterId::ARM_FS12, ARM::S12},
273  {codeview::RegisterId::ARM_FS13, ARM::S13},
274  {codeview::RegisterId::ARM_FS14, ARM::S14},
275  {codeview::RegisterId::ARM_FS15, ARM::S15},
276  {codeview::RegisterId::ARM_FS16, ARM::S16},
277  {codeview::RegisterId::ARM_FS17, ARM::S17},
278  {codeview::RegisterId::ARM_FS18, ARM::S18},
279  {codeview::RegisterId::ARM_FS19, ARM::S19},
280  {codeview::RegisterId::ARM_FS20, ARM::S20},
281  {codeview::RegisterId::ARM_FS21, ARM::S21},
282  {codeview::RegisterId::ARM_FS22, ARM::S22},
283  {codeview::RegisterId::ARM_FS23, ARM::S23},
284  {codeview::RegisterId::ARM_FS24, ARM::S24},
285  {codeview::RegisterId::ARM_FS25, ARM::S25},
286  {codeview::RegisterId::ARM_FS26, ARM::S26},
287  {codeview::RegisterId::ARM_FS27, ARM::S27},
288  {codeview::RegisterId::ARM_FS28, ARM::S28},
289  {codeview::RegisterId::ARM_FS29, ARM::S29},
290  {codeview::RegisterId::ARM_FS30, ARM::S30},
291  {codeview::RegisterId::ARM_FS31, ARM::S31},
292  {codeview::RegisterId::ARM_ND0, ARM::D0},
293  {codeview::RegisterId::ARM_ND1, ARM::D1},
294  {codeview::RegisterId::ARM_ND2, ARM::D2},
295  {codeview::RegisterId::ARM_ND3, ARM::D3},
296  {codeview::RegisterId::ARM_ND4, ARM::D4},
297  {codeview::RegisterId::ARM_ND5, ARM::D5},
298  {codeview::RegisterId::ARM_ND6, ARM::D6},
299  {codeview::RegisterId::ARM_ND7, ARM::D7},
300  {codeview::RegisterId::ARM_ND8, ARM::D8},
301  {codeview::RegisterId::ARM_ND9, ARM::D9},
302  {codeview::RegisterId::ARM_ND10, ARM::D10},
303  {codeview::RegisterId::ARM_ND11, ARM::D11},
304  {codeview::RegisterId::ARM_ND12, ARM::D12},
305  {codeview::RegisterId::ARM_ND13, ARM::D13},
306  {codeview::RegisterId::ARM_ND14, ARM::D14},
307  {codeview::RegisterId::ARM_ND15, ARM::D15},
308  {codeview::RegisterId::ARM_ND16, ARM::D16},
309  {codeview::RegisterId::ARM_ND17, ARM::D17},
310  {codeview::RegisterId::ARM_ND18, ARM::D18},
311  {codeview::RegisterId::ARM_ND19, ARM::D19},
312  {codeview::RegisterId::ARM_ND20, ARM::D20},
313  {codeview::RegisterId::ARM_ND21, ARM::D21},
314  {codeview::RegisterId::ARM_ND22, ARM::D22},
315  {codeview::RegisterId::ARM_ND23, ARM::D23},
316  {codeview::RegisterId::ARM_ND24, ARM::D24},
317  {codeview::RegisterId::ARM_ND25, ARM::D25},
318  {codeview::RegisterId::ARM_ND26, ARM::D26},
319  {codeview::RegisterId::ARM_ND27, ARM::D27},
320  {codeview::RegisterId::ARM_ND28, ARM::D28},
321  {codeview::RegisterId::ARM_ND29, ARM::D29},
322  {codeview::RegisterId::ARM_ND30, ARM::D30},
323  {codeview::RegisterId::ARM_ND31, ARM::D31},
324  {codeview::RegisterId::ARM_NQ0, ARM::Q0},
325  {codeview::RegisterId::ARM_NQ1, ARM::Q1},
326  {codeview::RegisterId::ARM_NQ2, ARM::Q2},
327  {codeview::RegisterId::ARM_NQ3, ARM::Q3},
328  {codeview::RegisterId::ARM_NQ4, ARM::Q4},
329  {codeview::RegisterId::ARM_NQ5, ARM::Q5},
330  {codeview::RegisterId::ARM_NQ6, ARM::Q6},
331  {codeview::RegisterId::ARM_NQ7, ARM::Q7},
332  {codeview::RegisterId::ARM_NQ8, ARM::Q8},
333  {codeview::RegisterId::ARM_NQ9, ARM::Q9},
334  {codeview::RegisterId::ARM_NQ10, ARM::Q10},
335  {codeview::RegisterId::ARM_NQ11, ARM::Q11},
336  {codeview::RegisterId::ARM_NQ12, ARM::Q12},
337  {codeview::RegisterId::ARM_NQ13, ARM::Q13},
338  {codeview::RegisterId::ARM_NQ14, ARM::Q14},
339  {codeview::RegisterId::ARM_NQ15, ARM::Q15},
340  };
341  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
342  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
343 }
344 
347  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
349  return X;
350 }
351 
353  const Triple &TheTriple,
354  const MCTargetOptions &Options) {
355  MCAsmInfo *MAI;
356  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
357  MAI = new ARMMCAsmInfoDarwin(TheTriple);
358  else if (TheTriple.isWindowsMSVCEnvironment())
359  MAI = new ARMCOFFMCAsmInfoMicrosoft();
360  else if (TheTriple.isOSWindows())
361  MAI = new ARMCOFFMCAsmInfoGNU();
362  else
363  MAI = new ARMELFMCAsmInfo(TheTriple);
364 
365  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
367 
368  return MAI;
369 }
370 
372  std::unique_ptr<MCAsmBackend> &&MAB,
373  std::unique_ptr<MCObjectWriter> &&OW,
374  std::unique_ptr<MCCodeEmitter> &&Emitter,
375  bool RelaxAll) {
376  return createARMELFStreamer(
377  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
378  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
379  T.isAndroid());
380 }
381 
382 static MCStreamer *
383 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
384  std::unique_ptr<MCObjectWriter> &&OW,
385  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
386  bool DWARFMustBeAtTheEnd) {
387  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
388  std::move(Emitter), false, DWARFMustBeAtTheEnd);
389 }
390 
392  unsigned SyntaxVariant,
393  const MCAsmInfo &MAI,
394  const MCInstrInfo &MII,
395  const MCRegisterInfo &MRI) {
396  if (SyntaxVariant == 0)
397  return new ARMInstPrinter(MAI, MII, MRI);
398  return nullptr;
399 }
400 
402  MCContext &Ctx) {
403  if (TT.isOSBinFormatMachO())
404  return createARMMachORelocationInfo(Ctx);
405  // Default to the stock relocation info.
406  return llvm::createMCRelocationInfo(TT, Ctx);
407 }
408 
409 namespace {
410 
411 class ARMMCInstrAnalysis : public MCInstrAnalysis {
412 public:
413  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
414 
415  bool isUnconditionalBranch(const MCInst &Inst) const override {
416  // BCCs with the "always" predicate are unconditional branches.
417  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
418  return true;
420  }
421 
422  bool isConditionalBranch(const MCInst &Inst) const override {
423  // BCCs with the "always" predicate are unconditional branches.
424  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
425  return false;
427  }
428 
429  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
430  uint64_t &Target) const override {
431  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
432 
433  // Find the PC-relative immediate operand in the instruction.
434  for (unsigned OpNum = 0; OpNum < Desc.getNumOperands(); ++OpNum) {
435  if (Inst.getOperand(OpNum).isImm() &&
436  Desc.OpInfo[OpNum].OperandType == MCOI::OPERAND_PCREL) {
437  int64_t Imm = Inst.getOperand(OpNum).getImm();
439  return true;
440  }
441  }
442  return false;
443  }
444 
445  Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
446  const MCSubtargetInfo *STI,
447  uint64_t Addr,
448  uint64_t Size) const override;
449 };
450 
451 } // namespace
452 
453 static Optional<uint64_t>
454 // NOLINTNEXTLINE(readability-identifier-naming)
456  unsigned MemOpIndex, uint64_t Addr) {
457  if (MemOpIndex + 1 >= Desc.getNumOperands())
458  return None;
459 
460  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
461  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
462  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
463  return None;
464 
465  int32_t OffImm = (int32_t)MO2.getImm();
466  // Special value for #-0. All others are normal.
467  if (OffImm == INT32_MIN)
468  OffImm = 0;
469  return Addr + OffImm;
470 }
471 
473  const MCInstrDesc &Desc,
474  unsigned MemOpIndex,
475  uint64_t Addr) {
476  if (MemOpIndex + 2 >= Desc.getNumOperands())
477  return None;
478 
479  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
480  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
481  const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
482  if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
483  return None;
484 
485  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
487 
488  if (Op == ARM_AM::sub)
489  return Addr - ImmOffs;
490  return Addr + ImmOffs;
491 }
492 
494  const MCInstrDesc &Desc,
495  unsigned MemOpIndex,
496  uint64_t Addr) {
497  if (MemOpIndex + 1 >= Desc.getNumOperands())
498  return None;
499 
500  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
501  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
502  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
503  return None;
504 
505  unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
507 
508  if (Op == ARM_AM::sub)
509  return Addr - ImmOffs * 4;
510  return Addr + ImmOffs * 4;
511 }
512 
513 static Optional<uint64_t>
515  unsigned MemOpIndex, uint64_t Addr) {
516  if (MemOpIndex + 1 >= Desc.getNumOperands())
517  return None;
518 
519  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
520  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
521  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
522  return None;
523 
524  unsigned ImmOffs = ARM_AM::getAM5FP16Offset(MO2.getImm());
526 
527  if (Op == ARM_AM::sub)
528  return Addr - ImmOffs * 2;
529  return Addr + ImmOffs * 2;
530 }
531 
532 static Optional<uint64_t>
533 // NOLINTNEXTLINE(readability-identifier-naming)
535  unsigned MemOpIndex, uint64_t Addr) {
536  if (MemOpIndex + 1 >= Desc.getNumOperands())
537  return None;
538 
539  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
540  const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
541  if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
542  return None;
543 
544  int32_t OffImm = (int32_t)MO2.getImm();
545  assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
546 
547  // Special value for #-0. All others are normal.
548  if (OffImm == INT32_MIN)
549  OffImm = 0;
550  return Addr + OffImm;
551 }
552 
553 static Optional<uint64_t>
554 // NOLINTNEXTLINE(readability-identifier-naming)
556  unsigned MemOpIndex, uint64_t Addr) {
557  const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
558  if (!MO1.isImm())
559  return None;
560 
561  int32_t OffImm = (int32_t)MO1.getImm();
562 
563  // Special value for #-0. All others are normal.
564  if (OffImm == INT32_MIN)
565  OffImm = 0;
566  return Addr + OffImm;
567 }
568 
569 static Optional<uint64_t>
570 // NOLINTNEXTLINE(readability-identifier-naming)
572  unsigned MemOpIndex, uint64_t Addr) {
573  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
574 }
575 
576 Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
577  const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr,
578  uint64_t Size) const {
579  const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
580 
581  // Only load instructions can have PC-relative memory addressing.
582  if (!Desc.mayLoad())
583  return None;
584 
585  // PC-relative addressing does not update the base register.
586  uint64_t TSFlags = Desc.TSFlags;
587  unsigned IndexMode =
590  return None;
591 
592  // Find the memory addressing operand in the instruction.
593  unsigned OpIndex = Desc.NumDefs;
594  while (OpIndex < Desc.getNumOperands() &&
595  Desc.OpInfo[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
596  ++OpIndex;
597  if (OpIndex == Desc.getNumOperands())
598  return None;
599 
600  // Base address for PC-relative addressing is always 32-bit aligned.
601  Addr &= ~0x3;
602 
603  // For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
604  // is 4 bytes.
605  switch (Desc.TSFlags & ARMII::FormMask) {
606  default:
607  Addr += 8;
608  break;
609  case ARMII::ThumbFrm:
610  Addr += 4;
611  break;
612  // VLDR* instructions share the same opcode (and thus the same form) for Arm
613  // and Thumb. Use a bit longer route through STI in that case.
614  case ARMII::VFPLdStFrm:
615  Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8;
616  break;
617  }
618 
619  // Eveluate the address depending on the addressing mode
620  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
621  switch (AddrMode) {
622  default:
623  return None;
624  case ARMII::AddrMode_i12:
625  return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
626  case ARMII::AddrMode3:
627  return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
628  case ARMII::AddrMode5:
629  return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
631  return evaluateMemOpAddrForAddrMode5FP16(Inst, Desc, OpIndex, Addr);
633  return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
635  return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
636  case ARMII::AddrModeT1_s:
637  return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
638  }
639 }
640 
642  return new ARMMCInstrAnalysis(Info);
643 }
644 
645 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
646  // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
647  // to rely on feature bits.
648  if (Coproc >= 8)
649  return false;
650  return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
651 }
652 
653 // Force static initialization.
657  // Register the MC asm info.
659 
660  // Register the MC instruction info.
662 
663  // Register the MC register info.
665 
666  // Register the MC subtarget info.
669 
673 
674  // Register the obj target streamer.
677 
678  // Register the asm streamer.
680 
681  // Register the null TargetStreamer.
683 
684  // Register the MCInstPrinter.
686 
687  // Register the MC relocation info.
689  }
690 
691  // Register the MC instruction analyzer.
695 
696  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
699  }
700  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
703  }
704 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
getARMStoreDeprecationInfo
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:102
llvm::MCInstrDesc::getOpcode
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:221
llvm::ARMMCAsmInfoDarwin
Definition: ARMMCAsmInfo.h:23
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
evaluateMemOpAddrForAddrMode5
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:493
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
ARMTargetInfo.h
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::ARM_AM::getAM3Offset
unsigned char getAM3Offset(unsigned AM3Opc)
Definition: ARMAddressingModes.h:450
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:153
createARMMachOStreamer
static MCStreamer * createARMMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool DWARFMustBeAtTheEnd)
Definition: ARMMCTargetDesc.cpp:383
ARMMCTargetDesc.h
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
llvm::ARM::getArchName
StringRef getArchName(ArchKind AK)
Definition: ARMTargetParser.cpp:428
llvm::ARMII::AddrModeT2_pc
@ AddrModeT2_pc
Definition: ARMBaseInfo.h:200
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
ARMInstPrinter.h
MCCodeEmitter.h
llvm::MCOI::OPERAND_MEMORY
@ OPERAND_MEMORY
Definition: MCInstrDesc.h:60
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:201
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::createARMObjectTargetStreamer
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: ARMELFStreamer.cpp:1339
llvm::createARMNullTargetStreamer
MCTargetStreamer * createARMNullTargetStreamer(MCStreamer &S)
Definition: ARMELFStreamer.cpp:1335
llvm::MCRelocationInfo
Create MCExprs from relocations found in an object file.
Definition: MCRelocationInfo.h:24
ErrorHandling.h
llvm::createARMBEAsmBackend
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1321
llvm::createARMLEAsmBackend
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: ARMAsmBackend.cpp:1314
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:823
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::ARM_AM::getAM3Op
AddrOpc getAM3Op(unsigned AM3Opc)
Definition: ARMAddressingModes.h:451
llvm::ARM_MC::isCPSRDefined
bool isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:187
R4
#define R4(n)
llvm::createMachOStreamer
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
Definition: MCMachOStreamer.cpp:509
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:203
llvm::ARM_AM::getAM5FP16Op
AddrOpc getAM5FP16Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:517
llvm::Optional< uint64_t >
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:621
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:930
createARMMCInstPrinter
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: ARMMCTargetDesc.cpp:391
llvm::ARMII::IndexMode
IndexMode
ARM Index Modes.
Definition: ARMBaseInfo.h:177
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:947
MCELFStreamer.h
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:557
llvm::MCInstrDesc::NumDefs
unsigned char NumDefs
Definition: MCInstrDesc.h:199
llvm::ARM_AM::getAM5Op
AddrOpc getAM5Op(unsigned AM5Opc)
Definition: ARMAddressingModes.h:494
llvm::ARMII::FormMask
@ FormMask
Definition: ARMBaseInfo.h:311
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:202
x3
In x86 we generate this spiffy xmm0 xmm0 ret in x86 we generate this which could be xmm1 movss xmm1 xmm0 ret In sse4 we could use insertps to make both better Here s another testcase that could use x3
Definition: README-SSE.txt:547
R2
#define R2(n)
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2014
llvm::MCInstrDesc::TSFlags
uint64_t TSFlags
Definition: MCInstrDesc.h:203
llvm::ARM_AM::AddrOpc
AddrOpc
Definition: ARMAddressingModes.h:37
llvm::ARM_MC::evaluateBranchTarget
uint64_t evaluateBranchTarget(const MCInstrDesc &InstDesc, uint64_t Addr, int64_t Imm)
Definition: ARMMCTargetDesc.cpp:198
ARMBaseInfo.h
MCAsmBackend.h
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:181
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:484
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:645
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:45
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
createARMMCRelocationInfo
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: ARMMCTargetDesc.cpp:401
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2008
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
evaluateMemOpAddrForAddrModeT2_i8s4
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:534
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:61
getMRCDeprecationInfo
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:78
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:28
CodeView.h
llvm::ARMCOFFMCAsmInfoMicrosoft
Definition: ARMMCAsmInfo.h:39
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1390
llvm::None
const NoneType None
Definition: None.h:23
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1097
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
createARMMCInstrInfo
static MCInstrInfo * createARMMCInstrInfo()
Definition: ARMMCTargetDesc.cpp:229
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:111
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MCInstrDesc::mayLoad
bool mayLoad() const
Return true if this instruction could possibly read memory.
Definition: MCInstrDesc.h:429
evaluateMemOpAddrForAddrMode3
static Optional< uint64_t > evaluateMemOpAddrForAddrMode3(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:472
llvm::ARMII::IndexModeMask
@ IndexModeMask
Definition: ARMBaseInfo.h:305
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:877
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:951
evaluateMemOpAddrForAddrMode5FP16
static Optional< uint64_t > evaluateMemOpAddrForAddrMode5FP16(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:514
uint64_t
getARMLoadDeprecationInfo
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:118
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:41
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ARMELFMCAsmInfo
Definition: ARMMCAsmInfo.h:30
evaluateMemOpAddrForAddrModeT1_s
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:571
llvm::createARMTargetAsmStreamer
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: ARMELFStreamer.cpp:1328
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
llvm::ARMII::AddrModeT1_s
@ AddrModeT1_s
Definition: ARMBaseInfo.h:196
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::ARMII::ThumbFrm
@ ThumbFrm
Definition: ARMBaseInfo.h:356
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:978
MCRegisterInfo.h
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:235
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:299
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:517
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:86
evaluateMemOpAddrForAddrModeT2_pc
static Optional< uint64_t > evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:555
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:850
R6
#define R6(n)
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
Triple.h
llvm::createARMELFStreamer
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb, bool IsAndroid)
Definition: ARMELFStreamer.cpp:1347
llvm::ARM_AM::sub
@ sub
Definition: ARMAddressingModes.h:38
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
MCInstrAnalysis.h
ARMAddressingModes.h
getITDeprecationInfo
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:90
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::Triple::thumb
@ thumb
Definition: Triple.h:81
AddrMode
AddrMode
Definition: MSP430Disassembler.cpp:142
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::createARMMachORelocationInfo
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
Definition: ARMMachORelocationInfo.cpp:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:211
llvm::createARMWinCOFFStreamer
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: ARMWinCOFFStreamer.cpp:40
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:547
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:888
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:817
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:943
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:104
llvm::ARMII::VFPLdStFrm
@ VFPLdStFrm
Definition: ARMBaseInfo.h:351
createARMMCAsmInfo
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: ARMMCTargetDesc.cpp:352
uint16_t
llvm::ARMII::IndexModeNone
@ IndexModeNone
Definition: ARMBaseInfo.h:178
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:837
llvm::ARMInstPrinter
Definition: ARMInstPrinter.h:21
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:955
llvm::ARM_AM::getAM5Offset
unsigned char getAM5Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:493
llvm::ARM_MC::createARMMCSubtargetInfo
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Definition: ARMMCTargetDesc.cpp:216
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:967
evaluateMemOpAddrForAddrMode_i12
static Optional< uint64_t > evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc, unsigned MemOpIndex, uint64_t Addr)
Definition: ARMMCTargetDesc.cpp:455
llvm::ARM_AM::getAM5FP16Offset
unsigned char getAM5FP16Offset(unsigned AM5Opc)
Definition: ARMAddressingModes.h:514
getMCRDeprecationInfo
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:39
LLVMInitializeARMTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()
Definition: ARMMCTargetDesc.cpp:654
llvm::Triple::thumbeb
@ thumbeb
Definition: Triple.h:82
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::ARMCOFFMCAsmInfoGNU
Definition: ARMMCAsmInfo.h:46
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:645
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::ARMII::IndexModeShift
@ IndexModeShift
Definition: ARMBaseInfo.h:304
createARMMCRegisterInfo
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Definition: ARMMCTargetDesc.cpp:345
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition: TargetRegistry.h:992
createARMMCInstrAnalysis
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
Definition: ARMMCTargetDesc.cpp:641
ARMMCAsmInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69