36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
42 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 15) &&
43 (
MI.getOperand(1).isImm() &&
MI.getOperand(1).getImm() == 0) &&
46 (
MI.getOperand(3).isImm() &&
MI.getOperand(3).getImm() == 7)) {
47 if ((
MI.getOperand(5).isImm() &&
MI.getOperand(5).getImm() == 4)) {
48 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 5) {
49 Info =
"deprecated since v7, use 'isb'";
55 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 10) {
56 Info =
"deprecated since v7, use 'dsb'";
62 if (
MI.getOperand(4).isImm() &&
MI.getOperand(4).getImm() == 10 &&
63 (
MI.getOperand(5).isImm() &&
MI.getOperand(5).getImm() == 5)) {
64 Info =
"deprecated since v7, use 'dmb'";
69 ((
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 10) ||
70 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 11))) {
71 Info =
"since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
81 ((
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 10) ||
82 (
MI.getOperand(0).isImm() &&
MI.getOperand(0).getImm() == 11))) {
83 Info =
"since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
93 "cannot predicate thumb instructions");
95 assert(
MI.getNumOperands() >= 4 &&
"expected >= 4 arguments");
96 for (
unsigned OI = 4, OE =
MI.getNumOperands(); OI < OE; ++OI) {
97 assert(
MI.getOperand(OI).isReg() &&
"expected register");
98 if (
MI.getOperand(OI).getReg() == ARM::PC) {
99 Info =
"use of PC in the list is deprecated";
109 "cannot predicate thumb instructions");
111 assert(
MI.getNumOperands() >= 4 &&
"expected >= 4 arguments");
112 bool ListContainsPC =
false, ListContainsLR =
false;
113 for (
unsigned OI = 4, OE =
MI.getNumOperands(); OI < OE; ++OI) {
114 assert(
MI.getOperand(OI).isReg() &&
"expected register");
115 switch (
MI.getOperand(OI).getReg()) {
119 ListContainsLR =
true;
122 ListContainsPC =
true;
127 if (ListContainsPC && ListContainsLR) {
128 Info =
"use of LR and PC simultaneously in the list is deprecated";
135 #define GET_INSTRINFO_MC_DESC
136 #include "ARMGenInstrInfo.inc"
138 #define GET_SUBTARGETINFO_MC_DESC
139 #include "ARMGenSubtargetInfo.inc"
142 std::string ARMArchFeature;
145 if (ArchID != ARM::ArchKind::INVALID && (CPU.
empty() || CPU ==
"generic"))
149 if (!ARMArchFeature.empty())
150 ARMArchFeature +=
",";
151 ARMArchFeature +=
"+thumb-mode,+v4t";
155 if (!ARMArchFeature.empty())
156 ARMArchFeature +=
",";
157 ARMArchFeature +=
"+nacl-trap";
160 if (TT.isOSWindows()) {
161 if (!ARMArchFeature.empty())
162 ARMArchFeature +=
",";
163 ARMArchFeature +=
"+noarm";
166 return ARMArchFeature;
172 return PredOpIdx != -1 &&
MI.getOperand(PredOpIdx).getImm() !=
ARMCC::AL;
177 for (
unsigned I = 0;
I <
MI.getNumOperands(); ++
I) {
209 ArchFS = (
Twine(ArchFS) +
"," +
FS).str();
211 ArchFS = std::string(
FS);
214 return createARMMCSubtargetInfoImpl(TT, CPU, CPU, ArchFS);
219 InitARMMCInstrInfo(
X);
225 static const struct {
229 {codeview::RegisterId::ARM_R0, ARM::R0},
230 {codeview::RegisterId::ARM_R1, ARM::R1},
231 {codeview::RegisterId::ARM_R2,
ARM::R2},
232 {codeview::RegisterId::ARM_R3, ARM::R3},
233 {codeview::RegisterId::ARM_R4,
ARM::R4},
234 {codeview::RegisterId::ARM_R5, ARM::R5},
235 {codeview::RegisterId::ARM_R6,
ARM::R6},
236 {codeview::RegisterId::ARM_R7, ARM::R7},
237 {codeview::RegisterId::ARM_R8, ARM::R8},
238 {codeview::RegisterId::ARM_R9, ARM::R9},
239 {codeview::RegisterId::ARM_R10, ARM::R10},
240 {codeview::RegisterId::ARM_R11, ARM::R11},
241 {codeview::RegisterId::ARM_R12, ARM::R12},
242 {codeview::RegisterId::ARM_SP, ARM::SP},
243 {codeview::RegisterId::ARM_LR, ARM::LR},
244 {codeview::RegisterId::ARM_PC, ARM::PC},
245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
246 {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
247 {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
248 {codeview::RegisterId::ARM_FS0, ARM::S0},
249 {codeview::RegisterId::ARM_FS1, ARM::S1},
250 {codeview::RegisterId::ARM_FS2, ARM::S2},
251 {codeview::RegisterId::ARM_FS3, ARM::S3},
252 {codeview::RegisterId::ARM_FS4, ARM::S4},
253 {codeview::RegisterId::ARM_FS5, ARM::S5},
254 {codeview::RegisterId::ARM_FS6, ARM::S6},
255 {codeview::RegisterId::ARM_FS7, ARM::S7},
256 {codeview::RegisterId::ARM_FS8, ARM::S8},
257 {codeview::RegisterId::ARM_FS9, ARM::S9},
258 {codeview::RegisterId::ARM_FS10, ARM::S10},
259 {codeview::RegisterId::ARM_FS11, ARM::S11},
260 {codeview::RegisterId::ARM_FS12, ARM::S12},
261 {codeview::RegisterId::ARM_FS13, ARM::S13},
262 {codeview::RegisterId::ARM_FS14, ARM::S14},
263 {codeview::RegisterId::ARM_FS15, ARM::S15},
264 {codeview::RegisterId::ARM_FS16, ARM::S16},
265 {codeview::RegisterId::ARM_FS17, ARM::S17},
266 {codeview::RegisterId::ARM_FS18, ARM::S18},
267 {codeview::RegisterId::ARM_FS19, ARM::S19},
268 {codeview::RegisterId::ARM_FS20, ARM::S20},
269 {codeview::RegisterId::ARM_FS21, ARM::S21},
270 {codeview::RegisterId::ARM_FS22, ARM::S22},
271 {codeview::RegisterId::ARM_FS23, ARM::S23},
272 {codeview::RegisterId::ARM_FS24, ARM::S24},
273 {codeview::RegisterId::ARM_FS25, ARM::S25},
274 {codeview::RegisterId::ARM_FS26, ARM::S26},
275 {codeview::RegisterId::ARM_FS27, ARM::S27},
276 {codeview::RegisterId::ARM_FS28, ARM::S28},
277 {codeview::RegisterId::ARM_FS29, ARM::S29},
278 {codeview::RegisterId::ARM_FS30, ARM::S30},
279 {codeview::RegisterId::ARM_FS31, ARM::S31},
280 {codeview::RegisterId::ARM_ND0, ARM::D0},
281 {codeview::RegisterId::ARM_ND1, ARM::D1},
282 {codeview::RegisterId::ARM_ND2, ARM::D2},
283 {codeview::RegisterId::ARM_ND3, ARM::D3},
284 {codeview::RegisterId::ARM_ND4, ARM::D4},
285 {codeview::RegisterId::ARM_ND5, ARM::D5},
286 {codeview::RegisterId::ARM_ND6, ARM::D6},
287 {codeview::RegisterId::ARM_ND7, ARM::D7},
288 {codeview::RegisterId::ARM_ND8, ARM::D8},
289 {codeview::RegisterId::ARM_ND9, ARM::D9},
290 {codeview::RegisterId::ARM_ND10, ARM::D10},
291 {codeview::RegisterId::ARM_ND11, ARM::D11},
292 {codeview::RegisterId::ARM_ND12, ARM::D12},
293 {codeview::RegisterId::ARM_ND13, ARM::D13},
294 {codeview::RegisterId::ARM_ND14, ARM::D14},
295 {codeview::RegisterId::ARM_ND15, ARM::D15},
296 {codeview::RegisterId::ARM_ND16, ARM::D16},
297 {codeview::RegisterId::ARM_ND17, ARM::D17},
298 {codeview::RegisterId::ARM_ND18, ARM::D18},
299 {codeview::RegisterId::ARM_ND19, ARM::D19},
300 {codeview::RegisterId::ARM_ND20, ARM::D20},
301 {codeview::RegisterId::ARM_ND21, ARM::D21},
302 {codeview::RegisterId::ARM_ND22, ARM::D22},
303 {codeview::RegisterId::ARM_ND23, ARM::D23},
304 {codeview::RegisterId::ARM_ND24, ARM::D24},
305 {codeview::RegisterId::ARM_ND25, ARM::D25},
306 {codeview::RegisterId::ARM_ND26, ARM::D26},
307 {codeview::RegisterId::ARM_ND27, ARM::D27},
308 {codeview::RegisterId::ARM_ND28, ARM::D28},
309 {codeview::RegisterId::ARM_ND29, ARM::D29},
310 {codeview::RegisterId::ARM_ND30, ARM::D30},
311 {codeview::RegisterId::ARM_ND31, ARM::D31},
312 {codeview::RegisterId::ARM_NQ0, ARM::Q0},
313 {codeview::RegisterId::ARM_NQ1, ARM::Q1},
314 {codeview::RegisterId::ARM_NQ2, ARM::Q2},
315 {codeview::RegisterId::ARM_NQ3, ARM::Q3},
316 {codeview::RegisterId::ARM_NQ4, ARM::Q4},
317 {codeview::RegisterId::ARM_NQ5, ARM::Q5},
318 {codeview::RegisterId::ARM_NQ6, ARM::Q6},
319 {codeview::RegisterId::ARM_NQ7, ARM::Q7},
320 {codeview::RegisterId::ARM_NQ8, ARM::Q8},
321 {codeview::RegisterId::ARM_NQ9, ARM::Q9},
322 {codeview::RegisterId::ARM_NQ10, ARM::Q10},
323 {codeview::RegisterId::ARM_NQ11, ARM::Q11},
324 {codeview::RegisterId::ARM_NQ12, ARM::Q12},
325 {codeview::RegisterId::ARM_NQ13, ARM::Q13},
326 {codeview::RegisterId::ARM_NQ14, ARM::Q14},
327 {codeview::RegisterId::ARM_NQ15, ARM::Q15},
329 for (
const auto &
I : RegMap)
330 MRI->mapLLVMRegToCVReg(
I.Reg,
static_cast<int>(
I.CVReg));
335 InitARMMCRegisterInfo(
X, ARM::LR, 0, 0, ARM::PC);
353 unsigned Reg =
MRI.getDwarfRegNum(ARM::SP,
true);
360 std::unique_ptr<MCAsmBackend> &&MAB,
361 std::unique_ptr<MCObjectWriter> &&OW,
362 std::unique_ptr<MCCodeEmitter> &&Emitter,
372 std::unique_ptr<MCObjectWriter> &&OW,
373 std::unique_ptr<MCCodeEmitter> &&Emitter,
bool RelaxAll,
374 bool DWARFMustBeAtTheEnd) {
376 std::move(Emitter),
false, DWARFMustBeAtTheEnd);
380 unsigned SyntaxVariant,
384 if (SyntaxVariant == 0)
391 if (TT.isOSBinFormatMachO())
410 bool isConditionalBranch(
const MCInst &Inst)
const override {
422 for (
unsigned OpNum = 0; OpNum < Desc.
getNumOperands(); ++OpNum) {
453 int32_t OffImm = (int32_t)MO2.
getImm();
455 if (OffImm == INT32_MIN)
457 return Addr + OffImm;
477 return Addr - ImmOffs;
478 return Addr + ImmOffs;
497 return Addr - ImmOffs * 4;
498 return Addr + ImmOffs * 4;
516 return Addr - ImmOffs * 2;
517 return Addr + ImmOffs * 2;
532 int32_t OffImm = (int32_t)MO2.
getImm();
533 assert(((OffImm & 0
x3) == 0) &&
"Not a valid immediate!");
536 if (OffImm == INT32_MIN)
538 return Addr + OffImm;
549 int32_t OffImm = (int32_t)MO1.
getImm();
552 if (OffImm == INT32_MIN)
554 return Addr + OffImm;
630 return new ARMMCInstrAnalysis(
Info);