LLVM  13.0.0git
ARMMCTargetDesc.cpp
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1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides ARM specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "ARMMCTargetDesc.h"
14 #include "ARMAddressingModes.h"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMMCAsmInfo.h"
19 #include "llvm/ADT/Triple.h"
21 #include "llvm/MC/MCAsmBackend.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCStreamer.h"
33 
34 using namespace llvm;
35 
36 #define GET_REGINFO_MC_DESC
37 #include "ARMGenRegisterInfo.inc"
38 
40  std::string &Info) {
41  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
42  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
43  (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
44  // Checks for the deprecated CP15ISB encoding:
45  // mcr p15, #0, rX, c7, c5, #4
46  (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) {
47  if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) {
48  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) {
49  Info = "deprecated since v7, use 'isb'";
50  return true;
51  }
52 
53  // Checks for the deprecated CP15DSB encoding:
54  // mcr p15, #0, rX, c7, c10, #4
55  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) {
56  Info = "deprecated since v7, use 'dsb'";
57  return true;
58  }
59  }
60  // Checks for the deprecated CP15DMB encoding:
61  // mcr p15, #0, rX, c7, c10, #5
62  if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 &&
63  (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) {
64  Info = "deprecated since v7, use 'dmb'";
65  return true;
66  }
67  }
68  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
69  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
70  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
71  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
72  "point instructions";
73  return true;
74  }
75  return false;
76 }
77 
79  std::string &Info) {
80  if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
81  ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
82  (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
83  Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
84  "point instructions";
85  return true;
86  }
87  return false;
88 }
89 
90 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
91  std::string &Info) {
92  if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
93  MI.getOperand(1).getImm() != 8) {
94  Info = "applying IT instruction to more than one subsequent instruction is "
95  "deprecated";
96  return true;
97  }
98 
99  return false;
100 }
101 
103  std::string &Info) {
104  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
105  "cannot predicate thumb instructions");
106 
107  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
108  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
109  assert(MI.getOperand(OI).isReg() && "expected register");
110  if (MI.getOperand(OI).getReg() == ARM::PC) {
111  Info = "use of PC in the list is deprecated";
112  return true;
113  }
114  }
115  return false;
116 }
117 
119  std::string &Info) {
120  assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
121  "cannot predicate thumb instructions");
122 
123  assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
124  bool ListContainsPC = false, ListContainsLR = false;
125  for (unsigned OI = 4, OE = MI.getNumOperands(); OI < OE; ++OI) {
126  assert(MI.getOperand(OI).isReg() && "expected register");
127  switch (MI.getOperand(OI).getReg()) {
128  default:
129  break;
130  case ARM::LR:
131  ListContainsLR = true;
132  break;
133  case ARM::PC:
134  ListContainsPC = true;
135  break;
136  }
137  }
138 
139  if (ListContainsPC && ListContainsLR) {
140  Info = "use of LR and PC simultaneously in the list is deprecated";
141  return true;
142  }
143 
144  return false;
145 }
146 
147 #define GET_INSTRINFO_MC_DESC
148 #include "ARMGenInstrInfo.inc"
149 
150 #define GET_SUBTARGETINFO_MC_DESC
151 #include "ARMGenSubtargetInfo.inc"
152 
153 std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
154  std::string ARMArchFeature;
155 
156  ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName());
157  if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic"))
158  ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str();
159 
160  if (TT.isThumb()) {
161  if (!ARMArchFeature.empty())
162  ARMArchFeature += ",";
163  ARMArchFeature += "+thumb-mode,+v4t";
164  }
165 
166  if (TT.isOSNaCl()) {
167  if (!ARMArchFeature.empty())
168  ARMArchFeature += ",";
169  ARMArchFeature += "+nacl-trap";
170  }
171 
172  if (TT.isOSWindows()) {
173  if (!ARMArchFeature.empty())
174  ARMArchFeature += ",";
175  ARMArchFeature += "+noarm";
176  }
177 
178  return ARMArchFeature;
179 }
180 
181 bool ARM_MC::isPredicated(const MCInst &MI, const MCInstrInfo *MCII) {
182  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
183  int PredOpIdx = Desc.findFirstPredOperandIdx();
184  return PredOpIdx != -1 && MI.getOperand(PredOpIdx).getImm() != ARMCC::AL;
185 }
186 
187 bool ARM_MC::isCPSRDefined(const MCInst &MI, const MCInstrInfo *MCII) {
188  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
189  for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
190  const MCOperand &MO = MI.getOperand(I);
191  if (MO.isReg() && MO.getReg() == ARM::CPSR &&
192  Desc.OpInfo[I].isOptionalDef())
193  return true;
194  }
195  return false;
196 }
197 
199  StringRef CPU, StringRef FS) {
200  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
201  if (!FS.empty()) {
202  if (!ArchFS.empty())
203  ArchFS = (Twine(ArchFS) + "," + FS).str();
204  else
205  ArchFS = std::string(FS);
206  }
207 
208  return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
209 }
210 
212  MCInstrInfo *X = new MCInstrInfo();
213  InitARMMCInstrInfo(X);
214  return X;
215 }
216 
218  // Mapping from CodeView to MC register id.
219  static const struct {
220  codeview::RegisterId CVReg;
221  MCPhysReg Reg;
222  } RegMap[] = {
223  {codeview::RegisterId::ARM_R0, ARM::R0},
224  {codeview::RegisterId::ARM_R1, ARM::R1},
225  {codeview::RegisterId::ARM_R2, ARM::R2},
226  {codeview::RegisterId::ARM_R3, ARM::R3},
227  {codeview::RegisterId::ARM_R4, ARM::R4},
228  {codeview::RegisterId::ARM_R5, ARM::R5},
229  {codeview::RegisterId::ARM_R6, ARM::R6},
230  {codeview::RegisterId::ARM_R7, ARM::R7},
231  {codeview::RegisterId::ARM_R8, ARM::R8},
232  {codeview::RegisterId::ARM_R9, ARM::R9},
233  {codeview::RegisterId::ARM_R10, ARM::R10},
234  {codeview::RegisterId::ARM_R11, ARM::R11},
235  {codeview::RegisterId::ARM_R12, ARM::R12},
236  {codeview::RegisterId::ARM_SP, ARM::SP},
237  {codeview::RegisterId::ARM_LR, ARM::LR},
238  {codeview::RegisterId::ARM_PC, ARM::PC},
239  {codeview::RegisterId::ARM_CPSR, ARM::CPSR},
240  {codeview::RegisterId::ARM_FPSCR, ARM::FPSCR},
241  {codeview::RegisterId::ARM_FPEXC, ARM::FPEXC},
242  {codeview::RegisterId::ARM_FS0, ARM::S0},
243  {codeview::RegisterId::ARM_FS1, ARM::S1},
244  {codeview::RegisterId::ARM_FS2, ARM::S2},
245  {codeview::RegisterId::ARM_FS3, ARM::S3},
246  {codeview::RegisterId::ARM_FS4, ARM::S4},
247  {codeview::RegisterId::ARM_FS5, ARM::S5},
248  {codeview::RegisterId::ARM_FS6, ARM::S6},
249  {codeview::RegisterId::ARM_FS7, ARM::S7},
250  {codeview::RegisterId::ARM_FS8, ARM::S8},
251  {codeview::RegisterId::ARM_FS9, ARM::S9},
252  {codeview::RegisterId::ARM_FS10, ARM::S10},
253  {codeview::RegisterId::ARM_FS11, ARM::S11},
254  {codeview::RegisterId::ARM_FS12, ARM::S12},
255  {codeview::RegisterId::ARM_FS13, ARM::S13},
256  {codeview::RegisterId::ARM_FS14, ARM::S14},
257  {codeview::RegisterId::ARM_FS15, ARM::S15},
258  {codeview::RegisterId::ARM_FS16, ARM::S16},
259  {codeview::RegisterId::ARM_FS17, ARM::S17},
260  {codeview::RegisterId::ARM_FS18, ARM::S18},
261  {codeview::RegisterId::ARM_FS19, ARM::S19},
262  {codeview::RegisterId::ARM_FS20, ARM::S20},
263  {codeview::RegisterId::ARM_FS21, ARM::S21},
264  {codeview::RegisterId::ARM_FS22, ARM::S22},
265  {codeview::RegisterId::ARM_FS23, ARM::S23},
266  {codeview::RegisterId::ARM_FS24, ARM::S24},
267  {codeview::RegisterId::ARM_FS25, ARM::S25},
268  {codeview::RegisterId::ARM_FS26, ARM::S26},
269  {codeview::RegisterId::ARM_FS27, ARM::S27},
270  {codeview::RegisterId::ARM_FS28, ARM::S28},
271  {codeview::RegisterId::ARM_FS29, ARM::S29},
272  {codeview::RegisterId::ARM_FS30, ARM::S30},
273  {codeview::RegisterId::ARM_FS31, ARM::S31},
274  {codeview::RegisterId::ARM_ND0, ARM::D0},
275  {codeview::RegisterId::ARM_ND1, ARM::D1},
276  {codeview::RegisterId::ARM_ND2, ARM::D2},
277  {codeview::RegisterId::ARM_ND3, ARM::D3},
278  {codeview::RegisterId::ARM_ND4, ARM::D4},
279  {codeview::RegisterId::ARM_ND5, ARM::D5},
280  {codeview::RegisterId::ARM_ND6, ARM::D6},
281  {codeview::RegisterId::ARM_ND7, ARM::D7},
282  {codeview::RegisterId::ARM_ND8, ARM::D8},
283  {codeview::RegisterId::ARM_ND9, ARM::D9},
284  {codeview::RegisterId::ARM_ND10, ARM::D10},
285  {codeview::RegisterId::ARM_ND11, ARM::D11},
286  {codeview::RegisterId::ARM_ND12, ARM::D12},
287  {codeview::RegisterId::ARM_ND13, ARM::D13},
288  {codeview::RegisterId::ARM_ND14, ARM::D14},
289  {codeview::RegisterId::ARM_ND15, ARM::D15},
290  {codeview::RegisterId::ARM_ND16, ARM::D16},
291  {codeview::RegisterId::ARM_ND17, ARM::D17},
292  {codeview::RegisterId::ARM_ND18, ARM::D18},
293  {codeview::RegisterId::ARM_ND19, ARM::D19},
294  {codeview::RegisterId::ARM_ND20, ARM::D20},
295  {codeview::RegisterId::ARM_ND21, ARM::D21},
296  {codeview::RegisterId::ARM_ND22, ARM::D22},
297  {codeview::RegisterId::ARM_ND23, ARM::D23},
298  {codeview::RegisterId::ARM_ND24, ARM::D24},
299  {codeview::RegisterId::ARM_ND25, ARM::D25},
300  {codeview::RegisterId::ARM_ND26, ARM::D26},
301  {codeview::RegisterId::ARM_ND27, ARM::D27},
302  {codeview::RegisterId::ARM_ND28, ARM::D28},
303  {codeview::RegisterId::ARM_ND29, ARM::D29},
304  {codeview::RegisterId::ARM_ND30, ARM::D30},
305  {codeview::RegisterId::ARM_ND31, ARM::D31},
306  {codeview::RegisterId::ARM_NQ0, ARM::Q0},
307  {codeview::RegisterId::ARM_NQ1, ARM::Q1},
308  {codeview::RegisterId::ARM_NQ2, ARM::Q2},
309  {codeview::RegisterId::ARM_NQ3, ARM::Q3},
310  {codeview::RegisterId::ARM_NQ4, ARM::Q4},
311  {codeview::RegisterId::ARM_NQ5, ARM::Q5},
312  {codeview::RegisterId::ARM_NQ6, ARM::Q6},
313  {codeview::RegisterId::ARM_NQ7, ARM::Q7},
314  {codeview::RegisterId::ARM_NQ8, ARM::Q8},
315  {codeview::RegisterId::ARM_NQ9, ARM::Q9},
316  {codeview::RegisterId::ARM_NQ10, ARM::Q10},
317  {codeview::RegisterId::ARM_NQ11, ARM::Q11},
318  {codeview::RegisterId::ARM_NQ12, ARM::Q12},
319  {codeview::RegisterId::ARM_NQ13, ARM::Q13},
320  {codeview::RegisterId::ARM_NQ14, ARM::Q14},
321  {codeview::RegisterId::ARM_NQ15, ARM::Q15},
322  };
323  for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
324  MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
325 }
326 
329  InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
331  return X;
332 }
333 
335  const Triple &TheTriple,
336  const MCTargetOptions &Options) {
337  MCAsmInfo *MAI;
338  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
339  MAI = new ARMMCAsmInfoDarwin(TheTriple);
340  else if (TheTriple.isWindowsMSVCEnvironment())
341  MAI = new ARMCOFFMCAsmInfoMicrosoft();
342  else if (TheTriple.isOSWindows())
343  MAI = new ARMCOFFMCAsmInfoGNU();
344  else
345  MAI = new ARMELFMCAsmInfo(TheTriple);
346 
347  unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
349 
350  return MAI;
351 }
352 
354  std::unique_ptr<MCAsmBackend> &&MAB,
355  std::unique_ptr<MCObjectWriter> &&OW,
356  std::unique_ptr<MCCodeEmitter> &&Emitter,
357  bool RelaxAll) {
358  return createARMELFStreamer(
359  Ctx, std::move(MAB), std::move(OW), std::move(Emitter), false,
360  (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb),
361  T.isAndroid());
362 }
363 
364 static MCStreamer *
365 createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB,
366  std::unique_ptr<MCObjectWriter> &&OW,
367  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
368  bool DWARFMustBeAtTheEnd) {
369  return createMachOStreamer(Ctx, std::move(MAB), std::move(OW),
370  std::move(Emitter), false, DWARFMustBeAtTheEnd);
371 }
372 
374  unsigned SyntaxVariant,
375  const MCAsmInfo &MAI,
376  const MCInstrInfo &MII,
377  const MCRegisterInfo &MRI) {
378  if (SyntaxVariant == 0)
379  return new ARMInstPrinter(MAI, MII, MRI);
380  return nullptr;
381 }
382 
384  MCContext &Ctx) {
385  if (TT.isOSBinFormatMachO())
386  return createARMMachORelocationInfo(Ctx);
387  // Default to the stock relocation info.
388  return llvm::createMCRelocationInfo(TT, Ctx);
389 }
390 
391 namespace {
392 
393 class ARMMCInstrAnalysis : public MCInstrAnalysis {
394 public:
395  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
396 
397  bool isUnconditionalBranch(const MCInst &Inst) const override {
398  // BCCs with the "always" predicate are unconditional branches.
399  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
400  return true;
402  }
403 
404  bool isConditionalBranch(const MCInst &Inst) const override {
405  // BCCs with the "always" predicate are unconditional branches.
406  if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
407  return false;
409  }
410 
411  bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
412  uint64_t Size, uint64_t &Target) const override {
413  // We only handle PCRel branches for now.
414  if (Inst.getNumOperands() == 0 ||
415  Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
417  return false;
418 
419  int64_t Imm = Inst.getOperand(0).getImm();
420  Target = Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
421  return true;
422  }
423 };
424 
425 class ThumbMCInstrAnalysis : public ARMMCInstrAnalysis {
426 public:
427  ThumbMCInstrAnalysis(const MCInstrInfo *Info) : ARMMCInstrAnalysis(Info) {}
428 
429  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
430  uint64_t &Target) const override {
431  unsigned OpId;
432  switch (Inst.getOpcode()) {
433  default:
434  OpId = 0;
435  if (Inst.getNumOperands() == 0)
436  return false;
437  break;
438  case ARM::MVE_WLSTP_8:
439  case ARM::MVE_WLSTP_16:
440  case ARM::MVE_WLSTP_32:
441  case ARM::MVE_WLSTP_64:
442  case ARM::t2WLS:
443  case ARM::MVE_LETP:
444  case ARM::t2LEUpdate:
445  OpId = 2;
446  break;
447  case ARM::t2LE:
448  OpId = 1;
449  break;
450  }
451 
452  // We only handle PCRel branches for now.
453  if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
455  return false;
456 
457  // In Thumb mode the PC is always off by 4 bytes.
458  Target = Addr + Inst.getOperand(OpId).getImm() + 4;
459  return true;
460  }
461 };
462 
463 }
464 
466  return new ARMMCInstrAnalysis(Info);
467 }
468 
470  return new ThumbMCInstrAnalysis(Info);
471 }
472 
473 bool ARM::isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI) {
474  // Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
475  // to rely on feature bits.
476  if (Coproc >= 8)
477  return false;
478  return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc];
479 }
480 
481 // Force static initialization.
485  // Register the MC asm info.
487 
488  // Register the MC instruction info.
490 
491  // Register the MC register info.
493 
494  // Register the MC subtarget info.
497 
501 
502  // Register the obj target streamer.
505 
506  // Register the asm streamer.
508 
509  // Register the null TargetStreamer.
511 
512  // Register the MCInstPrinter.
514 
515  // Register the MC relocation info.
517  }
518 
519  // Register the MC instruction analyzer.
520  for (Target *T : {&getTheARMLETarget(), &getTheARMBETarget()})
524 
525  for (Target *T : {&getTheARMLETarget(), &getTheThumbLETarget()}) {
528  }
529  for (Target *T : {&getTheARMBETarget(), &getTheThumbBETarget()}) {
532  }
533 }
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Definition: ARMMCTargetDesc.cpp:102
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Definition: ARMMCAsmInfo.h:23
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Definition: IRTranslator.cpp:100
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Definition: ARMMCTargetDesc.cpp:153
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Definition: ARMMCTargetDesc.cpp:365
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Definition: Triple.h:45
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#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MCInstrDesc::findFirstPredOperandIdx
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
Definition: MCInstrDesc.h:622
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:194
TargetParser.h
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:833
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:218
createARMMCInstPrinter
static MCInstPrinter * createARMMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: ARMMCTargetDesc.cpp:373
llvm::TargetRegistry::RegisterCOFFStreamer
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Definition: TargetRegistry.h:850
MCELFStreamer.h
llvm::Triple::isWindowsMSVCEnvironment
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:555
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
R2
#define R2(n)
llvm::createARMBEMCCodeEmitter
MCCodeEmitter * createARMBEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2009
ARMBaseInfo.h
MCAsmBackend.h
llvm::ARM_MC::isPredicated
bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII)
Definition: ARMMCTargetDesc.cpp:181
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::Triple::isOSDarwin
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:482
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::X86AS::FS
@ FS
Definition: X86.h:182
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:27
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:110
llvm::Triple::isOSBinFormatMachO
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:643
llvm::MCInstrAnalysis::isUnconditionalBranch
virtual bool isUnconditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:45
createARMMCRelocationInfo
static MCRelocationInfo * createARMMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: ARMMCTargetDesc.cpp:383
llvm::createARMLEMCCodeEmitter
MCCodeEmitter * createARMLEMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
Definition: ARMMCCodeEmitter.cpp:2003
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
getMRCDeprecationInfo
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:78
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:28
CodeView.h
llvm::ARMCOFFMCAsmInfoMicrosoft
Definition: ARMMCAsmInfo.h:39
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1341
llvm::RegisterMCAsmInfoFn
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:968
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
createARMMCInstrInfo
static MCInstrInfo * createARMMCInstrInfo()
Definition: ARMMCTargetDesc.cpp:211
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:780
llvm::TargetRegistry::RegisterMachOStreamer
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
Definition: TargetRegistry.h:854
getARMLoadDeprecationInfo
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:118
llvm::MCInstrAnalysis::isConditionalBranch
virtual bool isConditionalBranch(const MCInst &Inst) const
Definition: MCInstrAnalysis.h:41
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::ARMELFMCAsmInfo
Definition: ARMMCAsmInfo.h:30
llvm::createARMTargetAsmStreamer
MCTargetStreamer * createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: ARMELFStreamer.cpp:1505
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:877
createThumbMCInstrAnalysis
static MCInstrAnalysis * createThumbMCInstrAnalysis(const MCInstrInfo *Info)
Definition: ARMMCTargetDesc.cpp:469
MCRegisterInfo.h
llvm::ARM_MC::initLLVMToCVRegMapping
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
Definition: ARMMCTargetDesc.cpp:217
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:207
llvm::codeview::RegisterId
RegisterId
Definition: CodeView.h:514
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:488
llvm::MCAsmInfo::addInitialFrameState
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.cpp:81
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:753
R6
#define R6(n)
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
Triple.h
llvm::createARMELFStreamer
MCELFStreamer * createARMELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IsThumb, bool IsAndroid)
Definition: ARMELFStreamer.cpp:1524
llvm::createMCRelocationInfo
MCRelocationInfo * createMCRelocationInfo(const Triple &TT, MCContext &Ctx)
Definition: MCRelocationInfo.cpp:27
MCInstrAnalysis.h
ARMAddressingModes.h
getITDeprecationInfo
static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:90
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::Triple::thumb
@ thumb
Definition: Triple.h:80
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:128
llvm::createARMMachORelocationInfo
MCRelocationInfo * createARMMachORelocationInfo(MCContext &Ctx)
Construct ARM Mach-O relocation info.
Definition: ARMMachORelocationInfo.cpp:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
isUnconditionalBranch
static bool isUnconditionalBranch(Instruction *Term)
Definition: ADCE.cpp:210
llvm::createARMWinCOFFStreamer
MCStreamer * createARMWinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
Definition: ARMWinCOFFStreamer.cpp:40
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:545
llvm::createELFStreamer
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
Definition: MCELFStreamer.cpp:710
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:720
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:846
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:104
createARMMCAsmInfo
static MCAsmInfo * createARMMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple, const MCTargetOptions &Options)
Definition: ARMMCTargetDesc.cpp:334
uint16_t
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:740
llvm::ARMInstPrinter
Definition: ARMInstPrinter.h:21
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:858
llvm::ARM_MC::createARMMCSubtargetInfo
MCSubtargetInfo * createARMMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Create a ARM MCSubtargetInfo instance.
Definition: ARMMCTargetDesc.cpp:198
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:208
llvm::TargetRegistry::RegisterNullTargetStreamer
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:866
getMCRDeprecationInfo
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, std::string &Info)
Definition: ARMMCTargetDesc.cpp:39
LLVMInitializeARMTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTargetMC()
Definition: ARMMCTargetDesc.cpp:482
llvm::Triple::thumbeb
@ thumbeb
Definition: Triple.h:81
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:216
llvm::ARMCOFFMCAsmInfoGNU
Definition: ARMMCAsmInfo.h:46
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::ARM::isCDECoproc
bool isCDECoproc(size_t Coproc, const MCSubtargetInfo &STI)
Definition: ARMMCTargetDesc.cpp:473
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
createARMMCRegisterInfo
static MCRegisterInfo * createARMMCRegisterInfo(const Triple &Triple)
Definition: ARMMCTargetDesc.cpp:327
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::TargetRegistry::RegisterMCRelocationInfo
static void RegisterMCRelocationInfo(Target &T, Target::MCRelocationInfoCtorTy Fn)
RegisterMCRelocationInfo - Register an MCRelocationInfo implementation for the given target.
Definition: TargetRegistry.h:891
createARMMCInstrAnalysis
static MCInstrAnalysis * createARMMCInstrAnalysis(const MCInstrInfo *Info)
Definition: ARMMCTargetDesc.cpp:465
ARMMCAsmInfo.h
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69