LLVM 19.0.0git
ARMAsmBackend.cpp
Go to the documentation of this file.
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
20#include "llvm/MC/MCAsmLayout.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
25#include "llvm/MC/MCExpr.h"
33#include "llvm/MC/MCValue.h"
34#include "llvm/Support/Debug.h"
37#include "llvm/Support/Format.h"
39using namespace llvm;
40
41namespace {
42class ARMELFObjectWriter : public MCELFObjectTargetWriter {
43public:
44 ARMELFObjectWriter(uint8_t OSABI)
45 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
46 /*HasRelocationAddend*/ false) {}
47};
48} // end anonymous namespace
49
50std::optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
51 return std::nullopt;
52}
53
54std::optional<MCFixupKind>
55ARMAsmBackendELF::getFixupKind(StringRef Name) const {
57#define ELF_RELOC(X, Y) .Case(#X, Y)
58#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
59#undef ELF_RELOC
60 .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
61 .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
62 .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
63 .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
64 .Default(-1u);
65 if (Type == -1u)
66 return std::nullopt;
67 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
68}
69
71 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
72 // This table *must* be in the order that the fixup_* kinds are defined in
73 // ARMFixupKinds.h.
74 //
75 // Name Offset (bits) Size (bits) Flags
76 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
77 {"fixup_t2_ldst_pcrel_12", 0, 32,
80 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
81 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
82 {"fixup_t2_pcrel_10", 0, 32,
85 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86 {"fixup_t2_pcrel_9", 0, 32,
89 {"fixup_arm_ldst_abs_12", 0, 32, 0},
90 {"fixup_thumb_adr_pcrel_10", 0, 8,
93 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
94 {"fixup_t2_adr_pcrel_12", 0, 32,
97 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
98 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
103 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
104 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
105 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
106 {"fixup_arm_thumb_blx", 0, 32,
109 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
110 {"fixup_arm_thumb_cp", 0, 8,
113 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
114 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
115 // - 19.
116 {"fixup_arm_movt_hi16", 0, 20, 0},
117 {"fixup_arm_movw_lo16", 0, 20, 0},
118 {"fixup_t2_movt_hi16", 0, 20, 0},
119 {"fixup_t2_movw_lo16", 0, 20, 0},
120 {"fixup_arm_thumb_upper_8_15", 0, 8, 0},
121 {"fixup_arm_thumb_upper_0_7", 0, 8, 0},
122 {"fixup_arm_thumb_lower_8_15", 0, 8, 0},
123 {"fixup_arm_thumb_lower_0_7", 0, 8, 0},
124 {"fixup_arm_mod_imm", 0, 12, 0},
125 {"fixup_t2_so_imm", 0, 26, 0},
126 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
127 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
128 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
129 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
130 {"fixup_bfcsel_else_target", 0, 32, 0},
131 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
132 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
133 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
134 // This table *must* be in the order that the fixup_* kinds are defined in
135 // ARMFixupKinds.h.
136 //
137 // Name Offset (bits) Size (bits) Flags
138 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
139 {"fixup_t2_ldst_pcrel_12", 0, 32,
142 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
143 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
144 {"fixup_t2_pcrel_10", 0, 32,
147 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
148 {"fixup_t2_pcrel_9", 0, 32,
151 {"fixup_arm_ldst_abs_12", 0, 32, 0},
152 {"fixup_thumb_adr_pcrel_10", 8, 8,
155 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
156 {"fixup_t2_adr_pcrel_12", 0, 32,
159 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
160 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
161 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
162 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
163 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
164 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
165 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
166 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
167 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
168 {"fixup_arm_thumb_blx", 0, 32,
171 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
172 {"fixup_arm_thumb_cp", 8, 8,
175 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
176 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
177 // - 19.
178 {"fixup_arm_movt_hi16", 12, 20, 0},
179 {"fixup_arm_movw_lo16", 12, 20, 0},
180 {"fixup_t2_movt_hi16", 12, 20, 0},
181 {"fixup_t2_movw_lo16", 12, 20, 0},
182 {"fixup_arm_thumb_upper_8_15", 24, 8, 0},
183 {"fixup_arm_thumb_upper_0_7", 24, 8, 0},
184 {"fixup_arm_thumb_lower_8_15", 24, 8, 0},
185 {"fixup_arm_thumb_lower_0_7", 24, 8, 0},
186 {"fixup_arm_mod_imm", 20, 12, 0},
187 {"fixup_t2_so_imm", 26, 6, 0},
188 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
189 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
190 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
191 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
192 {"fixup_bfcsel_else_target", 0, 32, 0},
193 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
194 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
195
196 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
197 // any extra processing.
198 if (Kind >= FirstLiteralRelocationKind)
200
201 if (Kind < FirstTargetFixupKind)
203
204 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
205 "Invalid kind!");
207 ? InfosLE
208 : InfosBE)[Kind - FirstTargetFixupKind];
209}
210
212 switch (Flag) {
213 default:
214 break;
215 case MCAF_Code16:
216 setIsThumb(true);
217 break;
218 case MCAF_Code32:
219 setIsThumb(false);
220 break;
221 }
222}
223
225 const MCSubtargetInfo &STI) const {
226 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2);
227 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps);
228
229 switch (Op) {
230 default:
231 return Op;
232 case ARM::tBcc:
233 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
234 case ARM::tLDRpci:
235 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
236 case ARM::tADR:
237 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
238 case ARM::tB:
239 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
240 case ARM::tCBZ:
241 return ARM::tHINT;
242 case ARM::tCBNZ:
243 return ARM::tHINT;
244 }
245}
246
248 const MCSubtargetInfo &STI) const {
249 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
250 return true;
251 return false;
252}
253
254static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
255 int64_t Offset = int64_t(Value) - 4;
256 if (Offset < Min || Offset > Max)
257 return "out of range pc-relative fixup value";
258 return nullptr;
259}
260
262 uint64_t Value) const {
263 switch (Fixup.getTargetKind()) {
265 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
266 // low bit being an implied zero. There's an implied +4 offset for the
267 // branch, so we adjust the other way here to determine what's
268 // encodable.
269 //
270 // Relax if the value is too big for a (signed) i8.
271 int64_t Offset = int64_t(Value) - 4;
272 if (Offset > 2046 || Offset < -2048)
273 return "out of range pc-relative fixup value";
274 break;
275 }
277 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
278 // low bit being an implied zero. There's an implied +4 offset for the
279 // branch, so we adjust the other way here to determine what's
280 // encodable.
281 //
282 // Relax if the value is too big for a (signed) i8.
283 int64_t Offset = int64_t(Value) - 4;
284 if (Offset > 254 || Offset < -256)
285 return "out of range pc-relative fixup value";
286 break;
287 }
290 // If the immediate is negative, greater than 1020, or not a multiple
291 // of four, the wide version of the instruction must be used.
292 int64_t Offset = int64_t(Value) - 4;
293 if (Offset & 3)
294 return "misaligned pc-relative fixup value";
295 else if (Offset > 1020 || Offset < 0)
296 return "out of range pc-relative fixup value";
297 break;
298 }
300 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
301 // instruction it is actually out of range for the instruction.
302 // It will be changed to a NOP.
303 int64_t Offset = (Value & ~1);
304 if (Offset == 2)
305 return "will be converted to nop";
306 break;
307 }
309 return checkPCRelOffset(Value, 0, 30);
311 return checkPCRelOffset(Value, -0x10000, +0xfffe);
313 return checkPCRelOffset(Value, -0x40000, +0x3fffe);
315 return checkPCRelOffset(Value, -0x1000, +0xffe);
316 case ARM::fixup_wls:
317 return checkPCRelOffset(Value, 0, +0xffe);
318 case ARM::fixup_le:
319 // The offset field in the LE and LETP instructions is an 11-bit
320 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
321 // interpreted as a negative offset from the value read from pc,
322 // i.e. from instruction_address+4.
323 //
324 // So an LE instruction can in principle address the instruction
325 // immediately after itself, or (not very usefully) the address
326 // half way through the 4-byte LE.
327 return checkPCRelOffset(Value, -0xffe, 0);
329 if (Value != 2 && Value != 4)
330 return "out of range label-relative fixup value";
331 break;
332 }
333
334 default:
335 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
336 }
337 return nullptr;
338}
339
341 const MCRelaxableFragment *DF,
342 const MCAsmLayout &Layout) const {
344}
345
347 const MCSubtargetInfo &STI) const {
348 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
349
350 // Return a diagnostic if we get here w/ a bogus instruction.
351 if (RelaxedOp == Inst.getOpcode()) {
354 Inst.dump_pretty(OS);
355 OS << "\n";
356 report_fatal_error("unexpected instruction to relax: " + OS.str());
357 }
358
359 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
360 // have to change the operands too.
361 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
362 RelaxedOp == ARM::tHINT) {
363 MCInst Res;
364 Res.setOpcode(RelaxedOp);
368 Inst = std::move(Res);
369 return;
370 }
371
372 // The rest of instructions we're relaxing have the same operands.
373 // We just need to update to the proper opcode.
374 Inst.setOpcode(RelaxedOp);
375}
376
378 const MCSubtargetInfo *STI) const {
379 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
380 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
381 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
382 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
383 if (isThumb()) {
384 const uint16_t nopEncoding =
385 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
386 uint64_t NumNops = Count / 2;
387 for (uint64_t i = 0; i != NumNops; ++i)
388 support::endian::write(OS, nopEncoding, Endian);
389 if (Count & 1)
390 OS << '\0';
391 return true;
392 }
393 // ARM mode
394 const uint32_t nopEncoding =
395 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
396 uint64_t NumNops = Count / 4;
397 for (uint64_t i = 0; i != NumNops; ++i)
398 support::endian::write(OS, nopEncoding, Endian);
399 // FIXME: should this function return false when unable to write exactly
400 // 'Count' bytes with NOP encodings?
401 switch (Count % 4) {
402 default:
403 break; // No leftover bytes to write
404 case 1:
405 OS << '\0';
406 break;
407 case 2:
408 OS.write("\0\0", 2);
409 break;
410 case 3:
411 OS.write("\0\0\xa0", 3);
412 break;
413 }
414
415 return true;
416}
417
418static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
419 if (IsLittleEndian) {
420 // Note that the halfwords are stored high first and low second in thumb;
421 // so we need to swap the fixup value here to map properly.
422 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
423 Swapped |= (Value & 0x0000FFFF) << 16;
424 return Swapped;
425 } else
426 return Value;
427}
428
429static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
430 bool IsLittleEndian) {
432
433 if (IsLittleEndian) {
434 Value = (SecondHalf & 0xFFFF) << 16;
435 Value |= (FirstHalf & 0xFFFF);
436 } else {
437 Value = (SecondHalf & 0xFFFF);
438 Value |= (FirstHalf & 0xFFFF) << 16;
439 }
440
441 return Value;
442}
443
445 const MCFixup &Fixup,
447 bool IsResolved, MCContext &Ctx,
448 const MCSubtargetInfo* STI) const {
449 unsigned Kind = Fixup.getKind();
450
451 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
452 // and .word relocations they put the Thumb bit into the addend if possible.
453 // Other relocation types don't want this bit though (branches couldn't encode
454 // it if it *was* present, and no other relocations exist) and it can
455 // interfere with checking valid expressions.
456 if (const MCSymbolRefExpr *A = Target.getSymA()) {
457 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
458 A->getSymbol().isExternal() &&
459 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
462 Value |= 1;
463 }
464
465 switch (Kind) {
466 default:
467 return 0;
468 case FK_Data_1:
469 case FK_Data_2:
470 case FK_Data_4:
471 return Value;
472 case FK_SecRel_2:
473 return Value;
474 case FK_SecRel_4:
475 return Value;
477 assert(STI != nullptr);
478 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
479 Value >>= 16;
480 [[fallthrough]];
482 unsigned Hi4 = (Value & 0xF000) >> 12;
483 unsigned Lo12 = Value & 0x0FFF;
484 // inst{19-16} = Hi4;
485 // inst{11-0} = Lo12;
486 Value = (Hi4 << 16) | (Lo12);
487 return Value;
488 }
490 assert(STI != nullptr);
491 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
492 Value >>= 16;
493 [[fallthrough]];
495 unsigned Hi4 = (Value & 0xF000) >> 12;
496 unsigned i = (Value & 0x800) >> 11;
497 unsigned Mid3 = (Value & 0x700) >> 8;
498 unsigned Lo8 = Value & 0x0FF;
499 // inst{19-16} = Hi4;
500 // inst{26} = i;
501 // inst{14-12} = Mid3;
502 // inst{7-0} = Lo8;
503 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
505 }
507 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
508 return (Value & 0xff000000) >> 24;
509 return Value & 0xff;
511 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
512 return (Value & 0x00ff0000) >> 16;
513 return Value & 0xff;
515 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
516 return (Value & 0x0000ff00) >> 8;
517 return Value & 0xff;
519 return Value & 0x000000ff;
521 // ARM PC-relative values are offset by 8.
522 Value -= 4;
523 [[fallthrough]];
525 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
526 Value -= 4;
527 [[fallthrough]];
529 bool isAdd = true;
530 if ((int64_t)Value < 0) {
531 Value = -Value;
532 isAdd = false;
533 }
534 if (Value >= 4096) {
535 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
536 return 0;
537 }
538 Value |= isAdd << 23;
539
540 // Same addressing mode as fixup_arm_pcrel_10,
541 // but with 16-bit halfwords swapped.
542 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
544
545 return Value;
546 }
548 // ARM PC-relative values are offset by 8.
549 Value -= 8;
550 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
551 if ((int64_t)Value < 0) {
552 Value = -Value;
553 opc = 2; // 0b0010
554 }
555 if (ARM_AM::getSOImmVal(Value) == -1) {
556 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
557 return 0;
558 }
559 // Encode the immediate and shift the opcode into place.
560 return ARM_AM::getSOImmVal(Value) | (opc << 21);
561 }
562
564 Value -= 4;
565 unsigned opc = 0;
566 if ((int64_t)Value < 0) {
567 Value = -Value;
568 opc = 5;
569 }
570
571 uint32_t out = (opc << 21);
572 out |= (Value & 0x800) << 15;
573 out |= (Value & 0x700) << 4;
574 out |= (Value & 0x0FF);
575
577 }
578
584 // These values don't encode the low two bits since they're always zero.
585 // Offset by 8 just as above.
586 if (const MCSymbolRefExpr *SRE =
587 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
588 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
589 return 0;
590 return 0xffffff & ((Value - 8) >> 2);
592 Value = Value - 4;
593 if (!isInt<25>(Value)) {
594 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
595 return 0;
596 }
597
598 Value >>= 1; // Low bit is not encoded.
599
600 uint32_t out = 0;
601 bool I = Value & 0x800000;
602 bool J1 = Value & 0x400000;
603 bool J2 = Value & 0x200000;
604 J1 ^= I;
605 J2 ^= I;
606
607 out |= I << 26; // S bit
608 out |= !J1 << 13; // J1 bit
609 out |= !J2 << 11; // J2 bit
610 out |= (Value & 0x1FF800) << 5; // imm6 field
611 out |= (Value & 0x0007FF); // imm11 field
612
614 }
616 Value = Value - 4;
617 if (!isInt<21>(Value)) {
618 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
619 return 0;
620 }
621
622 Value >>= 1; // Low bit is not encoded.
623
624 uint64_t out = 0;
625 out |= (Value & 0x80000) << 7; // S bit
626 out |= (Value & 0x40000) >> 7; // J2 bit
627 out |= (Value & 0x20000) >> 4; // J1 bit
628 out |= (Value & 0x1F800) << 5; // imm6 field
629 out |= (Value & 0x007FF); // imm11 field
630
632 }
634 if (!isInt<25>(Value - 4) ||
635 (!STI->hasFeature(ARM::FeatureThumb2) &&
636 !STI->hasFeature(ARM::HasV8MBaselineOps) &&
637 !STI->hasFeature(ARM::HasV6MOps) &&
638 !isInt<23>(Value - 4))) {
639 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
640 return 0;
641 }
642
643 // The value doesn't encode the low bit (always zero) and is offset by
644 // four. The 32-bit immediate value is encoded as
645 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
646 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
647 // The value is encoded into disjoint bit positions in the destination
648 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
649 // J = either J1 or J2 bit
650 //
651 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
652 //
653 // Note that the halfwords are stored high first, low second; so we need
654 // to transpose the fixup value here to map properly.
655 uint32_t offset = (Value - 4) >> 1;
656 uint32_t signBit = (offset & 0x800000) >> 23;
657 uint32_t I1Bit = (offset & 0x400000) >> 22;
658 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
659 uint32_t I2Bit = (offset & 0x200000) >> 21;
660 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
661 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
662 uint32_t imm11Bits = (offset & 0x000007FF);
663
664 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
665 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
666 (uint16_t)imm11Bits);
667 return joinHalfWords(FirstHalf, SecondHalf,
669 }
671 // The value doesn't encode the low two bits (always zero) and is offset by
672 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
673 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
674 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
675 // The value is encoded into disjoint bit positions in the destination
676 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
677 // J = either J1 or J2 bit, 0 = zero.
678 //
679 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
680 //
681 // Note that the halfwords are stored high first, low second; so we need
682 // to transpose the fixup value here to map properly.
683 if (Value % 4 != 0) {
684 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
685 return 0;
686 }
687
688 uint32_t offset = (Value - 4) >> 2;
689 if (const MCSymbolRefExpr *SRE =
690 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
691 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
692 offset = 0;
693 uint32_t signBit = (offset & 0x400000) >> 22;
694 uint32_t I1Bit = (offset & 0x200000) >> 21;
695 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
696 uint32_t I2Bit = (offset & 0x100000) >> 20;
697 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
698 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
699 uint32_t imm10LBits = (offset & 0x3FF);
700
701 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
702 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
703 ((uint16_t)imm10LBits) << 1);
704 return joinHalfWords(FirstHalf, SecondHalf,
706 }
709 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
710 // could have an error on our hands.
711 assert(STI != nullptr);
712 if (!STI->hasFeature(ARM::FeatureThumb2) && IsResolved) {
713 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
714 if (FixupDiagnostic) {
715 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
716 return 0;
717 }
718 }
719 // Offset by 4, and don't encode the low two bits.
720 return ((Value - 4) >> 2) & 0xff;
722 // CB instructions can only branch to offsets in [4, 126] in multiples of 2
723 // so ensure that the raw value LSB is zero and it lies in [2, 130].
724 // An offset of 2 will be relaxed to a NOP.
725 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
726 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
727 return 0;
728 }
729 // Offset by 4 and don't encode the lower bit, which is always 0.
730 // FIXME: diagnose if no Thumb2
731 uint32_t Binary = (Value - 4) >> 1;
732 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
733 }
735 // Offset by 4 and don't encode the lower bit, which is always 0.
736 assert(STI != nullptr);
737 if (!STI->hasFeature(ARM::FeatureThumb2) &&
738 !STI->hasFeature(ARM::HasV8MBaselineOps)) {
739 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
740 if (FixupDiagnostic) {
741 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
742 return 0;
743 }
744 }
745 return ((Value - 4) >> 1) & 0x7ff;
747 // Offset by 4 and don't encode the lower bit, which is always 0.
748 assert(STI != nullptr);
749 if (!STI->hasFeature(ARM::FeatureThumb2)) {
750 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
751 if (FixupDiagnostic) {
752 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
753 return 0;
754 }
755 }
756 return ((Value - 4) >> 1) & 0xff;
758 Value = Value - 8; // ARM fixups offset by an additional word and don't
759 // need to adjust for the half-word ordering.
760 bool isAdd = true;
761 if ((int64_t)Value < 0) {
762 Value = -Value;
763 isAdd = false;
764 }
765 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
766 if (Value >= 256) {
767 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
768 return 0;
769 }
770 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
771 return Value | (isAdd << 23);
772 }
774 Value = Value - 4; // ARM fixups offset by an additional word and don't
775 // need to adjust for the half-word ordering.
776 [[fallthrough]];
778 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
779 Value = Value - 4;
780 bool isAdd = true;
781 if ((int64_t)Value < 0) {
782 Value = -Value;
783 isAdd = false;
784 }
785 // These values don't encode the low two bits since they're always zero.
786 Value >>= 2;
787 if (Value >= 256) {
788 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
789 return 0;
790 }
791 Value |= isAdd << 23;
792
793 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
794 // swapped.
795 if (Kind == ARM::fixup_t2_pcrel_10)
797
798 return Value;
799 }
801 Value = Value - 4; // ARM fixups offset by an additional word and don't
802 // need to adjust for the half-word ordering.
803 [[fallthrough]];
805 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
806 Value = Value - 4;
807 bool isAdd = true;
808 if ((int64_t)Value < 0) {
809 Value = -Value;
810 isAdd = false;
811 }
812 // These values don't encode the low bit since it's always zero.
813 if (Value & 1) {
814 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
815 return 0;
816 }
817 Value >>= 1;
818 if (Value >= 256) {
819 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
820 return 0;
821 }
822 Value |= isAdd << 23;
823
824 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
825 // swapped.
826 if (Kind == ARM::fixup_t2_pcrel_9)
828
829 return Value;
830 }
833 if (Value >> 12) {
834 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
835 return 0;
836 }
837 return Value;
840 if ((int64_t)Value < 0) {
841 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
842 return 0;
843 }
844 // Value will contain a 12-bit value broken up into a 4-bit shift in bits
845 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
846 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
847 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
848 // half-word.
849 uint64_t EncValue = 0;
850 EncValue |= (Value & 0x800) << 15;
851 EncValue |= (Value & 0x700) << 4;
852 EncValue |= (Value & 0xff);
853 return swapHalfWords(EncValue, Endian == llvm::endianness::little);
854 }
856 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
857 if (FixupDiagnostic) {
858 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
859 return 0;
860 }
861 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
863 }
867 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
868 if (FixupDiagnostic) {
869 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
870 return 0;
871 }
872 uint32_t out = 0;
873 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
874 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
875 out |= (((Value - 4) >> 1) & 0x1) << 11;
876 out |= (((Value - 4) >> 1) & 0x7fe);
877 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
879 }
881 // If this is a fixup of a branch future's else target then it should be a
882 // constant MCExpr representing the distance between the branch targetted
883 // and the instruction after that same branch.
884 Value = Target.getConstant();
885
886 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
887 if (FixupDiagnostic) {
888 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
889 return 0;
890 }
891 uint32_t out = ((Value >> 2) & 1) << 17;
893 }
894 case ARM::fixup_wls:
895 case ARM::fixup_le: {
896 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
897 if (FixupDiagnostic) {
898 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
899 return 0;
900 }
901 uint64_t real_value = Value - 4;
902 uint32_t out = 0;
903 if (Kind == ARM::fixup_le)
904 real_value = -real_value;
905 out |= ((real_value >> 1) & 0x1) << 11;
906 out |= ((real_value >> 1) & 0x7fe);
908 }
909 }
910}
911
913 const MCFixup &Fixup,
914 const MCValue &Target,
915 const MCSubtargetInfo *STI) {
916 const MCSymbolRefExpr *A = Target.getSymA();
917 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
918 const unsigned FixupKind = Fixup.getKind();
919 if (FixupKind >= FirstLiteralRelocationKind)
920 return true;
921 if (FixupKind == ARM::fixup_arm_thumb_bl) {
922 assert(Sym && "How did we resolve this?");
923
924 // If the symbol is external the linker will handle it.
925 // FIXME: Should we handle it as an optimization?
926
927 // If the symbol is out of range, produce a relocation and hope the
928 // linker can handle it. GNU AS produces an error in this case.
929 if (Sym->isExternal())
930 return true;
931 }
932 // Create relocations for unconditional branches to function symbols with
933 // different execution mode in ELF binaries.
934 if (Sym && Sym->isELF()) {
935 unsigned Type = cast<MCSymbolELF>(Sym)->getType();
936 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
937 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
938 return true;
939 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
940 FixupKind == ARM::fixup_arm_thumb_bl ||
941 FixupKind == ARM::fixup_t2_condbranch ||
942 FixupKind == ARM::fixup_t2_uncondbranch))
943 return true;
944 }
945 }
946 // We must always generate a relocation for BL/BLX instructions if we have
947 // a symbol to reference, as the linker relies on knowing the destination
948 // symbol's thumb-ness to get interworking right.
949 if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
950 FixupKind == ARM::fixup_arm_blx ||
951 FixupKind == ARM::fixup_arm_uncondbl ||
952 FixupKind == ARM::fixup_arm_condbl))
953 return true;
954 return false;
955}
956
957/// getFixupKindNumBytes - The number of bytes the fixup may change.
958static unsigned getFixupKindNumBytes(unsigned Kind) {
959 switch (Kind) {
960 default:
961 llvm_unreachable("Unknown fixup kind!");
962
963 case FK_Data_1:
971 return 1;
972
973 case FK_Data_2:
977 return 2;
978
990 return 3;
991
992 case FK_Data_4:
1011 case ARM::fixup_wls:
1012 case ARM::fixup_le:
1013 return 4;
1014
1015 case FK_SecRel_2:
1016 return 2;
1017 case FK_SecRel_4:
1018 return 4;
1019 }
1020}
1021
1022/// getFixupKindContainerSizeBytes - The number of bytes of the
1023/// container involved in big endian.
1024static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
1025 switch (Kind) {
1026 default:
1027 llvm_unreachable("Unknown fixup kind!");
1028
1029 case FK_Data_1:
1030 return 1;
1031 case FK_Data_2:
1032 return 2;
1033 case FK_Data_4:
1034 return 4;
1035
1045 // Instruction size is 2 bytes.
1046 return 2;
1047
1055 case ARM::fixup_arm_blx:
1077 case ARM::fixup_wls:
1078 case ARM::fixup_le:
1079 // Instruction size is 4 bytes.
1080 return 4;
1081 }
1082}
1083
1085 const MCValue &Target,
1087 bool IsResolved,
1088 const MCSubtargetInfo* STI) const {
1089 unsigned Kind = Fixup.getKind();
1090 if (Kind >= FirstLiteralRelocationKind)
1091 return;
1092 MCContext &Ctx = Asm.getContext();
1093 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
1094 if (!Value)
1095 return; // Doesn't change encoding.
1096 const unsigned NumBytes = getFixupKindNumBytes(Kind);
1097
1098 unsigned Offset = Fixup.getOffset();
1099 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
1100
1101 // Used to point to big endian bytes.
1102 unsigned FullSizeBytes;
1104 FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
1105 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
1106 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
1107 }
1108
1109 // For each byte of the fragment that the fixup touches, mask in the bits from
1110 // the fixup value. The Value has been "split up" into the appropriate
1111 // bitfields above.
1112 for (unsigned i = 0; i != NumBytes; ++i) {
1113 unsigned Idx =
1114 Endian == llvm::endianness::little ? i : (FullSizeBytes - 1 - i);
1115 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1116 }
1117}
1118
1119namespace CU {
1120
1121/// Compact unwind encoding values.
1127
1129
1133
1139
1141
1144
1145} // end CU namespace
1146
1147/// Generate compact unwind encoding for the function based on the CFI
1148/// instructions. If the CFI instructions describe a frame that cannot be
1149/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1150/// tells the runtime to fallback and unwind using dwarf.
1152 const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const {
1153 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
1154 // Only armv7k uses CFI based unwinding.
1156 return 0;
1157 // No .cfi directives means no frame.
1159 if (Instrs.empty())
1160 return 0;
1164
1165 // Start off assuming CFA is at SP+0.
1166 unsigned CFARegister = ARM::SP;
1167 int CFARegisterOffset = 0;
1168 // Mark savable registers as initially unsaved
1169 DenseMap<unsigned, int> RegOffsets;
1170 int FloatRegCount = 0;
1171 // Process each .cfi directive and build up compact unwind info.
1172 for (const MCCFIInstruction &Inst : Instrs) {
1173 unsigned Reg;
1174 switch (Inst.getOperation()) {
1175 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1176 CFARegisterOffset = Inst.getOffset();
1177 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1178 break;
1179 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1180 CFARegisterOffset = Inst.getOffset();
1181 break;
1182 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1183 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1184 break;
1185 case MCCFIInstruction::OpOffset: // DW_CFA_offset
1186 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1187 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1188 RegOffsets[Reg] = Inst.getOffset();
1189 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1190 RegOffsets[Reg] = Inst.getOffset();
1191 ++FloatRegCount;
1192 } else {
1193 DEBUG_WITH_TYPE("compact-unwind",
1194 llvm::dbgs() << ".cfi_offset on unknown register="
1195 << Inst.getRegister() << "\n");
1197 }
1198 break;
1199 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1200 // Ignore
1201 break;
1202 default:
1203 // Directive not convertable to compact unwind, bail out.
1204 DEBUG_WITH_TYPE("compact-unwind",
1205 llvm::dbgs()
1206 << "CFI directive not compatible with compact "
1207 "unwind encoding, opcode=" << Inst.getOperation()
1208 << "\n");
1210 break;
1211 }
1212 }
1213
1214 // If no frame set up, return no unwind info.
1215 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1216 return 0;
1217
1218 // Verify standard frame (lr/r7) was used.
1219 if (CFARegister != ARM::R7) {
1220 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1221 << CFARegister
1222 << " instead of r7\n");
1224 }
1225 int StackAdjust = CFARegisterOffset - 8;
1226 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1227 DEBUG_WITH_TYPE("compact-unwind",
1228 llvm::dbgs()
1229 << "LR not saved as standard frame, StackAdjust="
1230 << StackAdjust
1231 << ", CFARegisterOffset=" << CFARegisterOffset
1232 << ", lr save at offset=" << RegOffsets[14] << "\n");
1234 }
1235 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1236 DEBUG_WITH_TYPE("compact-unwind",
1237 llvm::dbgs() << "r7 not saved as standard frame\n");
1239 }
1240 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1241
1242 // If var-args are used, there may be a stack adjust required.
1243 switch (StackAdjust) {
1244 case 0:
1245 break;
1246 case 4:
1247 CompactUnwindEncoding |= 0x00400000;
1248 break;
1249 case 8:
1250 CompactUnwindEncoding |= 0x00800000;
1251 break;
1252 case 12:
1253 CompactUnwindEncoding |= 0x00C00000;
1254 break;
1255 default:
1256 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1257 << ".cfi_def_cfa stack adjust ("
1258 << StackAdjust << ") out of range\n");
1260 }
1261
1262 // If r6 is saved, it must be right below r7.
1263 static struct {
1264 unsigned Reg;
1265 unsigned Encoding;
1266 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1274
1275 int CurOffset = -8 - StackAdjust;
1276 for (auto CSReg : GPRCSRegs) {
1277 auto Offset = RegOffsets.find(CSReg.Reg);
1278 if (Offset == RegOffsets.end())
1279 continue;
1280
1281 int RegOffset = Offset->second;
1282 if (RegOffset != CurOffset - 4) {
1283 DEBUG_WITH_TYPE("compact-unwind",
1284 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1285 << RegOffset << " but only supported at "
1286 << CurOffset << "\n");
1288 }
1289 CompactUnwindEncoding |= CSReg.Encoding;
1290 CurOffset -= 4;
1291 }
1292
1293 // If no floats saved, we are done.
1294 if (FloatRegCount == 0)
1295 return CompactUnwindEncoding;
1296
1297 // Switch mode to include D register saving.
1298 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1299 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1300
1301 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1302 // but needs coordination with the linker and libunwind.
1303 if (FloatRegCount > 4) {
1304 DEBUG_WITH_TYPE("compact-unwind",
1305 llvm::dbgs() << "unsupported number of D registers saved ("
1306 << FloatRegCount << ")\n");
1308 }
1309
1310 // Floating point registers must either be saved sequentially, or we defer to
1311 // DWARF. No gaps allowed here so check that each saved d-register is
1312 // precisely where it should be.
1313 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1314 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1315 auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1316 if (Offset == RegOffsets.end()) {
1317 DEBUG_WITH_TYPE("compact-unwind",
1318 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1319 << MRI.getName(FPRCSRegs[Idx])
1320 << " not saved\n");
1322 } else if (Offset->second != CurOffset - 8) {
1323 DEBUG_WITH_TYPE("compact-unwind",
1324 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1325 << MRI.getName(FPRCSRegs[Idx])
1326 << " saved at " << Offset->second
1327 << ", expected at " << CurOffset - 8
1328 << "\n");
1330 }
1331 CurOffset -= 8;
1332 }
1333
1334 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1335}
1336
1338 const MCSubtargetInfo &STI,
1339 const MCRegisterInfo &MRI,
1340 const MCTargetOptions &Options,
1341 llvm::endianness Endian) {
1342 const Triple &TheTriple = STI.getTargetTriple();
1343 switch (TheTriple.getObjectFormat()) {
1344 default:
1345 llvm_unreachable("unsupported object format");
1346 case Triple::MachO:
1347 return new ARMAsmBackendDarwin(T, STI, MRI);
1348 case Triple::COFF:
1349 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1350 return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
1351 case Triple::ELF:
1352 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1353 uint8_t OSABI = Options.FDPIC
1356 return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
1357 Endian);
1358 }
1359}
1360
1362 const MCSubtargetInfo &STI,
1363 const MCRegisterInfo &MRI,
1364 const MCTargetOptions &Options) {
1366}
1367
1369 const MCSubtargetInfo &STI,
1370 const MCRegisterInfo &MRI,
1371 const MCTargetOptions &Options) {
1373}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian.
static MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, llvm::endianness Endian)
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
static const char * checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
Symbol * Sym
Definition: ELF_riscv.cpp:479
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
const MachO::CPUSubTypeARM Subtype
uint32_t generateCompactUnwindEncoding(const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const override
Generate compact unwind encoding for the function based on the CFI instructions.
bool isThumb() const
Definition: ARMAsmBackend.h:73
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: ARMAsmBackend.h:26
void setIsThumb(bool it)
Definition: ARMAsmBackend.h:74
bool hasNOP(const MCSubtargetInfo *STI) const
Definition: ARMAsmBackend.h:30
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI) override
Hook to check if a relocation is needed for some target specific reason.
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
This class represents an Operation in the Expression.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:202
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
const llvm::endianness Endian
Definition: MCAsmBackend.h:52
bool isDarwinCanonicalPersonality(const MCSymbol *Sym) const
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Context object for machine code objects.
Definition: MCContext.h:81
bool emitCompactUnwindNonCanonical() const
Definition: MCContext.cpp:969
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1099
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:84
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:271
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:852
ObjectFormatType getObjectFormat() const
Get the object format for this triple.
Definition: Triple.h:399
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:624
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:719
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ UNWIND_ARM_FRAME_SECOND_PUSH_R10
@ UNWIND_ARM_FRAME_FIRST_PUSH_R6
@ UNWIND_ARM_FRAME_SECOND_PUSH_R11
@ UNWIND_ARM_MODE_DWARF
@ UNWIND_ARM_DWARF_SECTION_OFFSET
@ UNWIND_ARM_FRAME_FIRST_PUSH_R4
@ UNWIND_ARM_FRAME_SECOND_PUSH_R9
@ UNWIND_ARM_FRAME_SECOND_PUSH_R8
@ UNWIND_ARM_FRAME_STACK_ADJUST_MASK
@ UNWIND_ARM_MODE_FRAME
@ UNWIND_ARM_FRAME_SECOND_PUSH_R12
@ UNWIND_ARM_FRAME_D_REG_COUNT_MASK
@ UNWIND_ARM_MODE_MASK
@ UNWIND_ARM_MODE_FRAME_D
@ UNWIND_ARM_FRAME_FIRST_PUSH_R5
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
@ fixup_arm_thumb_br
Definition: ARMFixupKinds.h:60
@ fixup_thumb_adr_pcrel_10
Definition: ARMFixupKinds.h:43
@ fixup_arm_thumb_upper_8_15
@ fixup_arm_adr_pcrel_12
Definition: ARMFixupKinds.h:45
@ fixup_arm_pcrel_10
Definition: ARMFixupKinds.h:29
@ fixup_arm_uncondbranch
Definition: ARMFixupKinds.h:51
@ fixup_arm_thumb_cb
Definition: ARMFixupKinds.h:87
@ fixup_arm_movw_lo16
Definition: ARMFixupKinds.h:98
@ fixup_t2_movt_hi16
Definition: ARMFixupKinds.h:99
@ fixup_t2_ldst_pcrel_12
Definition: ARMFixupKinds.h:21
@ fixup_arm_thumb_lower_0_7
@ fixup_arm_ldst_abs_12
Definition: ARMFixupKinds.h:40
@ fixup_arm_pcrel_9
Definition: ARMFixupKinds.h:35
@ fixup_arm_movt_hi16
Definition: ARMFixupKinds.h:97
@ fixup_t2_pcrel_9
Definition: ARMFixupKinds.h:38
@ fixup_t2_pcrel_10
Definition: ARMFixupKinds.h:32
@ fixup_arm_thumb_blx
Definition: ARMFixupKinds.h:84
@ fixup_arm_thumb_cp
Definition: ARMFixupKinds.h:90
@ fixup_t2_uncondbranch
Definition: ARMFixupKinds.h:57
@ NumTargetFixupKinds
@ fixup_arm_uncondbl
Definition: ARMFixupKinds.h:72
@ fixup_arm_pcrel_10_unscaled
Definition: ARMFixupKinds.h:25
@ fixup_arm_thumb_bcc
Definition: ARMFixupKinds.h:93
@ fixup_arm_thumb_upper_0_7
@ fixup_bfcsel_else_target
@ fixup_t2_adr_pcrel_12
Definition: ARMFixupKinds.h:47
@ fixup_t2_condbranch
Definition: ARMFixupKinds.h:54
@ fixup_arm_condbl
Definition: ARMFixupKinds.h:75
@ fixup_arm_ldst_pcrel_12
Definition: ARMFixupKinds.h:18
@ fixup_arm_thumb_lower_8_15
@ fixup_arm_thumb_bl
Definition: ARMFixupKinds.h:81
@ fixup_t2_movw_lo16
@ fixup_arm_condbranch
Definition: ARMFixupKinds.h:49
@ EM_ARM
Definition: ELF.h:156
@ ELFOSABI_ARM_FDPIC
Definition: ELF.h:365
@ STT_FUNC
Definition: ELF.h:1328
@ STT_GNU_IFUNC
Definition: ELF.h:1333
@ CPU_SUBTYPE_ARM_V7K
Definition: MachO.h:1634
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:92
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:159
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
MCAssemblerFlag
Definition: MCDirectives.h:53
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:56
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:57
DWARFExpression::Operation Op
endianness
Definition: bit.h:70
const MCSymbol * Personality
Definition: MCDwarf.h:702
std::vector< MCCFIInstruction > Instructions
Definition: MCDwarf.h:704
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...