LLVM 17.0.0git
ARMAsmBackend.cpp
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1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
20#include "llvm/MC/MCAsmLayout.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
25#include "llvm/MC/MCExpr.h"
32#include "llvm/MC/MCValue.h"
33#include "llvm/Support/Debug.h"
36#include "llvm/Support/Format.h"
38using namespace llvm;
39
40namespace {
41class ARMELFObjectWriter : public MCELFObjectTargetWriter {
42public:
43 ARMELFObjectWriter(uint8_t OSABI)
44 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
45 /*HasRelocationAddend*/ false) {}
46};
47} // end anonymous namespace
48
49std::optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const {
50 return std::nullopt;
51}
52
53std::optional<MCFixupKind>
54ARMAsmBackendELF::getFixupKind(StringRef Name) const {
56#define ELF_RELOC(X, Y) .Case(#X, Y)
57#include "llvm/BinaryFormat/ELFRelocs/ARM.def"
58#undef ELF_RELOC
59 .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE)
60 .Case("BFD_RELOC_8", ELF::R_ARM_ABS8)
61 .Case("BFD_RELOC_16", ELF::R_ARM_ABS16)
62 .Case("BFD_RELOC_32", ELF::R_ARM_ABS32)
63 .Default(-1u);
64 if (Type == -1u)
65 return std::nullopt;
66 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type);
67}
68
70 unsigned IsPCRelConstant =
72 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
73 // This table *must* be in the order that the fixup_* kinds are defined in
74 // ARMFixupKinds.h.
75 //
76 // Name Offset (bits) Size (bits) Flags
77 {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
78 {"fixup_t2_ldst_pcrel_12", 0, 32,
80 {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
81 {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
82 {"fixup_t2_pcrel_10", 0, 32,
85 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86 {"fixup_t2_pcrel_9", 0, 32,
88 {"fixup_arm_ldst_abs_12", 0, 32, 0},
89 {"fixup_thumb_adr_pcrel_10", 0, 8,
91 {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
92 {"fixup_t2_adr_pcrel_12", 0, 32,
94 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
95 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
96 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
97 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
98 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
102 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
103 {"fixup_arm_thumb_blx", 0, 32,
106 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
107 {"fixup_arm_thumb_cp", 0, 8,
110 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
111 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
112 // - 19.
113 {"fixup_arm_movt_hi16", 0, 20, 0},
114 {"fixup_arm_movw_lo16", 0, 20, 0},
115 {"fixup_t2_movt_hi16", 0, 20, 0},
116 {"fixup_t2_movw_lo16", 0, 20, 0},
117 {"fixup_arm_mod_imm", 0, 12, 0},
118 {"fixup_t2_so_imm", 0, 26, 0},
119 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
120 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
123 {"fixup_bfcsel_else_target", 0, 32, 0},
124 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
125 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
126 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
127 // This table *must* be in the order that the fixup_* kinds are defined in
128 // ARMFixupKinds.h.
129 //
130 // Name Offset (bits) Size (bits) Flags
131 {"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
132 {"fixup_t2_ldst_pcrel_12", 0, 32,
134 {"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
135 {"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
136 {"fixup_t2_pcrel_10", 0, 32,
139 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
140 {"fixup_t2_pcrel_9", 0, 32,
142 {"fixup_arm_ldst_abs_12", 0, 32, 0},
143 {"fixup_thumb_adr_pcrel_10", 8, 8,
145 {"fixup_arm_adr_pcrel_12", 0, 32, IsPCRelConstant},
146 {"fixup_t2_adr_pcrel_12", 0, 32,
148 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
149 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
150 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
151 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
152 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
153 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
154 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
155 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
156 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
157 {"fixup_arm_thumb_blx", 0, 32,
160 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
161 {"fixup_arm_thumb_cp", 8, 8,
164 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
165 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
166 // - 19.
167 {"fixup_arm_movt_hi16", 12, 20, 0},
168 {"fixup_arm_movw_lo16", 12, 20, 0},
169 {"fixup_t2_movt_hi16", 12, 20, 0},
170 {"fixup_t2_movw_lo16", 12, 20, 0},
171 {"fixup_arm_mod_imm", 20, 12, 0},
172 {"fixup_t2_so_imm", 26, 6, 0},
173 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
174 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
175 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
176 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
177 {"fixup_bfcsel_else_target", 0, 32, 0},
178 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
179 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}};
180
181 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require
182 // any extra processing.
183 if (Kind >= FirstLiteralRelocationKind)
185
186 if (Kind < FirstTargetFixupKind)
188
189 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
190 "Invalid kind!");
191 return (Endian == support::little ? InfosLE
192 : InfosBE)[Kind - FirstTargetFixupKind];
193}
194
196 switch (Flag) {
197 default:
198 break;
199 case MCAF_Code16:
200 setIsThumb(true);
201 break;
202 case MCAF_Code32:
203 setIsThumb(false);
204 break;
205 }
206}
207
209 const MCSubtargetInfo &STI) const {
210 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2);
211 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps);
212
213 switch (Op) {
214 default:
215 return Op;
216 case ARM::tBcc:
217 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
218 case ARM::tLDRpci:
219 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
220 case ARM::tADR:
221 return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
222 case ARM::tB:
223 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
224 case ARM::tCBZ:
225 return ARM::tHINT;
226 case ARM::tCBNZ:
227 return ARM::tHINT;
228 }
229}
230
232 const MCSubtargetInfo &STI) const {
233 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
234 return true;
235 return false;
236}
237
238static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) {
239 int64_t Offset = int64_t(Value) - 4;
240 if (Offset < Min || Offset > Max)
241 return "out of range pc-relative fixup value";
242 return nullptr;
243}
244
246 uint64_t Value) const {
247 switch (Fixup.getTargetKind()) {
249 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
250 // low bit being an implied zero. There's an implied +4 offset for the
251 // branch, so we adjust the other way here to determine what's
252 // encodable.
253 //
254 // Relax if the value is too big for a (signed) i8.
255 int64_t Offset = int64_t(Value) - 4;
256 if (Offset > 2046 || Offset < -2048)
257 return "out of range pc-relative fixup value";
258 break;
259 }
261 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
262 // low bit being an implied zero. There's an implied +4 offset for the
263 // branch, so we adjust the other way here to determine what's
264 // encodable.
265 //
266 // Relax if the value is too big for a (signed) i8.
267 int64_t Offset = int64_t(Value) - 4;
268 if (Offset > 254 || Offset < -256)
269 return "out of range pc-relative fixup value";
270 break;
271 }
274 // If the immediate is negative, greater than 1020, or not a multiple
275 // of four, the wide version of the instruction must be used.
276 int64_t Offset = int64_t(Value) - 4;
277 if (Offset & 3)
278 return "misaligned pc-relative fixup value";
279 else if (Offset > 1020 || Offset < 0)
280 return "out of range pc-relative fixup value";
281 break;
282 }
284 // If we have a Thumb CBZ or CBNZ instruction and its target is the next
285 // instruction it is actually out of range for the instruction.
286 // It will be changed to a NOP.
287 int64_t Offset = (Value & ~1);
288 if (Offset == 2)
289 return "will be converted to nop";
290 break;
291 }
293 return checkPCRelOffset(Value, 0, 30);
295 return checkPCRelOffset(Value, -0x10000, +0xfffe);
297 return checkPCRelOffset(Value, -0x40000, +0x3fffe);
299 return checkPCRelOffset(Value, -0x1000, +0xffe);
300 case ARM::fixup_wls:
301 return checkPCRelOffset(Value, 0, +0xffe);
302 case ARM::fixup_le:
303 // The offset field in the LE and LETP instructions is an 11-bit
304 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is
305 // interpreted as a negative offset from the value read from pc,
306 // i.e. from instruction_address+4.
307 //
308 // So an LE instruction can in principle address the instruction
309 // immediately after itself, or (not very usefully) the address
310 // half way through the 4-byte LE.
311 return checkPCRelOffset(Value, -0xffe, 0);
313 if (Value != 2 && Value != 4)
314 return "out of range label-relative fixup value";
315 break;
316 }
317
318 default:
319 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
320 }
321 return nullptr;
322}
323
325 const MCRelaxableFragment *DF,
326 const MCAsmLayout &Layout) const {
328}
329
331 const MCSubtargetInfo &STI) const {
332 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
333
334 // Return a diagnostic if we get here w/ a bogus instruction.
335 if (RelaxedOp == Inst.getOpcode()) {
338 Inst.dump_pretty(OS);
339 OS << "\n";
340 report_fatal_error("unexpected instruction to relax: " + OS.str());
341 }
342
343 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
344 // have to change the operands too.
345 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
346 RelaxedOp == ARM::tHINT) {
347 MCInst Res;
348 Res.setOpcode(RelaxedOp);
352 Inst = std::move(Res);
353 return;
354 }
355
356 // The rest of instructions we're relaxing have the same operands.
357 // We just need to update to the proper opcode.
358 Inst.setOpcode(RelaxedOp);
359}
360
362 const MCSubtargetInfo *STI) const {
363 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
364 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
365 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0
366 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
367 if (isThumb()) {
368 const uint16_t nopEncoding =
369 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
370 uint64_t NumNops = Count / 2;
371 for (uint64_t i = 0; i != NumNops; ++i)
372 support::endian::write(OS, nopEncoding, Endian);
373 if (Count & 1)
374 OS << '\0';
375 return true;
376 }
377 // ARM mode
378 const uint32_t nopEncoding =
379 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
380 uint64_t NumNops = Count / 4;
381 for (uint64_t i = 0; i != NumNops; ++i)
382 support::endian::write(OS, nopEncoding, Endian);
383 // FIXME: should this function return false when unable to write exactly
384 // 'Count' bytes with NOP encodings?
385 switch (Count % 4) {
386 default:
387 break; // No leftover bytes to write
388 case 1:
389 OS << '\0';
390 break;
391 case 2:
392 OS.write("\0\0", 2);
393 break;
394 case 3:
395 OS.write("\0\0\xa0", 3);
396 break;
397 }
398
399 return true;
400}
401
402static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
403 if (IsLittleEndian) {
404 // Note that the halfwords are stored high first and low second in thumb;
405 // so we need to swap the fixup value here to map properly.
406 uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
407 Swapped |= (Value & 0x0000FFFF) << 16;
408 return Swapped;
409 } else
410 return Value;
411}
412
413static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
414 bool IsLittleEndian) {
416
417 if (IsLittleEndian) {
418 Value = (SecondHalf & 0xFFFF) << 16;
419 Value |= (FirstHalf & 0xFFFF);
420 } else {
421 Value = (SecondHalf & 0xFFFF);
422 Value |= (FirstHalf & 0xFFFF) << 16;
423 }
424
425 return Value;
426}
427
429 const MCFixup &Fixup,
431 bool IsResolved, MCContext &Ctx,
432 const MCSubtargetInfo* STI) const {
433 unsigned Kind = Fixup.getKind();
434
435 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
436 // and .word relocations they put the Thumb bit into the addend if possible.
437 // Other relocation types don't want this bit though (branches couldn't encode
438 // it if it *was* present, and no other relocations exist) and it can
439 // interfere with checking valid expressions.
440 if (const MCSymbolRefExpr *A = Target.getSymA()) {
441 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
442 A->getSymbol().isExternal() &&
443 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
446 Value |= 1;
447 }
448
449 switch (Kind) {
450 default:
451 return 0;
452 case FK_Data_1:
453 case FK_Data_2:
454 case FK_Data_4:
455 return Value;
456 case FK_SecRel_2:
457 return Value;
458 case FK_SecRel_4:
459 return Value;
461 assert(STI != nullptr);
462 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
463 Value >>= 16;
464 [[fallthrough]];
466 unsigned Hi4 = (Value & 0xF000) >> 12;
467 unsigned Lo12 = Value & 0x0FFF;
468 // inst{19-16} = Hi4;
469 // inst{11-0} = Lo12;
470 Value = (Hi4 << 16) | (Lo12);
471 return Value;
472 }
474 assert(STI != nullptr);
475 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
476 Value >>= 16;
477 [[fallthrough]];
479 unsigned Hi4 = (Value & 0xF000) >> 12;
480 unsigned i = (Value & 0x800) >> 11;
481 unsigned Mid3 = (Value & 0x700) >> 8;
482 unsigned Lo8 = Value & 0x0FF;
483 // inst{19-16} = Hi4;
484 // inst{26} = i;
485 // inst{14-12} = Mid3;
486 // inst{7-0} = Lo8;
487 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
489 }
491 // ARM PC-relative values are offset by 8.
492 Value -= 4;
493 [[fallthrough]];
495 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
496 Value -= 4;
497 [[fallthrough]];
499 bool isAdd = true;
500 if ((int64_t)Value < 0) {
501 Value = -Value;
502 isAdd = false;
503 }
504 if (Value >= 4096) {
505 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
506 return 0;
507 }
508 Value |= isAdd << 23;
509
510 // Same addressing mode as fixup_arm_pcrel_10,
511 // but with 16-bit halfwords swapped.
512 if (Kind == ARM::fixup_t2_ldst_pcrel_12)
514
515 return Value;
516 }
518 // ARM PC-relative values are offset by 8.
519 Value -= 8;
520 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
521 if ((int64_t)Value < 0) {
522 Value = -Value;
523 opc = 2; // 0b0010
524 }
525 if (ARM_AM::getSOImmVal(Value) == -1) {
526 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
527 return 0;
528 }
529 // Encode the immediate and shift the opcode into place.
530 return ARM_AM::getSOImmVal(Value) | (opc << 21);
531 }
532
534 Value -= 4;
535 unsigned opc = 0;
536 if ((int64_t)Value < 0) {
537 Value = -Value;
538 opc = 5;
539 }
540
541 uint32_t out = (opc << 21);
542 out |= (Value & 0x800) << 15;
543 out |= (Value & 0x700) << 4;
544 out |= (Value & 0x0FF);
545
546 return swapHalfWords(out, Endian == support::little);
547 }
548
554 // These values don't encode the low two bits since they're always zero.
555 // Offset by 8 just as above.
556 if (const MCSymbolRefExpr *SRE =
557 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
558 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
559 return 0;
560 return 0xffffff & ((Value - 8) >> 2);
562 Value = Value - 4;
563 if (!isInt<25>(Value)) {
564 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
565 return 0;
566 }
567
568 Value >>= 1; // Low bit is not encoded.
569
570 uint32_t out = 0;
571 bool I = Value & 0x800000;
572 bool J1 = Value & 0x400000;
573 bool J2 = Value & 0x200000;
574 J1 ^= I;
575 J2 ^= I;
576
577 out |= I << 26; // S bit
578 out |= !J1 << 13; // J1 bit
579 out |= !J2 << 11; // J2 bit
580 out |= (Value & 0x1FF800) << 5; // imm6 field
581 out |= (Value & 0x0007FF); // imm11 field
582
583 return swapHalfWords(out, Endian == support::little);
584 }
586 Value = Value - 4;
587 if (!isInt<21>(Value)) {
588 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
589 return 0;
590 }
591
592 Value >>= 1; // Low bit is not encoded.
593
594 uint64_t out = 0;
595 out |= (Value & 0x80000) << 7; // S bit
596 out |= (Value & 0x40000) >> 7; // J2 bit
597 out |= (Value & 0x20000) >> 4; // J1 bit
598 out |= (Value & 0x1F800) << 5; // imm6 field
599 out |= (Value & 0x007FF); // imm11 field
600
601 return swapHalfWords(out, Endian == support::little);
602 }
604 if (!isInt<25>(Value - 4) ||
605 (!STI->hasFeature(ARM::FeatureThumb2) &&
606 !STI->hasFeature(ARM::HasV8MBaselineOps) &&
607 !STI->hasFeature(ARM::HasV6MOps) &&
608 !isInt<23>(Value - 4))) {
609 Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
610 return 0;
611 }
612
613 // The value doesn't encode the low bit (always zero) and is offset by
614 // four. The 32-bit immediate value is encoded as
615 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
616 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
617 // The value is encoded into disjoint bit positions in the destination
618 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
619 // J = either J1 or J2 bit
620 //
621 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
622 //
623 // Note that the halfwords are stored high first, low second; so we need
624 // to transpose the fixup value here to map properly.
625 uint32_t offset = (Value - 4) >> 1;
626 uint32_t signBit = (offset & 0x800000) >> 23;
627 uint32_t I1Bit = (offset & 0x400000) >> 22;
628 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
629 uint32_t I2Bit = (offset & 0x200000) >> 21;
630 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
631 uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
632 uint32_t imm11Bits = (offset & 0x000007FF);
633
634 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
635 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
636 (uint16_t)imm11Bits);
637 return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
638 }
640 // The value doesn't encode the low two bits (always zero) and is offset by
641 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
642 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
643 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
644 // The value is encoded into disjoint bit positions in the destination
645 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
646 // J = either J1 or J2 bit, 0 = zero.
647 //
648 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
649 //
650 // Note that the halfwords are stored high first, low second; so we need
651 // to transpose the fixup value here to map properly.
652 if (Value % 4 != 0) {
653 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
654 return 0;
655 }
656
657 uint32_t offset = (Value - 4) >> 2;
658 if (const MCSymbolRefExpr *SRE =
659 dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
660 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
661 offset = 0;
662 uint32_t signBit = (offset & 0x400000) >> 22;
663 uint32_t I1Bit = (offset & 0x200000) >> 21;
664 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
665 uint32_t I2Bit = (offset & 0x100000) >> 20;
666 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
667 uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
668 uint32_t imm10LBits = (offset & 0x3FF);
669
670 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
671 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
672 ((uint16_t)imm10LBits) << 1);
673 return joinHalfWords(FirstHalf, SecondHalf, Endian == support::little);
674 }
677 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
678 // could have an error on our hands.
679 assert(STI != nullptr);
680 if (!STI->hasFeature(ARM::FeatureThumb2) && IsResolved) {
681 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
682 if (FixupDiagnostic) {
683 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
684 return 0;
685 }
686 }
687 // Offset by 4, and don't encode the low two bits.
688 return ((Value - 4) >> 2) & 0xff;
690 // CB instructions can only branch to offsets in [4, 126] in multiples of 2
691 // so ensure that the raw value LSB is zero and it lies in [2, 130].
692 // An offset of 2 will be relaxed to a NOP.
693 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
694 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
695 return 0;
696 }
697 // Offset by 4 and don't encode the lower bit, which is always 0.
698 // FIXME: diagnose if no Thumb2
699 uint32_t Binary = (Value - 4) >> 1;
700 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
701 }
703 // Offset by 4 and don't encode the lower bit, which is always 0.
704 assert(STI != nullptr);
705 if (!STI->hasFeature(ARM::FeatureThumb2) &&
706 !STI->hasFeature(ARM::HasV8MBaselineOps)) {
707 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
708 if (FixupDiagnostic) {
709 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
710 return 0;
711 }
712 }
713 return ((Value - 4) >> 1) & 0x7ff;
715 // Offset by 4 and don't encode the lower bit, which is always 0.
716 assert(STI != nullptr);
717 if (!STI->hasFeature(ARM::FeatureThumb2)) {
718 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
719 if (FixupDiagnostic) {
720 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
721 return 0;
722 }
723 }
724 return ((Value - 4) >> 1) & 0xff;
726 Value = Value - 8; // ARM fixups offset by an additional word and don't
727 // need to adjust for the half-word ordering.
728 bool isAdd = true;
729 if ((int64_t)Value < 0) {
730 Value = -Value;
731 isAdd = false;
732 }
733 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
734 if (Value >= 256) {
735 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
736 return 0;
737 }
738 Value = (Value & 0xf) | ((Value & 0xf0) << 4);
739 return Value | (isAdd << 23);
740 }
742 Value = Value - 4; // ARM fixups offset by an additional word and don't
743 // need to adjust for the half-word ordering.
744 [[fallthrough]];
746 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
747 Value = Value - 4;
748 bool isAdd = true;
749 if ((int64_t)Value < 0) {
750 Value = -Value;
751 isAdd = false;
752 }
753 // These values don't encode the low two bits since they're always zero.
754 Value >>= 2;
755 if (Value >= 256) {
756 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
757 return 0;
758 }
759 Value |= isAdd << 23;
760
761 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
762 // swapped.
763 if (Kind == ARM::fixup_t2_pcrel_10)
765
766 return Value;
767 }
769 Value = Value - 4; // ARM fixups offset by an additional word and don't
770 // need to adjust for the half-word ordering.
771 [[fallthrough]];
773 // Offset by 4, adjusted by two due to the half-word ordering of thumb.
774 Value = Value - 4;
775 bool isAdd = true;
776 if ((int64_t)Value < 0) {
777 Value = -Value;
778 isAdd = false;
779 }
780 // These values don't encode the low bit since it's always zero.
781 if (Value & 1) {
782 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
783 return 0;
784 }
785 Value >>= 1;
786 if (Value >= 256) {
787 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
788 return 0;
789 }
790 Value |= isAdd << 23;
791
792 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
793 // swapped.
794 if (Kind == ARM::fixup_t2_pcrel_9)
796
797 return Value;
798 }
801 if (Value >> 12) {
802 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
803 return 0;
804 }
805 return Value;
808 if ((int64_t)Value < 0) {
809 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
810 return 0;
811 }
812 // Value will contain a 12-bit value broken up into a 4-bit shift in bits
813 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
814 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
815 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
816 // half-word.
817 uint64_t EncValue = 0;
818 EncValue |= (Value & 0x800) << 15;
819 EncValue |= (Value & 0x700) << 4;
820 EncValue |= (Value & 0xff);
821 return swapHalfWords(EncValue, Endian == support::little);
822 }
824 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
825 if (FixupDiagnostic) {
826 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
827 return 0;
828 }
829 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23;
830 return swapHalfWords(out, Endian == support::little);
831 }
835 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
836 if (FixupDiagnostic) {
837 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
838 return 0;
839 }
840 uint32_t out = 0;
841 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 :
842 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800);
843 out |= (((Value - 4) >> 1) & 0x1) << 11;
844 out |= (((Value - 4) >> 1) & 0x7fe);
845 out |= (((Value - 4) >> 1) & HighBitMask) << 5;
846 return swapHalfWords(out, Endian == support::little);
847 }
849 // If this is a fixup of a branch future's else target then it should be a
850 // constant MCExpr representing the distance between the branch targetted
851 // and the instruction after that same branch.
852 Value = Target.getConstant();
853
854 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
855 if (FixupDiagnostic) {
856 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
857 return 0;
858 }
859 uint32_t out = ((Value >> 2) & 1) << 17;
860 return swapHalfWords(out, Endian == support::little);
861 }
862 case ARM::fixup_wls:
863 case ARM::fixup_le: {
864 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
865 if (FixupDiagnostic) {
866 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
867 return 0;
868 }
869 uint64_t real_value = Value - 4;
870 uint32_t out = 0;
871 if (Kind == ARM::fixup_le)
872 real_value = -real_value;
873 out |= ((real_value >> 1) & 0x1) << 11;
874 out |= ((real_value >> 1) & 0x7fe);
875 return swapHalfWords(out, Endian == support::little);
876 }
877 }
878}
879
881 const MCFixup &Fixup,
882 const MCValue &Target) {
883 const MCSymbolRefExpr *A = Target.getSymA();
884 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
885 const unsigned FixupKind = Fixup.getKind();
886 if (FixupKind >= FirstLiteralRelocationKind)
887 return true;
888 if (FixupKind == ARM::fixup_arm_thumb_bl) {
889 assert(Sym && "How did we resolve this?");
890
891 // If the symbol is external the linker will handle it.
892 // FIXME: Should we handle it as an optimization?
893
894 // If the symbol is out of range, produce a relocation and hope the
895 // linker can handle it. GNU AS produces an error in this case.
896 if (Sym->isExternal())
897 return true;
898 }
899 // Create relocations for unconditional branches to function symbols with
900 // different execution mode in ELF binaries.
901 if (Sym && Sym->isELF()) {
902 unsigned Type = cast<MCSymbolELF>(Sym)->getType();
903 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
904 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
905 return true;
906 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
907 FixupKind == ARM::fixup_arm_thumb_bl ||
908 FixupKind == ARM::fixup_t2_condbranch ||
909 FixupKind == ARM::fixup_t2_uncondbranch))
910 return true;
911 }
912 }
913 // We must always generate a relocation for BL/BLX instructions if we have
914 // a symbol to reference, as the linker relies on knowing the destination
915 // symbol's thumb-ness to get interworking right.
916 if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
917 FixupKind == ARM::fixup_arm_blx ||
918 FixupKind == ARM::fixup_arm_uncondbl ||
919 FixupKind == ARM::fixup_arm_condbl))
920 return true;
921 return false;
922}
923
924/// getFixupKindNumBytes - The number of bytes the fixup may change.
925static unsigned getFixupKindNumBytes(unsigned Kind) {
926 switch (Kind) {
927 default:
928 llvm_unreachable("Unknown fixup kind!");
929
930 case FK_Data_1:
934 return 1;
935
936 case FK_Data_2:
940 return 2;
941
953 return 3;
954
955 case FK_Data_4:
974 case ARM::fixup_wls:
975 case ARM::fixup_le:
976 return 4;
977
978 case FK_SecRel_2:
979 return 2;
980 case FK_SecRel_4:
981 return 4;
982 }
983}
984
985/// getFixupKindContainerSizeBytes - The number of bytes of the
986/// container involved in big endian.
987static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
988 switch (Kind) {
989 default:
990 llvm_unreachable("Unknown fixup kind!");
991
992 case FK_Data_1:
993 return 1;
994 case FK_Data_2:
995 return 2;
996 case FK_Data_4:
997 return 4;
998
1004 // Instruction size is 2 bytes.
1005 return 2;
1006
1014 case ARM::fixup_arm_blx:
1036 case ARM::fixup_wls:
1037 case ARM::fixup_le:
1038 // Instruction size is 4 bytes.
1039 return 4;
1040 }
1041}
1042
1044 const MCValue &Target,
1046 bool IsResolved,
1047 const MCSubtargetInfo* STI) const {
1048 unsigned Kind = Fixup.getKind();
1049 if (Kind >= FirstLiteralRelocationKind)
1050 return;
1051 MCContext &Ctx = Asm.getContext();
1052 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI);
1053 if (!Value)
1054 return; // Doesn't change encoding.
1055 const unsigned NumBytes = getFixupKindNumBytes(Kind);
1056
1057 unsigned Offset = Fixup.getOffset();
1058 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
1059
1060 // Used to point to big endian bytes.
1061 unsigned FullSizeBytes;
1062 if (Endian == support::big) {
1063 FullSizeBytes = getFixupKindContainerSizeBytes(Kind);
1064 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
1065 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
1066 }
1067
1068 // For each byte of the fragment that the fixup touches, mask in the bits from
1069 // the fixup value. The Value has been "split up" into the appropriate
1070 // bitfields above.
1071 for (unsigned i = 0; i != NumBytes; ++i) {
1072 unsigned Idx = Endian == support::little ? i : (FullSizeBytes - 1 - i);
1073 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
1074 }
1075}
1076
1077namespace CU {
1078
1079/// Compact unwind encoding values.
1085
1087
1091
1097
1099
1102
1103} // end CU namespace
1104
1105/// Generate compact unwind encoding for the function based on the CFI
1106/// instructions. If the CFI instructions describe a frame that cannot be
1107/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
1108/// tells the runtime to fallback and unwind using dwarf.
1110 ArrayRef<MCCFIInstruction> Instrs) const {
1111 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
1112 // Only armv7k uses CFI based unwinding.
1114 return 0;
1115 // No .cfi directives means no frame.
1116 if (Instrs.empty())
1117 return 0;
1118 // Start off assuming CFA is at SP+0.
1119 unsigned CFARegister = ARM::SP;
1120 int CFARegisterOffset = 0;
1121 // Mark savable registers as initially unsaved
1122 DenseMap<unsigned, int> RegOffsets;
1123 int FloatRegCount = 0;
1124 // Process each .cfi directive and build up compact unwind info.
1125 for (const MCCFIInstruction &Inst : Instrs) {
1126 unsigned Reg;
1127 switch (Inst.getOperation()) {
1128 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
1129 CFARegisterOffset = Inst.getOffset();
1130 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1131 break;
1132 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
1133 CFARegisterOffset = Inst.getOffset();
1134 break;
1135 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
1136 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1137 break;
1138 case MCCFIInstruction::OpOffset: // DW_CFA_offset
1139 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
1140 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1141 RegOffsets[Reg] = Inst.getOffset();
1142 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
1143 RegOffsets[Reg] = Inst.getOffset();
1144 ++FloatRegCount;
1145 } else {
1146 DEBUG_WITH_TYPE("compact-unwind",
1147 llvm::dbgs() << ".cfi_offset on unknown register="
1148 << Inst.getRegister() << "\n");
1150 }
1151 break;
1152 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
1153 // Ignore
1154 break;
1155 default:
1156 // Directive not convertable to compact unwind, bail out.
1157 DEBUG_WITH_TYPE("compact-unwind",
1158 llvm::dbgs()
1159 << "CFI directive not compatible with compact "
1160 "unwind encoding, opcode=" << Inst.getOperation()
1161 << "\n");
1163 break;
1164 }
1165 }
1166
1167 // If no frame set up, return no unwind info.
1168 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
1169 return 0;
1170
1171 // Verify standard frame (lr/r7) was used.
1172 if (CFARegister != ARM::R7) {
1173 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
1174 << CFARegister
1175 << " instead of r7\n");
1177 }
1178 int StackAdjust = CFARegisterOffset - 8;
1179 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
1180 DEBUG_WITH_TYPE("compact-unwind",
1181 llvm::dbgs()
1182 << "LR not saved as standard frame, StackAdjust="
1183 << StackAdjust
1184 << ", CFARegisterOffset=" << CFARegisterOffset
1185 << ", lr save at offset=" << RegOffsets[14] << "\n");
1187 }
1188 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
1189 DEBUG_WITH_TYPE("compact-unwind",
1190 llvm::dbgs() << "r7 not saved as standard frame\n");
1192 }
1193 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
1194
1195 // If var-args are used, there may be a stack adjust required.
1196 switch (StackAdjust) {
1197 case 0:
1198 break;
1199 case 4:
1200 CompactUnwindEncoding |= 0x00400000;
1201 break;
1202 case 8:
1203 CompactUnwindEncoding |= 0x00800000;
1204 break;
1205 case 12:
1206 CompactUnwindEncoding |= 0x00C00000;
1207 break;
1208 default:
1209 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
1210 << ".cfi_def_cfa stack adjust ("
1211 << StackAdjust << ") out of range\n");
1213 }
1214
1215 // If r6 is saved, it must be right below r7.
1216 static struct {
1217 unsigned Reg;
1218 unsigned Encoding;
1219 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
1227
1228 int CurOffset = -8 - StackAdjust;
1229 for (auto CSReg : GPRCSRegs) {
1230 auto Offset = RegOffsets.find(CSReg.Reg);
1231 if (Offset == RegOffsets.end())
1232 continue;
1233
1234 int RegOffset = Offset->second;
1235 if (RegOffset != CurOffset - 4) {
1236 DEBUG_WITH_TYPE("compact-unwind",
1237 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
1238 << RegOffset << " but only supported at "
1239 << CurOffset << "\n");
1241 }
1242 CompactUnwindEncoding |= CSReg.Encoding;
1243 CurOffset -= 4;
1244 }
1245
1246 // If no floats saved, we are done.
1247 if (FloatRegCount == 0)
1248 return CompactUnwindEncoding;
1249
1250 // Switch mode to include D register saving.
1251 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
1252 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
1253
1254 // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
1255 // but needs coordination with the linker and libunwind.
1256 if (FloatRegCount > 4) {
1257 DEBUG_WITH_TYPE("compact-unwind",
1258 llvm::dbgs() << "unsupported number of D registers saved ("
1259 << FloatRegCount << ")\n");
1261 }
1262
1263 // Floating point registers must either be saved sequentially, or we defer to
1264 // DWARF. No gaps allowed here so check that each saved d-register is
1265 // precisely where it should be.
1266 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
1267 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
1268 auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
1269 if (Offset == RegOffsets.end()) {
1270 DEBUG_WITH_TYPE("compact-unwind",
1271 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1272 << MRI.getName(FPRCSRegs[Idx])
1273 << " not saved\n");
1275 } else if (Offset->second != CurOffset - 8) {
1276 DEBUG_WITH_TYPE("compact-unwind",
1277 llvm::dbgs() << FloatRegCount << " D-regs saved, but "
1278 << MRI.getName(FPRCSRegs[Idx])
1279 << " saved at " << Offset->second
1280 << ", expected at " << CurOffset - 8
1281 << "\n");
1283 }
1284 CurOffset -= 8;
1285 }
1286
1287 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
1288}
1289
1291 const MCSubtargetInfo &STI,
1292 const MCRegisterInfo &MRI,
1293 const MCTargetOptions &Options,
1294 support::endianness Endian) {
1295 const Triple &TheTriple = STI.getTargetTriple();
1296 switch (TheTriple.getObjectFormat()) {
1297 default:
1298 llvm_unreachable("unsupported object format");
1299 case Triple::MachO:
1300 return new ARMAsmBackendDarwin(T, STI, MRI);
1301 case Triple::COFF:
1302 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
1303 return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb());
1304 case Triple::ELF:
1305 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
1306 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
1307 return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI,
1308 Endian);
1309 }
1310}
1311
1313 const MCSubtargetInfo &STI,
1314 const MCRegisterInfo &MRI,
1315 const MCTargetOptions &Options) {
1317}
1318
1320 const MCSubtargetInfo &STI,
1321 const MCRegisterInfo &MRI,
1322 const MCTargetOptions &Options) {
1324}
unsigned const MachineRegisterInfo * MRI
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian)
static MCAsmBackend * createARMAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options, support::endianness Endian)
static unsigned getFixupKindContainerSizeBytes(unsigned Kind)
getFixupKindContainerSizeBytes - The number of bytes of the container involved in big endian.
static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, bool IsLittleEndian)
static const char * checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
Definition: Debug.h:64
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
Symbol * Sym
Definition: ELF_riscv.cpp:463
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
endianness Endian
raw_pwrite_stream & OS
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:470
uint32_t generateCompactUnwindEncoding(ArrayRef< MCCFIInstruction > Instrs) const override
Generate compact unwind encoding for the function based on the CFI instructions.
const MachO::CPUSubTypeARM Subtype
bool isThumb() const
Definition: ARMAsmBackend.h:72
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Definition: ARMAsmBackend.h:26
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
void setIsThumb(bool it)
Definition: ARMAsmBackend.h:73
bool hasNOP(const MCSubtargetInfo *STI) const
Definition: ARMAsmBackend.h:30
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
std::optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:202
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:41
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
const support::endianness Endian
Definition: MCAsmBackend.h:50
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
Context object for machine code objects.
Definition: MCContext.h:76
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1049
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void dump_pretty(raw_ostream &OS, const MCInstPrinter *Printer=nullptr, StringRef Separator=" ", const MCRegisterInfo *RegInfo=nullptr) const
Dump the MCInst as prettily as possible using the additional MC structures, if given.
Definition: MCInst.cpp:81
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
void setOpcode(unsigned Op)
Definition: MCInst.h:197
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:305
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isThumb() const
Tests whether the target is Thumb (little and big endian).
Definition: Triple.h:784
ObjectFormatType getObjectFormat() const
Get the object format for this triple.
Definition: Triple.h:382
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:365
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:584
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:675
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write(unsigned char C)
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ UNWIND_ARM_FRAME_SECOND_PUSH_R10
@ UNWIND_ARM_FRAME_FIRST_PUSH_R6
@ UNWIND_ARM_FRAME_SECOND_PUSH_R11
@ UNWIND_ARM_MODE_DWARF
@ UNWIND_ARM_DWARF_SECTION_OFFSET
@ UNWIND_ARM_FRAME_FIRST_PUSH_R4
@ UNWIND_ARM_FRAME_SECOND_PUSH_R9
@ UNWIND_ARM_FRAME_SECOND_PUSH_R8
@ UNWIND_ARM_FRAME_STACK_ADJUST_MASK
@ UNWIND_ARM_MODE_FRAME
@ UNWIND_ARM_FRAME_SECOND_PUSH_R12
@ UNWIND_ARM_FRAME_D_REG_COUNT_MASK
@ UNWIND_ARM_MODE_MASK
@ UNWIND_ARM_MODE_FRAME_D
@ UNWIND_ARM_FRAME_FIRST_PUSH_R5
int getSOImmVal(unsigned Arg)
getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immed...
int getT2SOImmVal(unsigned Arg)
getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_oper...
@ fixup_arm_thumb_br
Definition: ARMFixupKinds.h:60
@ fixup_thumb_adr_pcrel_10
Definition: ARMFixupKinds.h:43
@ fixup_arm_adr_pcrel_12
Definition: ARMFixupKinds.h:45
@ fixup_arm_pcrel_10
Definition: ARMFixupKinds.h:29
@ fixup_arm_uncondbranch
Definition: ARMFixupKinds.h:51
@ fixup_arm_thumb_cb
Definition: ARMFixupKinds.h:87
@ fixup_arm_movw_lo16
Definition: ARMFixupKinds.h:98
@ fixup_t2_movt_hi16
Definition: ARMFixupKinds.h:99
@ fixup_t2_ldst_pcrel_12
Definition: ARMFixupKinds.h:21
@ fixup_arm_ldst_abs_12
Definition: ARMFixupKinds.h:40
@ fixup_arm_pcrel_9
Definition: ARMFixupKinds.h:35
@ fixup_arm_movt_hi16
Definition: ARMFixupKinds.h:97
@ fixup_t2_pcrel_9
Definition: ARMFixupKinds.h:38
@ fixup_t2_pcrel_10
Definition: ARMFixupKinds.h:32
@ fixup_arm_thumb_blx
Definition: ARMFixupKinds.h:84
@ fixup_arm_thumb_cp
Definition: ARMFixupKinds.h:90
@ fixup_t2_uncondbranch
Definition: ARMFixupKinds.h:57
@ NumTargetFixupKinds
@ fixup_arm_uncondbl
Definition: ARMFixupKinds.h:72
@ fixup_arm_pcrel_10_unscaled
Definition: ARMFixupKinds.h:25
@ fixup_arm_thumb_bcc
Definition: ARMFixupKinds.h:93
@ fixup_bfcsel_else_target
@ fixup_t2_adr_pcrel_12
Definition: ARMFixupKinds.h:47
@ fixup_t2_condbranch
Definition: ARMFixupKinds.h:54
@ fixup_arm_condbl
Definition: ARMFixupKinds.h:75
@ fixup_arm_ldst_pcrel_12
Definition: ARMFixupKinds.h:18
@ fixup_arm_thumb_bl
Definition: ARMFixupKinds.h:81
@ fixup_t2_movw_lo16
@ fixup_arm_condbranch
Definition: ARMFixupKinds.h:49
@ EM_ARM
Definition: ELF.h:156
@ STT_FUNC
Definition: ELF.h:1255
@ STT_GNU_IFUNC
Definition: ELF.h:1260
@ CPU_SUBTYPE_ARM_V7K
Definition: MachO.h:1632
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
Definition: Endian.h:97
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MCAsmBackend * createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCAsmBackend * createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
MCAssemblerFlag
Definition: MCDirectives.h:52
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:55
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:56
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_Constant
This fixup kind should be resolved if defined.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...