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9 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H
10 #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDDARWIN_H
25 MRI(
MRI), TT(STI.getTargetTriple()),
29 std::unique_ptr<MCObjectTargetWriter>
This is an optimization pass for GlobalISel generic memory operations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Expected< uint32_t > getCPUType(const Triple &T)
uint32_t generateCompactUnwindEncoding(ArrayRef< MCCFIInstruction > Instrs) const override
Generate compact unwind encoding for the function based on the CFI instructions.
std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const override
std::unique_ptr< MCObjectTargetWriter > createARMMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype)
Construct an ARM Mach-O object writer.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
static unsigned getCPUSubType(const MachOObjectFile &O)
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
ARMAsmBackendDarwin(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI)
Generic base class for all target subtargets.
const MachO::CPUSubTypeARM Subtype