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9 #ifndef LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
10 #define LLVM_LIB_TARGET_ARM_ARMASMBACKEND_H
72 bool isThumb()
const {
return isThumbMode; }
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
into xmm2 addss xmm2 xmm1 xmm3 addss xmm3 movaps xmm0 unpcklps xmm0 ret seems silly when it could just be one addps Expand libm rounding functions main should enable SSE DAZ mode and other fast SSE modes Think about doing i64 math in SSE regs on x86 This testcase should have no SSE instructions in it
Context object for machine code objects.
unsigned getNumFixupKinds() const override
Get the number of target specific fixup kinds.
Target - Wrapper for Target specific information.
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const override
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override
Simple predicate for targets where !Resolved implies requiring relaxation.
Instances of this class represent a single low-level machine instruction.
bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const override
Write an (optimal) nop sequence of Count bytes to the given output.
const support::endianness Endian
Generic interface to target specific assembler backends.
const char * reasonForFixupRelaxation(const MCFixup &Fixup, uint64_t Value) const
const FeatureBitset & getFeatureBits() const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
This class implements an extremely fast bulk output stream that can only output to a stream.
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
void handleAssemblerFlag(MCAssemblerFlag Flag) override
Handle any target-specific assembler flags. By default, do nothing.
const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const override
Get information on a fixup kind.
unsigned getRelaxedOpcode(unsigned Op, const MCSubtargetInfo &STI) const
unsigned getPointerSize() const
bool hasNOP(const MCSubtargetInfo *STI) const
bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override
Check whether the given instruction may need relaxation.
Target independent information on a fixup kind.
void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const override
Relax the instruction in the given fragment to the next wider instruction.
StringRef - Represent a constant reference to a string, i.e.
bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target) override
Hook to check if a relocation is needed for some target specific reason.
Encapsulates the layout of an assembly file at a particular point in time.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
unsigned adjustFixupValue(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, uint64_t Value, bool IsResolved, MCContext &Ctx, const MCSubtargetInfo *STI) const
ARMAsmBackend(const Target &T, bool isThumb, support::endianness Endian)
This represents an "assembler immediate".
Optional< MCFixupKind > getFixupKind(StringRef Name) const override
Map a relocation name used in .reloc to a fixup kind.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.