LLVM 19.0.0git
MCRegisterInfo.cpp
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1//===- MC/MCRegisterInfo.cpp - Target Register Description ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements MCRegisterInfo functions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/DenseMap.h"
15#include "llvm/ADT/Twine.h"
17#include <algorithm>
18#include <cassert>
19#include <cstdint>
20
21using namespace llvm;
22
25 const MCRegisterClass *RC) const {
26 for (MCPhysReg Super : superregs(Reg))
27 if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx))
28 return Super;
29 return 0;
30}
31
34 "This is not a subregister index");
35 // Get a pointer to the corresponding SubRegIndices list. This list has the
36 // name of each sub-register in the same order as MCSubRegIterator.
37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
38 for (MCPhysReg Sub : subregs(Reg)) {
39 if (*SRI == Idx)
40 return Sub;
41 ++SRI;
42 }
43 return 0;
44}
45
47 MCRegister SubReg) const {
48 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
49 // Get a pointer to the corresponding SubRegIndices list. This list has the
50 // name of each sub-register in the same order as MCSubRegIterator.
51 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
52 for (MCPhysReg Sub : subregs(Reg)) {
53 if (Sub == SubReg)
54 return *SRI;
55 ++SRI;
56 }
57 return 0;
58}
59
60unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
62 "This is not a subregister index");
63 return SubRegIdxRanges[Idx].Size;
64}
65
66unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
68 "This is not a subregister index");
69 return SubRegIdxRanges[Idx].Offset;
70}
71
72int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
73 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
74 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
75
76 if (!M)
77 return -1;
78 DwarfLLVMRegPair Key = { RegNum, 0 };
79 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
80 if (I == M+Size || I->FromReg != RegNum)
81 return -1;
82 return I->ToReg;
83}
84
85std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
86 bool isEH) const {
87 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
88 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
89
90 if (!M)
91 return std::nullopt;
92 DwarfLLVMRegPair Key = { RegNum, 0 };
93 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
94 if (I != M + Size && I->FromReg == RegNum)
95 return I->ToReg;
96 return std::nullopt;
97}
98
100 // On ELF platforms, DWARF EH register numbers are the same as DWARF
101 // other register numbers. On Darwin x86, they differ and so need to be
102 // mapped. The .cfi_* directives accept integer literals as well as
103 // register names and should generate exactly what the assembly code
104 // asked for, so there might be DWARF/EH register numbers that don't have
105 // a corresponding LLVM register number at all. So if we can't map the
106 // EH register number to an LLVM register number, assume it's just a
107 // valid DWARF register number as is.
108 if (std::optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) {
109 int DwarfRegNum = getDwarfRegNum(*LRegNum, false);
110 if (DwarfRegNum == -1)
111 return RegNum;
112 else
113 return DwarfRegNum;
114 }
115 return RegNum;
116}
117
119 const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum);
120 if (I == L2SEHRegs.end()) return (int)RegNum;
121 return I->second;
122}
123
125 if (L2CVRegs.empty())
126 report_fatal_error("target does not implement codeview register mapping");
127 const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
128 if (I == L2CVRegs.end())
129 report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
130 ? getName(RegNum)
131 : Twine(RegNum)));
132 return I->second;
133}
134
136 // Regunits are numerically ordered. Find a common unit.
137 auto RangeA = regunits(RegA);
138 MCRegUnitIterator IA = RangeA.begin(), EA = RangeA.end();
139 auto RangeB = regunits(RegB);
140 MCRegUnitIterator IB = RangeB.begin(), EB = RangeB.end();
141 do {
142 if (*IA == *IB)
143 return true;
144 } while (*IA < *IB ? ++IA != EA : ++IB != EB);
145 return false;
146}
unsigned SubReg
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MCRegisterClass - Base class of TargetRegisterClass.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
unsigned getNumSubRegIndices() const
Return the number of sub-register indices understood by the target.
unsigned getSubRegIdxSize(unsigned Idx) const
Get the size of the bit range covered by a sub-register index.
int getDwarfRegNum(MCRegister RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
bool regsOverlap(MCRegister RegA, MCRegister RegB) const
Returns true if the two registers are equal or alias each other.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
int getCodeViewRegNum(MCRegister RegNum) const
Map a target register to an equivalent CodeView register number.
std::optional< unsigned > getLLVMRegNum(unsigned RegNum, bool isEH) const
Map a dwarf register back to a target register.
const MCRegisterDesc & get(MCRegister RegNo) const
Provide a get method, equivalent to [], but more useful with a pointer to this object.
int getSEHRegNum(MCRegister RegNum) const
Map a target register to an equivalent SEH register number.
iterator_range< MCSuperRegIterator > superregs(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, excluding Reg.
const char * getName(MCRegister RegNo) const
Return the human-readable symbolic target-specific name for the specified physical register.
int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const
Map a target EH register number to an equivalent DWARF register number.
iterator_range< MCSubRegIterator > subregs(MCRegister Reg) const
Return an iterator range over all sub-registers of Reg, excluding Reg.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getSubRegIdxOffset(unsigned Idx) const
Get the offset of the bit range covered by a sub-register index.
iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const
Returns an iterator range over all regunits for Reg.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be performed with a binary se...