LLVM  13.0.0git
ARMTargetParser.cpp
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1 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a target parser to recognise ARM hardware features
10 // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
11 //
12 //===----------------------------------------------------------------------===//
13 
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/ADT/Triple.h"
17 #include <cctype>
18 
19 using namespace llvm;
20 
22  return StringSwitch<StringRef>(HWDiv)
23  .Case("thumb,arm", "arm,thumb")
24  .Default(HWDiv);
25 }
26 
27 // Allows partial match, ex. "v7a" matches "armv7a".
29  Arch = getCanonicalArchName(Arch);
30  StringRef Syn = getArchSynonym(Arch);
31  for (const auto &A : ARCHNames) {
32  if (A.getName().endswith(Syn))
33  return A.ID;
34  }
35  return ArchKind::INVALID;
36 }
37 
38 // Version number (ex. v7 = 7).
40  Arch = getCanonicalArchName(Arch);
41  switch (parseArch(Arch)) {
42  case ArchKind::ARMV2:
43  case ArchKind::ARMV2A:
44  return 2;
45  case ArchKind::ARMV3:
46  case ArchKind::ARMV3M:
47  return 3;
48  case ArchKind::ARMV4:
49  case ArchKind::ARMV4T:
50  return 4;
51  case ArchKind::ARMV5T:
52  case ArchKind::ARMV5TE:
53  case ArchKind::IWMMXT:
54  case ArchKind::IWMMXT2:
55  case ArchKind::XSCALE:
56  case ArchKind::ARMV5TEJ:
57  return 5;
58  case ArchKind::ARMV6:
59  case ArchKind::ARMV6K:
60  case ArchKind::ARMV6T2:
61  case ArchKind::ARMV6KZ:
62  case ArchKind::ARMV6M:
63  return 6;
64  case ArchKind::ARMV7A:
65  case ArchKind::ARMV7VE:
66  case ArchKind::ARMV7R:
67  case ArchKind::ARMV7M:
68  case ArchKind::ARMV7S:
69  case ArchKind::ARMV7EM:
70  case ArchKind::ARMV7K:
71  return 7;
72  case ArchKind::ARMV8A:
73  case ArchKind::ARMV8_1A:
74  case ArchKind::ARMV8_2A:
75  case ArchKind::ARMV8_3A:
76  case ArchKind::ARMV8_4A:
77  case ArchKind::ARMV8_5A:
78  case ArchKind::ARMV8_6A:
79  case ArchKind::ARMV8_7A:
80  case ArchKind::ARMV8R:
81  case ArchKind::ARMV8MBaseline:
82  case ArchKind::ARMV8MMainline:
83  case ArchKind::ARMV8_1MMainline:
84  return 8;
85  case ArchKind::INVALID:
86  return 0;
87  }
88  llvm_unreachable("Unhandled architecture");
89 }
90 
91 // Profile A/R/M
93  Arch = getCanonicalArchName(Arch);
94  switch (parseArch(Arch)) {
95  case ArchKind::ARMV6M:
96  case ArchKind::ARMV7M:
97  case ArchKind::ARMV7EM:
98  case ArchKind::ARMV8MMainline:
99  case ArchKind::ARMV8MBaseline:
100  case ArchKind::ARMV8_1MMainline:
101  return ProfileKind::M;
102  case ArchKind::ARMV7R:
103  case ArchKind::ARMV8R:
104  return ProfileKind::R;
105  case ArchKind::ARMV7A:
106  case ArchKind::ARMV7VE:
107  case ArchKind::ARMV7K:
108  case ArchKind::ARMV8A:
109  case ArchKind::ARMV8_1A:
110  case ArchKind::ARMV8_2A:
111  case ArchKind::ARMV8_3A:
112  case ArchKind::ARMV8_4A:
113  case ArchKind::ARMV8_5A:
114  case ArchKind::ARMV8_6A:
115  case ArchKind::ARMV8_7A:
116  return ProfileKind::A;
117  case ArchKind::ARMV2:
118  case ArchKind::ARMV2A:
119  case ArchKind::ARMV3:
120  case ArchKind::ARMV3M:
121  case ArchKind::ARMV4:
122  case ArchKind::ARMV4T:
123  case ArchKind::ARMV5T:
124  case ArchKind::ARMV5TE:
125  case ArchKind::ARMV5TEJ:
126  case ArchKind::ARMV6:
127  case ArchKind::ARMV6K:
128  case ArchKind::ARMV6T2:
129  case ArchKind::ARMV6KZ:
130  case ArchKind::ARMV7S:
131  case ArchKind::IWMMXT:
132  case ArchKind::IWMMXT2:
133  case ArchKind::XSCALE:
134  case ArchKind::INVALID:
135  return ProfileKind::INVALID;
136  }
137  llvm_unreachable("Unhandled architecture");
138 }
139 
141  return StringSwitch<StringRef>(Arch)
142  .Case("v5", "v5t")
143  .Case("v5e", "v5te")
144  .Case("v6j", "v6")
145  .Case("v6hl", "v6k")
146  .Cases("v6m", "v6sm", "v6s-m", "v6-m")
147  .Cases("v6z", "v6zk", "v6kz")
148  .Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
149  .Case("v7r", "v7-r")
150  .Case("v7m", "v7-m")
151  .Case("v7em", "v7e-m")
152  .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
153  .Case("v8.1a", "v8.1-a")
154  .Case("v8.2a", "v8.2-a")
155  .Case("v8.3a", "v8.3-a")
156  .Case("v8.4a", "v8.4-a")
157  .Case("v8.5a", "v8.5-a")
158  .Case("v8.6a", "v8.6-a")
159  .Case("v8.7a", "v8.7-a")
160  .Case("v8r", "v8-r")
161  .Case("v8m.base", "v8-m.base")
162  .Case("v8m.main", "v8-m.main")
163  .Case("v8.1m.main", "v8.1-m.main")
164  .Default(Arch);
165 }
166 
167 bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
168 
169  if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
170  return false;
171 
172  static const struct FPUFeatureNameInfo {
173  const char *PlusName, *MinusName;
174  FPUVersion MinVersion;
175  FPURestriction MaxRestriction;
176  } FPUFeatureInfoList[] = {
177  // We have to specify the + and - versions of the name in full so
178  // that we can return them as static StringRefs.
179  //
180  // Also, the SubtargetFeatures ending in just "sp" are listed here
181  // under FPURestriction::None, which is the only FPURestriction in
182  // which they would be valid (since FPURestriction::SP doesn't
183  // exist).
184  {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
185  {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
186  {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
187  {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
188  {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
189  {"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None},
190  {"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16},
191  {"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None},
192  {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16},
193  {"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16},
194  {"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None},
195  {"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None},
196  {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16},
197  {"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16},
198  {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
199  {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
200  {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
201  {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
202  };
203 
204  for (const auto &Info: FPUFeatureInfoList) {
205  if (FPUNames[FPUKind].FPUVer >= Info.MinVersion &&
206  FPUNames[FPUKind].Restriction <= Info.MaxRestriction)
207  Features.push_back(Info.PlusName);
208  else
209  Features.push_back(Info.MinusName);
210  }
211 
212  static const struct NeonFeatureNameInfo {
213  const char *PlusName, *MinusName;
214  NeonSupportLevel MinSupportLevel;
215  } NeonFeatureInfoList[] = {
216  {"+neon", "-neon", NeonSupportLevel::Neon},
217  {"+crypto", "-crypto", NeonSupportLevel::Crypto},
218  };
219 
220  for (const auto &Info: NeonFeatureInfoList) {
221  if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel)
222  Features.push_back(Info.PlusName);
223  else
224  Features.push_back(Info.MinusName);
225  }
226 
227  return true;
228 }
229 
230 // Little/Big endian
232  if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
233  Arch.startswith("aarch64_be"))
234  return EndianKind::BIG;
235 
236  if (Arch.startswith("arm") || Arch.startswith("thumb")) {
237  if (Arch.endswith("eb"))
238  return EndianKind::BIG;
239  else
240  return EndianKind::LITTLE;
241  }
242 
243  if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
244  return EndianKind::LITTLE;
245 
246  return EndianKind::INVALID;
247 }
248 
249 // ARM, Thumb, AArch64
251  return StringSwitch<ISAKind>(Arch)
252  .StartsWith("aarch64", ISAKind::AARCH64)
253  .StartsWith("arm64", ISAKind::AARCH64)
254  .StartsWith("thumb", ISAKind::THUMB)
255  .StartsWith("arm", ISAKind::ARM)
256  .Default(ISAKind::INVALID);
257 }
258 
259 unsigned ARM::parseFPU(StringRef FPU) {
260  StringRef Syn = getFPUSynonym(FPU);
261  for (const auto &F : FPUNames) {
262  if (Syn == F.getName())
263  return F.ID;
264  }
265  return FK_INVALID;
266 }
267 
269  if (FPUKind >= FK_LAST)
270  return NeonSupportLevel::None;
271  return FPUNames[FPUKind].NeonSupport;
272 }
273 
274 // MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
275 // (iwmmxt|xscale)(eb)? is also permitted. If the former, return
276 // "v.+", if the latter, return unmodified string, minus 'eb'.
277 // If invalid, return empty string.
279  size_t offset = StringRef::npos;
280  StringRef A = Arch;
281  StringRef Error = "";
282 
283  // Begins with "arm" / "thumb", move past it.
284  if (A.startswith("arm64_32"))
285  offset = 8;
286  else if (A.startswith("arm64e"))
287  offset = 6;
288  else if (A.startswith("arm64"))
289  offset = 5;
290  else if (A.startswith("aarch64_32"))
291  offset = 10;
292  else if (A.startswith("arm"))
293  offset = 3;
294  else if (A.startswith("thumb"))
295  offset = 5;
296  else if (A.startswith("aarch64")) {
297  offset = 7;
298  // AArch64 uses "_be", not "eb" suffix.
299  if (A.find("eb") != StringRef::npos)
300  return Error;
301  if (A.substr(offset, 3) == "_be")
302  offset += 3;
303  }
304 
305  // Ex. "armebv7", move past the "eb".
306  if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
307  offset += 2;
308  // Or, if it ends with eb ("armv7eb"), chop it off.
309  else if (A.endswith("eb"))
310  A = A.substr(0, A.size() - 2);
311  // Trim the head
312  if (offset != StringRef::npos)
313  A = A.substr(offset);
314 
315  // Empty string means offset reached the end, which means it's valid.
316  if (A.empty())
317  return Arch;
318 
319  // Only match non-marketing names
320  if (offset != StringRef::npos) {
321  // Must start with 'vN'.
322  if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1])))
323  return Error;
324  // Can't have an extra 'eb'.
325  if (A.find("eb") != StringRef::npos)
326  return Error;
327  }
328 
329  // Arch will either be a 'v' name (v7a) or a marketing name (xscale).
330  return A;
331 }
332 
334  return StringSwitch<StringRef>(FPU)
335  .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
336  .Case("vfp2", "vfpv2")
337  .Case("vfp3", "vfpv3")
338  .Case("vfp4", "vfpv4")
339  .Case("vfp3-d16", "vfpv3-d16")
340  .Case("vfp4-d16", "vfpv4-d16")
341  .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
342  .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
343  .Case("fp5-sp-d16", "fpv5-sp-d16")
344  .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
345  // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
346  .Case("neon-vfpv3", "neon")
347  .Default(FPU);
348 }
349 
351  if (FPUKind >= FK_LAST)
352  return StringRef();
353  return FPUNames[FPUKind].getName();
354 }
355 
357  if (FPUKind >= FK_LAST)
358  return FPUVersion::NONE;
359  return FPUNames[FPUKind].FPUVer;
360 }
361 
363  if (FPUKind >= FK_LAST)
364  return FPURestriction::None;
365  return FPUNames[FPUKind].Restriction;
366 }
367 
369  if (CPU == "generic")
370  return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
371 
372  return StringSwitch<unsigned>(CPU)
373 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
374  .Case(NAME, DEFAULT_FPU)
375 #include "llvm/Support/ARMTargetParser.def"
377 }
378 
380  if (CPU == "generic")
381  return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
382 
383  return StringSwitch<uint64_t>(CPU)
384 #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
385  .Case(NAME, \
386  ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
387  DEFAULT_EXT)
388 #include "llvm/Support/ARMTargetParser.def"
390 }
391 
392 bool ARM::getHWDivFeatures(uint64_t HWDivKind,
393  std::vector<StringRef> &Features) {
394 
395  if (HWDivKind == AEK_INVALID)
396  return false;
397 
398  if (HWDivKind & AEK_HWDIVARM)
399  Features.push_back("+hwdiv-arm");
400  else
401  Features.push_back("-hwdiv-arm");
402 
403  if (HWDivKind & AEK_HWDIVTHUMB)
404  Features.push_back("+hwdiv");
405  else
406  Features.push_back("-hwdiv");
407 
408  return true;
409 }
410 
411 bool ARM::getExtensionFeatures(uint64_t Extensions,
412  std::vector<StringRef> &Features) {
413 
414  if (Extensions == AEK_INVALID)
415  return false;
416 
417  for (const auto &AE : ARCHExtNames) {
418  if ((Extensions & AE.ID) == AE.ID && AE.Feature)
419  Features.push_back(AE.Feature);
420  else if (AE.NegFeature)
421  Features.push_back(AE.NegFeature);
422  }
423 
424  return getHWDivFeatures(Extensions, Features);
425 }
426 
428  return ARCHNames[static_cast<unsigned>(AK)].getName();
429 }
430 
432  return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
433 }
434 
436  return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
437 }
438 
440  return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
441 }
442 
444  for (const auto &AE : ARCHExtNames) {
445  if (ArchExtKind == AE.ID)
446  return AE.getName();
447  }
448  return StringRef();
449 }
450 
452  if (Name.startswith("no")) {
453  Name = Name.substr(2);
454  return true;
455  }
456  return false;
457 }
458 
460  bool Negated = stripNegationPrefix(ArchExt);
461  for (const auto &AE : ARCHExtNames) {
462  if (AE.Feature && ArchExt == AE.getName())
463  return StringRef(Negated ? AE.NegFeature : AE.Feature);
464  }
465 
466  return StringRef();
467 }
468 
469 static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) {
470  const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind];
471 
472  // If the input FPU already supports double-precision, then there
473  // isn't any different FPU we can return here.
474  //
475  // The current available FPURestriction values are None (no
476  // restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs
477  // and single precision only); there's no value representing
478  // SP restriction without D16. So this test just means 'is it
479  // SP only?'.
481  return ARM::FK_INVALID;
482 
483  // Otherwise, look for an FPU entry with all the same fields, except
484  // that SP_D16 has been replaced with just D16, representing adding
485  // double precision and not changing anything else.
486  for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) {
487  if (CandidateFPU.FPUVer == InputFPU.FPUVer &&
488  CandidateFPU.NeonSupport == InputFPU.NeonSupport &&
489  CandidateFPU.Restriction == ARM::FPURestriction::D16) {
490  return CandidateFPU.ID;
491  }
492  }
493 
494  // nothing found
495  return ARM::FK_INVALID;
496 }
497 
499  StringRef ArchExt,
500  std::vector<StringRef> &Features,
501  unsigned &ArgFPUID) {
502 
503  size_t StartingNumFeatures = Features.size();
504  const bool Negated = stripNegationPrefix(ArchExt);
505  uint64_t ID = parseArchExt(ArchExt);
506 
507  if (ID == AEK_INVALID)
508  return false;
509 
510  for (const auto &AE : ARCHExtNames) {
511  if (Negated) {
512  if ((AE.ID & ID) == ID && AE.NegFeature)
513  Features.push_back(AE.NegFeature);
514  } else {
515  if ((AE.ID & ID) == AE.ID && AE.Feature)
516  Features.push_back(AE.Feature);
517  }
518  }
519 
520  if (CPU == "")
521  CPU = "generic";
522 
523  if (ArchExt == "fp" || ArchExt == "fp.dp") {
524  unsigned FPUKind;
525  if (ArchExt == "fp.dp") {
526  if (Negated) {
527  Features.push_back("-fp64");
528  return true;
529  }
531  } else if (Negated) {
533  } else {
534  FPUKind = getDefaultFPU(CPU, AK);
535  }
536  ArgFPUID = FPUKind;
537  return ARM::getFPUFeatures(FPUKind, Features);
538  }
539  return StartingNumFeatures != Features.size();
540 }
541 
542 StringRef ARM::getHWDivName(uint64_t HWDivKind) {
543  for (const auto &D : HWDivNames) {
544  if (HWDivKind == D.ID)
545  return D.getName();
546  }
547  return StringRef();
548 }
549 
551  ArchKind AK = parseArch(Arch);
552  if (AK == ArchKind::INVALID)
553  return StringRef();
554 
555  // Look for multiple AKs to find the default for pair AK+Name.
556  for (const auto &CPU : CPUNames) {
557  if (CPU.ArchID == AK && CPU.Default)
558  return CPU.getName();
559  }
560 
561  // If we can't find a default then target the architecture instead
562  return "generic";
563 }
564 
565 uint64_t ARM::parseHWDiv(StringRef HWDiv) {
566  StringRef Syn = getHWDivSynonym(HWDiv);
567  for (const auto &D : HWDivNames) {
568  if (Syn == D.getName())
569  return D.ID;
570  }
571  return AEK_INVALID;
572 }
573 
574 uint64_t ARM::parseArchExt(StringRef ArchExt) {
575  for (const auto &A : ARCHExtNames) {
576  if (ArchExt == A.getName())
577  return A.ID;
578  }
579  return AEK_INVALID;
580 }
581 
583  for (const auto &C : CPUNames) {
584  if (CPU == C.getName())
585  return C.ArchID;
586  }
587  return ArchKind::INVALID;
588 }
589 
591  for (const CpuNames<ArchKind> &Arch : CPUNames) {
592  if (Arch.ArchID != ArchKind::INVALID)
593  Values.push_back(Arch.getName());
594  }
595 }
596 
598  StringRef ArchName =
599  CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
600 
601  if (TT.isOSBinFormatMachO()) {
602  if (TT.getEnvironment() == Triple::EABI ||
603  TT.getOS() == Triple::UnknownOS ||
604  parseArchProfile(ArchName) == ProfileKind::M)
605  return "aapcs";
606  if (TT.isWatchABI())
607  return "aapcs16";
608  return "apcs-gnu";
609  } else if (TT.isOSWindows())
610  // FIXME: this is invalid for WindowsCE.
611  return "aapcs";
612 
613  // Select the default based on the platform.
614  switch (TT.getEnvironment()) {
615  case Triple::Android:
616  case Triple::GNUEABI:
617  case Triple::GNUEABIHF:
618  case Triple::MuslEABI:
619  case Triple::MuslEABIHF:
620  return "aapcs-linux";
621  case Triple::EABIHF:
622  case Triple::EABI:
623  return "aapcs";
624  default:
625  if (TT.isOSNetBSD())
626  return "apcs-gnu";
627  if (TT.isOSOpenBSD())
628  return "aapcs-linux";
629  return "aapcs";
630  }
631 }
llvm::StringSwitch::Case
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:67
llvm::ARM::FK_LAST
@ FK_LAST
Definition: ARMTargetParser.h:134
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LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:289
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StringSwitch & StartsWith(StringLiteral S, T Value)
Definition: StringSwitch.h:81
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static StringRef getName(Value *V)
Definition: ProvenanceAnalysisEvaluator.cpp:42
llvm
Definition: AllocatorList.h:23
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
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EndianKind
Definition: ARMTargetParser.h:167
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LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
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Definition: ARMTargetParser.h:131
llvm::ARM::PredBlockMask::TT
@ TT
llvm::ARM::getCanonicalArchName
StringRef getCanonicalArchName(StringRef Arch)
Definition: ARMTargetParser.cpp:278
llvm::ARM::FPUName
Definition: ARMTargetParser.h:177
llvm::ARM::FPURestriction
FPURestriction
Definition: ARMTargetParser.h:149
llvm::ARM::FPUName::getName
StringRef getName() const
Definition: ARMTargetParser.h:185
llvm::ARM::getArchName
StringRef getArchName(ArchKind AK)
Definition: ARMTargetParser.cpp:427
llvm::StringRef::endswith
LLVM_NODISCARD bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:300
llvm::StringSwitch::Default
LLVM_NODISCARD R Default(T Value)
Definition: StringSwitch.h:181
llvm::StringRef::npos
static constexpr size_t npos
Definition: StringRef.h:59
llvm::ARM::ARCHExtNames
const ExtName ARCHExtNames[]
Definition: ARMTargetParser.h:83
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:220
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::ARM::parseArchProfile
ProfileKind parseArchProfile(StringRef Arch)
Definition: ARMTargetParser.cpp:92
llvm::ARM::getArchSynonym
StringRef getArchSynonym(StringRef Arch)
Definition: ARMTargetParser.cpp:140
llvm::AArch64::getCPUAttr
StringRef getCPUAttr(ArchKind AK)
Definition: AArch64TargetParser.cpp:139
llvm::ARM::ArchExtKind
ArchExtKind
Definition: ARMTargetParser.h:30
llvm::ARM::ProfileKind
ProfileKind
Definition: ARMTargetParser.h:170
llvm::ARM::FPURestriction::SP_D16
@ SP_D16
Only single-precision instructions, with 16 D registers.
llvm::ARM::getCPUAttr
StringRef getCPUAttr(ArchKind AK)
Definition: ARMTargetParser.cpp:431
llvm::AArch64::parseArchExt
ArchExtKind parseArchExt(StringRef ArchExt)
Definition: AArch64TargetParser.cpp:213
llvm::ARM::getFPUFeatures
bool getFPUFeatures(unsigned FPUKind, std::vector< StringRef > &Features)
Definition: ARMTargetParser.cpp:167
llvm::ARM::FPUName::NeonSupport
NeonSupportLevel NeonSupport
Definition: ARMTargetParser.h:182
llvm::ARM::FPUNames
static const FPUName FPUNames[]
Definition: ARMTargetParser.h:188
llvm::ARM::fillValidCPUArchList
void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values)
Definition: ARMTargetParser.cpp:590
stripNegationPrefix
static bool stripNegationPrefix(StringRef &Name)
Definition: ARMTargetParser.cpp:451
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:210
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:129
llvm::ARM::getArchAttr
unsigned getArchAttr(ArchKind AK)
Definition: ARMTargetParser.cpp:439
llvm::ARM::AEK_HWDIVTHUMB
@ AEK_HWDIVTHUMB
Definition: ARMTargetParser.h:36
llvm::AArch64::AEK_INVALID
@ AEK_INVALID
Definition: AArch64TargetParser.h:31
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARM::CPUNames
const CpuNames< ArchKind > CPUNames[]
Definition: ARMTargetParser.h:124
llvm::ARM::ARCHNames
static const ArchNames< ArchKind > ARCHNames[]
Definition: ARMTargetParser.h:223
llvm::ARM::parseCPUArch
ArchKind parseCPUArch(StringRef CPU)
Definition: ARMTargetParser.cpp:582
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:219
llvm::ARM::parseArch
ArchKind parseArch(StringRef Arch)
Definition: ARMTargetParser.cpp:28
llvm::ARM::getDefaultExtensions
uint64_t getDefaultExtensions(StringRef CPU, ArchKind AK)
Definition: ARMTargetParser.cpp:379
llvm::None
const NoneType None
Definition: None.h:23
llvm::ARM::NeonSupportLevel
NeonSupportLevel
Definition: ARMTargetParser.h:156
llvm::ARM::appendArchExtFeatures
bool appendArchExtFeatures(StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector< StringRef > &Features, unsigned &ArgFPUKind)
Definition: ARMTargetParser.cpp:498
llvm::ARM::parseArchEndian
EndianKind parseArchEndian(StringRef Arch)
Definition: ARMTargetParser.cpp:231
llvm::ARM::AEK_INVALID
@ AEK_INVALID
Definition: ARMTargetParser.h:31
llvm::AArch64::getDefaultFPU
unsigned getDefaultFPU(StringRef CPU, ArchKind AK)
Definition: AArch64TargetParser.cpp:27
llvm::ARM::FPUName::FPUVer
FPUVersion FPUVer
Definition: ARMTargetParser.h:181
llvm::ARM::AEK_HWDIVARM
@ AEK_HWDIVARM
Definition: ARMTargetParser.h:37
parseArch
static Triple::ArchType parseArch(StringRef ArchName)
Definition: Triple.cpp:403
llvm::ARM::HWDivNames
const struct llvm::ARM::@336 HWDivNames[]
llvm::ARM::parseHWDiv
uint64_t parseHWDiv(StringRef HWDiv)
Definition: ARMTargetParser.cpp:565
llvm::Triple::Android
@ Android
Definition: Triple.h:217
D
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
findDoublePrecisionFPU
static unsigned findDoublePrecisionFPU(unsigned InputFPUKind)
Definition: ARMTargetParser.cpp:469
llvm::ARM::getFPUSynonym
StringRef getFPUSynonym(StringRef FPU)
Definition: ARMTargetParser.cpp:333
llvm::AArch64::getArchName
StringRef getArchName(ArchKind AK)
Definition: AArch64TargetParser.cpp:135
ARMTargetParser.h
llvm::ARM::CpuNames
Definition: ARMTargetParser.h:114
llvm::ARM::FPURestriction::D16
@ D16
Only 16 D registers.
llvm::AArch64::parseCPUArch
ArchKind parseCPUArch(StringRef CPU)
Definition: AArch64TargetParser.cpp:221
llvm::ARM::parseArchVersion
unsigned parseArchVersion(StringRef Arch)
Definition: ARMTargetParser.cpp:39
llvm::ARM::getDefaultFPU
unsigned getDefaultFPU(StringRef CPU, ArchKind AK)
Definition: ARMTargetParser.cpp:368
llvm::FK_NONE
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
Triple.h
llvm::ARM::getSubArch
StringRef getSubArch(ArchKind AK)
Definition: ARMTargetParser.cpp:435
llvm::ARM::ISAKind
ISAKind
Definition: ARMTargetParser.h:163
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::ARM::parseArchISA
ISAKind parseArchISA(StringRef Arch)
Definition: ARMTargetParser.cpp:250
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
A
* A
Definition: README_ALTIVEC.txt:89
llvm::ARM::getHWDivName
StringRef getHWDivName(uint64_t HWDivKind)
Definition: ARMTargetParser.cpp:542
llvm::StringSwitch::Cases
StringSwitch & Cases(StringLiteral S0, StringLiteral S1, T Value)
Definition: StringSwitch.h:88
llvm::ARM::getHWDivFeatures
bool getHWDivFeatures(uint64_t HWDivKind, std::vector< StringRef > &Features)
Definition: ARMTargetParser.cpp:392
getHWDivSynonym
static StringRef getHWDivSynonym(StringRef HWDiv)
Definition: ARMTargetParser.cpp:21
llvm::ARM::getFPUNeonSupportLevel
NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind)
Definition: ARMTargetParser.cpp:268
llvm::ARM::getDefaultCPU
StringRef getDefaultCPU(StringRef Arch)
Definition: ARMTargetParser.cpp:550
llvm::ARM::getExtensionFeatures
bool getExtensionFeatures(uint64_t Extensions, std::vector< StringRef > &Features)
Definition: ARMTargetParser.cpp:411
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
llvm::ARM::ArchKind
ArchKind
Definition: ARMTargetParser.h:104
llvm::ARM::parseFPU
unsigned parseFPU(StringRef FPU)
Definition: ARMTargetParser.cpp:259
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::RISCV::FK_INVALID
@ FK_INVALID
Definition: TargetParser.h:155
llvm::ARM::getFPURestriction
FPURestriction getFPURestriction(unsigned FPUKind)
Definition: ARMTargetParser.cpp:362
llvm::AArch64::getSubArch
StringRef getSubArch(ArchKind AK)
Definition: AArch64TargetParser.cpp:143
StringSwitch.h
llvm::ARM::getFPUName
StringRef getFPUName(unsigned FPUKind)
Definition: ARMTargetParser.cpp:350
llvm::ARM::getFPUVersion
FPUVersion getFPUVersion(unsigned FPUKind)
Definition: ARMTargetParser.cpp:356
llvm::NONE
@ NONE
Definition: Attributor.h:3844
llvm::ARM::computeDefaultTargetABI
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
Definition: ARMTargetParser.cpp:597
llvm::ARM::parseArchExt
uint64_t parseArchExt(StringRef ArchExt)
Definition: ARMTargetParser.cpp:574
llvm::SmallVectorImpl< StringRef >
llvm::Triple::EABIHF
@ EABIHF
Definition: Triple.h:216
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:211
llvm::Triple::UnknownOS
@ UnknownOS
Definition: Triple.h:165
llvm::ARM::FPUName::Restriction
FPURestriction Restriction
Definition: ARMTargetParser.h:183
llvm::Triple::EABI
@ EABI
Definition: Triple.h:215
llvm::ARM::getArchExtFeature
StringRef getArchExtFeature(StringRef ArchExt)
Definition: ARMTargetParser.cpp:459
llvm::ARM::FPUVersion
FPUVersion
Definition: ARMTargetParser.h:138
llvm::ARM::getArchExtName
StringRef getArchExtName(uint64_t ArchExtKind)
Definition: ARMTargetParser.cpp:443
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38