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37 return ConstantPools->addEntry(
Streamer, Expr, 4, Loc);
41 ConstantPools->emitForCurrentSection(
Streamer);
42 ConstantPools->clearCacheForCurrentSection(
Streamer);
62 for (
unsigned II = 0,
IE = Size; II !=
IE; II++) {
63 const unsigned I = LittleEndian ? (Size - II - 1) : II;
64 Buffer[Size - II - 1] = uint8_t(Inst >>
I * CHAR_BIT);
70 Size = (Suffix ==
'n' ? 2 : 4);
74 for (
unsigned II = 0,
IE = Size; II !=
IE; II = II + 2) {
75 const unsigned I0 = LittleEndian ? II + 0 : II + 1;
76 const unsigned I1 = LittleEndian ? II + 1 : II + 0;
77 Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT);
78 Buffer[Size - II - 1] = uint8_t(Inst >>
I1 * CHAR_BIT);
133 if (STI.
getCPU() ==
"xscale")
142 }
else if (STI.
hasFeature(ARM::HasV8_1MMainlineOps))
144 else if (STI.
hasFeature(ARM::HasV8MMainlineOps))
152 else if (STI.
hasFeature(ARM::HasV8MBaselineOps))
170 return (STI.
hasFeature(ARM::HasV8MBaselineOps) &&
200 }
else if (STI.
hasFeature(ARM::FeatureRClass)) {
203 }
else if (STI.
hasFeature(ARM::FeatureMClass)) {
215 }
else if (STI.
hasFeature(ARM::FeatureThumb2)) {
227 emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
229 emitFPU(ARM::FK_NEON_FP_ARMV8);
242 if (STI.
hasFeature(ARM::FeatureFPARMv8_D16_SP))
247 : (STI.
hasFeature(ARM::FeatureFP64) ? ARM::FK_FPV5_D16
248 : ARM::FK_FPV5_SP_D16));
249 else if (STI.
hasFeature(ARM::FeatureVFP4_D16_SP))
252 : (STI.
hasFeature(ARM::FeatureFP64) ? ARM::FK_VFPV4_D16
253 : ARM::FK_FPV4_SP_D16));
254 else if (STI.
hasFeature(ARM::FeatureVFP3_D16_SP))
258 ? (STI.
hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
263 ? ARM::FK_VFPV3_D16_FP16
265 : (STI.
hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
266 : ARM::FK_VFPV3XD)));
284 else if (STI.
hasFeature(ARM::HasMVEIntegerOps))
310 else if (STI.
hasFeature(ARM::FeatureTrustZone))
312 else if (STI.
hasFeature(ARM::FeatureVirtualization))
325 if (TT.isOSBinFormatELF())
327 if (TT.isOSBinFormatCOFF())
MCStreamer & getStreamer()
virtual void emitCantUnwind()
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
This is an optimization pass for GlobalISel generic memory operations.
MCTargetStreamer * createARMObjectTargetWinCOFFStreamer(MCStreamer &S)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
virtual void emitPersonality(const MCSymbol *Personality)
MCTargetStreamer * createARMObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Reg
All possible values of the reg field in the ModR/M byte.
Triple - Helper class for working with autoconf configuration names.
virtual void emitARMWinCFINop(bool Wide)
virtual void emitARMWinCFIAllocStack(unsigned Size, bool Wide)
ARMTargetStreamer(MCStreamer &S)
virtual void reset()
Reset any state between object emissions, i.e.
virtual void emitPad(int64_t Offset)
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Streaming machine code generation interface.
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
Represents a location in source code.
virtual void emitInst(uint32_t Inst, char Suffix='\0')
bool hasFeature(unsigned Feature) const
static bool isV8M(const MCSubtargetInfo &STI)
const Triple & getTargetTriple() const
virtual void emitArch(ARM::ArchKind Arch)
MCTargetStreamer * createARMObjectTargetELFStreamer(MCStreamer &S)
Target specific streamer interface.
virtual void emitARMWinCFIPrologEnd(bool Fragment)
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
virtual void emitARMWinCFISaveRegMask(unsigned Mask, bool Wide)
virtual void emitARMWinCFIEpilogStart(unsigned Condition)
virtual void emitObjectArch(ARM::ArchKind Arch)
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
const MCAsmInfo * getAsmInfo() const
virtual void emitARMWinCFIEpilogEnd()
virtual void emitHandlerData()
const MCExpr * addConstantPoolEntry(const MCExpr *, SMLoc Loc)
Callback used to implement the ldr= pseudo.
virtual void switchVendor(StringRef Vendor)
virtual void emitThumbSet(MCSymbol *Symbol, const MCExpr *Value)
virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue="")
Represent a reference to a symbol from inside an expression.
virtual void emitPersonalityIndex(unsigned Index)
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
@ AllowMVEIntegerAndFloat
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI)
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
virtual void emitUnwindRaw(int64_t StackOffset, const SmallVectorImpl< uint8_t > &Opcodes)
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
virtual void emitAttribute(unsigned Attribute, unsigned Value)
bool isLittleEndian() const
True if the target is little endian.
~ARMTargetStreamer() override
virtual void emitFnStart()
virtual void emitARMWinCFISaveFRegs(unsigned First, unsigned Last)
LegalityPredicate isVector(unsigned TypeIdx)
True iff the specified type index is a vector.
MCContext & getContext() const
virtual void emitARMWinCFISaveSP(unsigned Reg)
virtual void emitArchExtension(uint64_t ArchExt)
virtual void emitARMWinCFISaveLR(unsigned Offset)
virtual void emitBytes(StringRef Data)
Emit the bytes in Data into the output.
virtual void finishAttributeSection()
void emitCurrentConstantPool()
Callback used to implement the .ltorg directive.
virtual void emitARMWinCFICustom(unsigned Opcode)
Generic base class for all target subtargets.
virtual void emitFPU(unsigned FPU)
LLVM Value Representation.
void emitConstantPools() override
Base class for the full range of assembler expressions which are needed for parsing.
virtual void annotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE)