LLVM 17.0.0git
ARMSubtarget.cpp
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1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARM.h"
14
15#include "ARMCallLowering.h"
16#include "ARMFrameLowering.h"
17#include "ARMInstrInfo.h"
18#include "ARMLegalizerInfo.h"
19#include "ARMRegisterBankInfo.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
23#include "Thumb1FrameLowering.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb2InstrInfo.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/Twine.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/GlobalValue.h"
33#include "llvm/MC/MCAsmInfo.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE "arm-subtarget"
44
45#define GET_SUBTARGETINFO_TARGET_DESC
46#define GET_SUBTARGETINFO_CTOR
47#include "ARMGenSubtargetInfo.inc"
48
49static cl::opt<bool>
50UseFusedMulOps("arm-use-mulops",
51 cl::init(true), cl::Hidden);
52
53enum ITMode {
56};
57
58static cl::opt<ITMode>
59 IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT),
60 cl::values(clEnumValN(DefaultIT, "arm-default-it",
61 "Generate any type of IT block"),
62 clEnumValN(RestrictedIT, "arm-restrict-it",
63 "Disallow complex IT blocks")));
64
65/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
66/// currently supported (for testing only).
67static cl::opt<bool>
68ForceFastISel("arm-force-fast-isel",
69 cl::init(false), cl::Hidden);
70
71static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness",
72 cl::init(false), cl::Hidden);
73
74/// initializeSubtargetDependencies - Initializes using a CPU and feature string
75/// so that we can use initializer lists for subtarget initialization.
77 StringRef FS) {
78 initializeEnvironment();
79 initSubtargetFeatures(CPU, FS);
80 return *this;
81}
82
83ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
84 StringRef FS) {
86 if (STI.isThumb1Only())
87 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
88
89 return new ARMFrameLowering(STI);
90}
91
92ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
93 const std::string &FS,
94 const ARMBaseTargetMachine &TM, bool IsLittle,
95 bool MinSize)
96 : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
97 UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
98 IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
99 FrameLowering(initializeFrameLowering(CPU, FS)),
100 // At this point initializeSubtargetDependencies has been called so
101 // we can query directly.
102 InstrInfo(isThumb1Only()
103 ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
104 : !isThumb()
105 ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
106 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
107 TLInfo(TM, *this) {
108
109 CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
110 Legalizer.reset(new ARMLegalizerInfo(*this));
111
112 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
113
114 // FIXME: At this point, we can't rely on Subtarget having RBI.
115 // It's awkward to mix passing RBI and the Subtarget; should we pass
116 // TII/TRI as well?
117 InstSelector.reset(createARMInstructionSelector(
118 *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
119
120 RegBankInfo.reset(RBI);
121}
122
124 return CallLoweringInfo.get();
125}
126
128 return InstSelector.get();
129}
130
132 return Legalizer.get();
133}
134
136 return RegBankInfo.get();
137}
138
140 // We don't currently suppport Thumb, but Windows requires Thumb.
141 return hasV6Ops() && hasARMOps() && !isTargetWindows();
142}
143
144void ARMSubtarget::initializeEnvironment() {
145 // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
146 // directly from it, but we can try to make sure they're consistent when both
147 // available.
151 assert((!TM.getMCAsmInfo() ||
154 "inconsistent sjlj choice between CodeGen and MC");
155}
156
157void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
158 if (CPUString.empty()) {
159 CPUString = "generic";
160
161 if (isTargetDarwin()) {
163 ARM::ArchKind AK = ARM::parseArch(ArchName);
164 if (AK == ARM::ArchKind::ARMV7S)
165 // Default to the Swift CPU when targeting armv7s/thumbv7s.
166 CPUString = "swift";
167 else if (AK == ARM::ArchKind::ARMV7K)
168 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
169 // ARMv7k does not use SjLj exception handling.
170 CPUString = "cortex-a7";
171 }
172 }
173
174 // Insert the architecture feature derived from the target triple into the
175 // feature string. This is important for setting features that are implied
176 // based on the architecture version.
177 std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
178 if (!FS.empty()) {
179 if (!ArchFS.empty())
180 ArchFS = (Twine(ArchFS) + "," + FS).str();
181 else
182 ArchFS = std::string(FS);
183 }
184 ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
185
186 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
187 // Assert this for now to make the change obvious.
188 assert(hasV6T2Ops() || !hasThumb2());
189
190 // Execute only support requires movt support
191 if (genExecuteOnly()) {
192 NoMovt = false;
193 assert(hasV8MBaselineOps() && "Cannot generate execute-only code for this target");
194 }
195
196 // Keep a pointer to static instruction cost data for the specified CPU.
197 SchedModel = getSchedModelForCPU(CPUString);
198
199 // Initialize scheduling itinerary for the specified CPU.
200 InstrItins = getInstrItineraryForCPU(CPUString);
201
202 // FIXME: this is invalid for WindowsCE
203 if (isTargetWindows())
204 NoARM = true;
205
206 if (isAAPCS_ABI())
208 if (isTargetNaCl() || isAAPCS16_ABI())
209 stackAlignment = Align(16);
210
211 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
212 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
213 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
214 // support in the assembler and linker to be used. This would need to be
215 // fixed to fully support tail calls in Thumb1.
216 //
217 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
218 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
219 // means if we need to reload LR, it takes extra instructions, which outweighs
220 // the value of the tail call; but here we don't know yet whether LR is going
221 // to be used. We take the optimistic approach of generating the tail call and
222 // perhaps taking a hit if we need to restore the LR.
223
224 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
225 // but we need to make sure there are enough registers; the only valid
226 // registers are the 4 used for parameters. We don't currently do this
227 // case.
228
229 SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
230
231 if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
232 SupportsTailCall = false;
233
234 switch (IT) {
235 case DefaultIT:
236 RestrictIT = false;
237 break;
238 case RestrictedIT:
239 RestrictIT = true;
240 break;
241 }
242
243 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
244 const FeatureBitset &Bits = getFeatureBits();
245 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
247 HasNEONForFP = true;
248
249 if (isRWPI())
250 ReserveR9 = true;
251
252 // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
253 if (MVEVectorCostFactor == 0)
255
256 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
257 switch (ARMProcFamily) {
258 case Others:
259 case CortexA5:
260 break;
261 case CortexA7:
263 break;
264 case CortexA8:
266 break;
267 case CortexA9:
270 break;
271 case CortexA12:
272 break;
273 case CortexA15:
277 break;
278 case CortexA17:
279 case CortexA32:
280 case CortexA35:
281 case CortexA53:
282 case CortexA55:
283 case CortexA57:
284 case CortexA72:
285 case CortexA73:
286 case CortexA75:
287 case CortexA76:
288 case CortexA77:
289 case CortexA78:
290 case CortexA78C:
291 case CortexA710:
292 case CortexR4:
293 case CortexR4F:
294 case CortexR5:
295 case CortexR7:
296 case CortexM3:
297 case CortexM7:
298 case CortexR52:
299 case CortexX1:
300 case CortexX1C:
301 break;
302 case Exynos:
305 if (!isThumb())
307 break;
308 case Kryo:
309 break;
310 case Krait:
312 break;
313 case NeoverseN1:
314 case NeoverseN2:
315 case NeoverseV1:
316 break;
317 case Swift:
322 break;
323 }
324}
325
327
331}
336}
340}
341
343 return TM.getRelocationModel() == Reloc::ROPI ||
345}
347 return TM.getRelocationModel() == Reloc::RWPI ||
349}
350
352 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
353 return true;
354
355 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
356 // the section that is being relocated. This means we have to use o load even
357 // for GVs that are known to be local to the dso.
360 return true;
361
362 return false;
363}
364
366 return isTargetELF() && TM.isPositionIndependent() &&
367 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
368}
369
372}
373
375 // The MachineScheduler can increase register usage, so we use more high
376 // registers and end up with more T2 instructions that cannot be converted to
377 // T1 instructions. At least until we do better at converting to thumb1
378 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
379 // Machine scheduler, relying on the DAG register pressure scheduler instead.
380 if (isMClass() && hasMinSize())
381 return false;
382 // Enable the MachineScheduler before register allocation for subtargets
383 // with the use-misched feature.
384 return useMachineScheduler();
385}
386
388 if (EnableSubRegLiveness.getNumOccurrences())
390 // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
391 // and q subregs for qqqqpr regs.
392 return hasMVEIntegerOps();
393}
394
396 // Enable the MachinePipeliner before register allocation for subtargets
397 // with the use-mipipeliner feature.
398 return getSchedModel().hasInstrSchedModel() && useMachinePipeliner();
399}
400
401bool ARMSubtarget::useDFAforSMS() const { return false; }
402
403// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
406 return false;
407 if (disablePostRAScheduler())
408 return false;
409 // Thumb1 cores will generally not benefit from post-ra scheduling
410 return !isThumb1Only();
411}
412
415 return false;
416 if (disablePostRAScheduler())
417 return false;
418 return !isThumb1Only();
419}
420
422 // For general targets, the prologue can grow when VFPs are allocated with
423 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
424 // format which it's more important to get right.
425 return isTargetWatchABI() ||
426 (useWideStrideVFP() && !OptMinSize);
427}
428
430 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
431 // immediates as it is inherently position independent, and may be out of
432 // range otherwise.
433 return !NoMovt && hasV8MBaselineOps() &&
434 (isTargetWindows() || !OptMinSize || genExecuteOnly());
435}
436
438 // Enable fast-isel for any target, for testing only.
439 if (ForceFastISel)
440 return true;
441
442 // Limit fast-isel to the targets that are or have been tested.
443 if (!hasV6Ops())
444 return false;
445
446 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
447 return TM.Options.EnableFastISel &&
448 ((isTargetMachO() && !isThumb1Only()) ||
449 (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
450}
451
453 // The GPR register class has multiple possible allocation orders, with
454 // tradeoffs preferred by different sub-architectures and optimisation goals.
455 // The allocation orders are:
456 // 0: (the default tablegen order, not used)
457 // 1: r14, r0-r13
458 // 2: r0-r7
459 // 3: r0-r7, r12, lr, r8-r11
460 // Note that the register allocator will change this order so that
461 // callee-saved registers are used later, as they require extra work in the
462 // prologue/epilogue (though we sometimes override that).
463
464 // For thumb1-only targets, only the low registers are allocatable.
465 if (isThumb1Only())
466 return 2;
467
468 // Allocate low registers first, so we can select more 16-bit instructions.
469 // We also (in ignoreCSRForAllocationOrder) override the default behaviour
470 // with regards to callee-saved registers, because pushing extra registers is
471 // much cheaper (in terms of code size) than using high registers. After
472 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
473 // can return with the pop, don't need an extra "bx lr") and then the rest of
474 // the high registers.
475 if (isThumb2() && MF.getFunction().hasMinSize())
476 return 3;
477
478 // Otherwise, allocate in the default order, using LR first because saving it
479 // allows a shorter epilogue sequence.
480 return 1;
481}
482
484 unsigned PhysReg) const {
485 // To minimize code size in Thumb2, we prefer the usage of low regs (lower
486 // cost per use) so we can use narrow encoding. By default, caller-saved
487 // registers (e.g. lr, r12) are always allocated first, regardless of
488 // their cost per use. When optForMinSize, we prefer the low regs even if
489 // they are CSR because usually push/pop can be folded into existing ones.
490 return isThumb2() && MF.getFunction().hasMinSize() &&
491 ARM::GPRRegClass.contains(PhysReg);
492}
493
495 const Function &F = MF.getFunction();
496 if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI() ||
497 !F.needsUnwindTableEntry())
498 return false;
499 const MachineFrameInfo &MFI = MF.getFrameInfo();
500 return MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF);
501}
static bool isThumb(const MCSubtargetInfo &STI)
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for ARM.
This file declares the targeting of the RegisterBankInfo class for ARM.
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
static cl::opt< bool > EnableSubRegLiveness("arm-enable-subreg-liveness", cl::init(false), cl::Hidden)
ITMode
@ RestrictedIT
@ DefaultIT
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
Definition: CommandLine.h:678
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
static cl::opt< bool > EnableSubRegLiveness("enable-subreg-liveness", cl::Hidden, cl::init(true), cl::desc("Enable subregister liveness tracking."))
const char LLVMTargetMachineRef TM
return InstrInfo
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
This class provides the information for the target register banks.
This class provides the information for the target register banks.
bool useFastISel() const
True if fast-isel is used.
bool isTargetMachO() const
Definition: ARMSubtarget.h:371
bool useMovt() const
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Definition: ARMSubtarget.h:195
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
bool hasARMOps() const
Definition: ARMSubtarget.h:324
const Triple & getTargetTriple() const
Definition: ARMSubtarget.h:357
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
Definition: ARMSubtarget.h:179
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
const RegisterBankInfo * getRegBankInfo() const override
unsigned MaxInterleaveFactor
Definition: ARMSubtarget.h:188
const ARMBaseTargetMachine & TM
Definition: ARMSubtarget.h:228
bool isThumb1Only() const
Definition: ARMSubtarget.h:419
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Definition: ARMSubtarget.h:157
bool isThumb2() const
Definition: ARMSubtarget.h:420
bool useDFAforSMS() const override
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
bool isAAPCS16_ABI() const
bool isTargetWindows() const
Definition: ARMSubtarget.h:367
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
Definition: ARMSubtarget.h:207
const ARMTargetLowering * getTargetLowering() const override
Definition: ARMSubtarget.h:266
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
Definition: ARMSubtarget.h:220
std::string CPUString
CPUString - String name of used CPU.
Definition: ARMSubtarget.h:186
unsigned getMispredictionPenalty() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Definition: ARMSubtarget.h:217
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
bool isTargetDarwin() const
Definition: ARMSubtarget.h:359
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:274
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Definition: ARMSubtarget.h:223
bool useStride4VFPs() const
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
Definition: ARMSubtarget.h:211
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
Definition: ARMSubtarget.h:176
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
Definition: ARMSubtarget.h:202
bool isROPI() const
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
Definition: ARMSubtarget.h:183
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
Definition: ARMSubtarget.h:191
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
InstructionSelector * getInstructionSelector() const override
bool isAPCS_ABI() const
bool isXRaySupported() const override
const CallLowering * getCallLowering() const override
bool hasMinSize() const
Definition: ARMSubtarget.h:418
bool splitFramePointerPush(const MachineFunction &MF) const
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
bool isTargetIOS() const
Definition: ARMSubtarget.h:360
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool isTargetNaCl() const
Definition: ARMSubtarget.h:365
bool isTargetWatchABI() const
Definition: ARMSubtarget.h:362
const TargetOptions & Options
Options passed via command line that could influence the target.
Definition: ARMSubtarget.h:226
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
Definition: ARMSubtarget.h:142
@ DoubleIssue
Can load/store 2 registers/cycle.
Definition: ARMSubtarget.h:139
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
Definition: ARMSubtarget.h:147
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool useMachinePipeliner() const
Definition: ARMSubtarget.h:417
bool isAAPCS_ABI() const
bool useMachineScheduler() const
Definition: ARMSubtarget.h:416
bool isRWPI() const
const LegalizerInfo * getLegalizerInfo() const override
bool isTargetLinux() const
Definition: ARMSubtarget.h:364
bool isMClass() const
Definition: ARMSubtarget.h:421
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
Definition: ARMSubtarget.h:172
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
Definition: ARMSubtarget.h:199
bool isTargetHardFloat() const
bool isTargetELF() const
Definition: ARMSubtarget.h:370
Container class for subtarget features.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:642
bool isDeclarationForLinker() const
Definition: GlobalValue.h:614
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:652
bool hasCommonLinkage() const
Definition: GlobalValue.h:527
Provides the logic to select generic machine instructions.
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:799
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Holds all the information related to register banks.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool isPositionIndependent() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
TargetOptions Options
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
ExceptionHandling ExceptionModel
What exception model to use.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
StringRef getArchName() const
Get the architecture (first) component of the triple.
Definition: Triple.cpp:1144
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
ArchKind parseArch(StringRef Arch)
@ ROPI_RWPI
Definition: CodeGen.h:25
@ FS
Definition: X86.h:208
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
Definition: CommandLine.h:703
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
@ SjLj
setjmp/longjmp based exceptions
@ None
No exception support.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
unsigned MispredictPenalty
Definition: MCSchedule.h:309