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44 #define DEBUG_TYPE "arm-subtarget"
46 #define GET_SUBTARGETINFO_TARGET_DESC
47 #define GET_SUBTARGETINFO_CTOR
48 #include "ARMGenSubtargetInfo.inc"
62 "Generate any type of IT block"),
64 "Disallow complex IT blocks")));
79 initializeEnvironment();
80 initSubtargetFeatures(CPU,
FS);
94 const std::string &
FS,
100 FrameLowering(initializeFrameLowering(CPU,
FS)),
121 RegBankInfo.reset(RBI);
125 return CallLoweringInfo.get();
129 return InstSelector.get();
137 return RegBankInfo.get();
145 void ARMSubtarget::initializeEnvironment() {
155 "inconsistent sjlj choice between CodeGen and MC");
165 if (AK == ARM::ArchKind::ARMV7S)
168 else if (AK == ARM::ArchKind::ARMV7K)
181 ArchFS = (
Twine(ArchFS) +
"," +
FS).str();
183 ArchFS = std::string(
FS);
189 assert(hasV6T2Ops() || !hasThumb2());
192 if (genExecuteOnly()) {
194 assert(hasV8MBaselineOps() &&
"Cannot generate execute-only code for this target");
246 if ((
Bits[ARM::ProcA5] ||
Bits[ARM::ProcA8]) &&
393 return hasMVEIntegerOps();
408 if (disablePostRAScheduler())
417 if (disablePostRAScheduler())
434 return !NoMovt && hasV8MBaselineOps() &&
485 unsigned PhysReg)
const {
492 ARM::GPRRegClass.contains(PhysReg);
498 !
F.needsUnwindTableEntry())
bool SupportsTailCall
SupportsTailCall - True if the OS supports tail call.
bool UseSjLjEH
UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const ARMBaseTargetMachine & TM
bool enableSubRegLiveness() const override
Check whether this subtarget wants to use subregister liveness.
This is an optimization pass for GlobalISel generic memory operations.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool hasCommonLinkage() const
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
const LegalizerInfo * getLegalizerInfo() const override
bool enableMachineScheduler() const override
Returns true if machine scheduler should be enabled.
@ SjLj
setjmp/longjmp based exceptions
unsigned getMispredictionPenalty() const
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
Triple - Helper class for working with autoconf configuration names.
static cl::opt< ITMode > IT(cl::desc("IT block support"), cl::Hidden, cl::init(DefaultIT), cl::values(clEnumValN(DefaultIT, "arm-default-it", "Generate any type of IT block"), clEnumValN(RestrictedIT, "arm-restrict-it", "Disallow complex IT blocks")))
const Triple & getTargetTriple() const
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
const ARMTargetLowering * getTargetLowering() const override
Container class for subtarget features.
bool isTargetLinux() const
bool isTargetWatchABI() const
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
bool OptMinSize
OptMinSize - True if we're optimising for minimum code size, equal to the function attribute.
This class provides the information for the target register banks.
unsigned MispredictPenalty
bool isTargetHardFloat() const
static cl::opt< bool > EnableSubRegLiveness("arm-enable-subreg-liveness", cl::init(false), cl::Hidden)
MCSchedModel SchedModel
SchedModel - Processor specific instruction costs.
unsigned MaxInterleaveFactor
@ DoubleIssue
Can load/store 2 registers/cycle.
bool isTargetHardFloat() const
bool isAAPCS16_ABI() const
ExceptionHandling ExceptionModel
What exception model to use.
@ DoubleIssueCheckUnalignedAccess
Can load/store 2 registers/cycle, but needs an extra cycle if the access is not 64-bit aligned.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
int getNumOccurrences() const
unsigned PrefLoopLogAlignment
What alignment is preferred for loop bodies, in log2(bytes).
StringRef getArchName() const
Get the architecture (first) component of the triple.
bool enablePostRAScheduler() const override
True for some subtargets at > -O0.
static bool isThumb(const MCSubtargetInfo &STI)
ArchKind parseArch(StringRef Arch)
bool useMachinePipeliner() const
const RegisterBankInfo * getRegBankInfo() const override
bool isPositionIndependent() const
Triple TargetTriple
TargetTriple - What processor and OS we're targeting.
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
ValuesClass values(OptsTy... Options)
Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...
bool isThumb1Only() const
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
ARMLdStMultipleTiming LdStMultipleTiming
What kind of timing do load multiple/store multiple have (double issue, single issue etc).
Module * getParent()
Get the module that this global value is contained inside of...
ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize=false)
This constructor initializes the data members to match that of the specified triple.
Align stackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
ARMSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU and feature string so that we can use initi...
initializer< Ty > init(const Ty &Val)
std::string CPUString
CPUString - String name of used CPU.
unsigned MVEVectorCostFactor
The cost factor for MVE instructions, representing the multiple beats an.
const TargetOptions & Options
Options passed via command line that could influence the target.
bool RestrictIT
RestrictIT - If true, the subtarget disallows generation of complex IT blocks.
bool useDFAforSMS() const override
bool splitFramePointerPush(const MachineFunction &MF) const
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool enablePostRAMachineScheduler() const override
True for some subtargets at > -O0.
bool useFastISel() const
True if fast-isel is used.
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
This class provides the information for the target register banks.
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
const CallLowering * getCallLowering() const override
const ARMBaseRegisterInfo * getRegisterInfo() const override
StringRef - Represent a constant reference to a string, i.e.
Analysis the ScalarEvolution expression for r is this
bool useMachineScheduler() const
unsigned PartialUpdateClearance
Clearance before partial register updates (in number of instructions)
#define clEnumValN(ENUMVAL, FLAGNAME, DESC)
InstructionSelector * getInstructionSelector() const override
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
int PreISelOperandLatencyAdjustment
The adjustment that we need to apply to get the operand latency from the operand cycle returned by th...
bool isTargetWindows() const
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Function & getFunction()
Return the LLVM function that this machine code represents.
bool isTargetDarwin() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
bool isTargetMachO() const
@ SingleIssuePlusExtras
Can load/store 1 register/cycle, but needs an extra cycle for address computation and potentially als...
bool enableMachinePipeliner() const override
Returns true if machine pipeliner should be enabled.
@ None
No exception support.
enum llvm::ARMBaseTargetMachine::ARMABI TargetABI
ExceptionHandling getExceptionHandlingType() const
static cl::opt< bool > ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden)
ForceFastISel - Use the fast-isel, even for subtargets where it is not currently supported (for testi...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isDeclarationForLinker() const
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
const char LLVMTargetMachineRef TM
unsigned getGPRAllocationOrder(const MachineFunction &MF) const
bool usesWindowsCFI() const
bool isTargetNaCl() const
bool isXRaySupported() const override
bool useStride4VFPs() const
static cl::opt< bool > UseFusedMulOps("arm-use-mulops", cl::init(true), cl::Hidden)