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Thumb2InstrInfo.h
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1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ThumbRegisterInfo.h"
18 
19 namespace llvm {
20 class ARMSubtarget;
21 class ScheduleHazardRecognizer;
22 
25 public:
26  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
27 
28  /// Return the noop instruction to use for a noop.
29  void getNoop(MCInst &NopInst) const override;
30 
31  // Return the non-pre/post incrementing version of 'Opc'. Return 0
32  // if there is not such an opcode.
33  unsigned getUnindexedOpcode(unsigned Opc) const override;
34 
36  MachineBasicBlock *NewDest) const override;
37 
39  MachineBasicBlock::iterator MBBI) const override;
40 
42  const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
43  bool KillSrc) const override;
44 
47  unsigned SrcReg, bool isKill, int FrameIndex,
48  const TargetRegisterClass *RC,
49  const TargetRegisterInfo *TRI) const override;
50 
53  unsigned DestReg, int FrameIndex,
54  const TargetRegisterClass *RC,
55  const TargetRegisterInfo *TRI) const override;
56 
57  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
58  /// such, whenever a client has an instance of instruction info, it should
59  /// always be able to get register info as well (through this method).
60  ///
61  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
62 
63 private:
64  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
65 };
66 
67 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
68 /// to llvm::getInstrPredicate except it returns AL for conditional branch
69 /// instructions which are "predicated", but are not in IT blocks.
70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
71 
72 // getVPTInstrPredicate: VPT analogue of that, plus a helper function
73 // corresponding to MachineInstr::findFirstPredOperandIdx.
76  unsigned &PredReg);
77 }
78 
79 #endif
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
unsigned getUnindexedOpcode(unsigned Opc) const override
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
void getNoop(MCInst &NopInst) const override
Return the noop instruction to use for a noop.
Thumb2InstrInfo(const ARMSubtarget &STI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
Representation of each machine instruction.
Definition: MachineInstr.h:64
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, unsigned &PredReg)
#define I(x, y, z)
Definition: MD5.cpp:58
IRTranslator LLVM IR MI