LLVM  15.0.0git
Thumb2InstrInfo.h
Go to the documentation of this file.
1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15 
16 #include "ARMBaseInstrInfo.h"
17 #include "ThumbRegisterInfo.h"
18 
19 namespace llvm {
20 class ARMSubtarget;
21 
24 public:
25  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
26 
27  /// Return the noop instruction to use for a noop.
28  MCInst getNop() const override;
29 
30  // Return the non-pre/post incrementing version of 'Opc'. Return 0
31  // if there is not such an opcode.
32  unsigned getUnindexedOpcode(unsigned Opc) const override;
33 
35  MachineBasicBlock *NewDest) const override;
36 
38  MachineBasicBlock::iterator MBBI) const override;
39 
41  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42  bool KillSrc) const override;
43 
46  Register SrcReg, bool isKill, int FrameIndex,
47  const TargetRegisterClass *RC,
48  const TargetRegisterInfo *TRI) const override;
49 
52  Register DestReg, int FrameIndex,
53  const TargetRegisterClass *RC,
54  const TargetRegisterInfo *TRI) const override;
55 
56  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
57  /// such, whenever a client has an instance of instruction info, it should
58  /// always be able to get register info as well (through this method).
59  ///
60  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
61 
64  bool) const override;
65 
67  unsigned OpIdx1,
68  unsigned OpIdx2) const override;
69 
70 private:
71  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
72 };
73 
74 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
75 /// to llvm::getInstrPredicate except it returns AL for conditional branch
76 /// instructions which are "predicated", but are not in IT blocks.
77 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);
78 
79 // getVPTInstrPredicate: VPT analogue of that, plus a helper function
80 // corresponding to MachineInstr::findFirstPredOperandIdx.
81 int findFirstVPTPredOperandIdx(const MachineInstr &MI);
82 ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
83  Register &PredReg);
85  Register PredReg;
86  return getVPTInstrPredicate(MI, PredReg);
87 }
88 
89 // Recomputes the Block Mask of Instr, a VPT or VPST instruction.
90 // This rebuilds the block mask of the instruction depending on the predicates
91 // of the instructions following it. This should only be used after the
92 // MVEVPTBlockInsertion pass has run, and should be used whenever a predicated
93 // instruction is added to/removed from the block.
94 void recomputeVPTBlockMask(MachineInstr &Instr);
95 } // namespace llvm
96 
97 #endif
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::Thumb2InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:207
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:232
llvm::Thumb2InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: Thumb2InstrInfo.cpp:150
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::getITInstrPredicate
ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg)
getITInstrPredicate - Valid only in Thumb2 mode.
Definition: Thumb2InstrInfo.cpp:766
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::Thumb2InstrInfo::optimizeSelect
MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
Definition: Thumb2InstrInfo.cpp:126
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::Thumb2InstrInfo::getUnindexedOpcode
unsigned getUnindexedOpcode(unsigned Opc) const override
Definition: Thumb2InstrInfo.cpp:56
llvm::Thumb2InstrInfo::isLegalToSplitMBBAt
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Definition: Thumb2InstrInfo.cpp:113
llvm::findFirstVPTPredOperandIdx
int findFirstVPTPredOperandIdx(const MachineInstr &MI)
Definition: Thumb2InstrInfo.cpp:774
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::getVPTInstrPredicate
ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI, Register &PredReg)
Definition: Thumb2InstrInfo.cpp:787
ThumbRegisterInfo.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::Thumb2InstrInfo::ReplaceTailWithBranchTo
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const override
Definition: Thumb2InstrInfo.cpp:62
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
ARMBaseInstrInfo.h
llvm::Thumb2InstrInfo::Thumb2InstrInfo
Thumb2InstrInfo(const ARMSubtarget &STI)
Definition: Thumb2InstrInfo.cpp:48
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::Thumb2InstrInfo
Definition: Thumb2InstrInfo.h:22
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::recomputeVPTBlockMask
void recomputeVPTBlockMask(MachineInstr &Instr)
Definition: Thumb2InstrInfo.cpp:799
llvm::Thumb2InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: Thumb2InstrInfo.cpp:164
llvm::ARMVCC::VPTCodes
VPTCodes
Definition: ARMBaseInfo.h:89
llvm::Thumb2InstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
Definition: Thumb2InstrInfo.cpp:271
llvm::ThumbRegisterInfo
Definition: ThumbRegisterInfo.h:25
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::Thumb2InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: Thumb2InstrInfo.cpp:52
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::Thumb2InstrInfo::getRegisterInfo
const ThumbRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: Thumb2InstrInfo.h:60
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24