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17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
30 #define GET_INSTRINFO_HEADER
31 #include "MipsGenInstrInfo.inc"
38 class TargetRegisterClass;
39 class TargetRegisterInfo;
42 virtual void anchor();
66 bool AllowModify)
const override;
69 int *BytesRemoved =
nullptr)
const override;
74 int *BytesAdded =
nullptr)
const override;
90 int64_t BrOffset)
const override;
157 int64_t Offset)
const = 0;
164 int64_t Offset)
const = 0;
176 unsigned &SrcOpIdx2)
const override;
182 std::pair<unsigned, unsigned>
201 virtual unsigned getAnalyzableBrOpc(
unsigned Opc)
const = 0;
203 void AnalyzeCondBr(
const MachineInstr *Inst,
unsigned Opc,
217 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
static const MipsInstrInfo * create(MipsSubtarget &STI)
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
Insert an ISA appropriate nop.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
virtual void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
Predicate to determine if an instruction can go in a load delay slot.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
Reg
All possible values of the reg field in the ModR/M byte.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
A description of a memory reference used in the backend.
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned const TargetRegisterInfo * TRI
virtual bool isBranchWithImm(unsigned Opc) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
MachineOperand class - Representation of each machine instruction operand.
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isZeroImm(const MachineOperand &op) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Representation of each machine instruction.
bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
Flags
Flags values. These may be or'd together.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const =0
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
MachineBasicBlock MachineBasicBlock::iterator MBBI
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
Wrapper class representing virtual and physical registers.
bool HasLoadDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a load delay slot.
virtual const MipsRegisterInfo & getRegisterInfo() const =0
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool HasFPUDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
const MipsSubtarget & Subtarget