LLVM  14.0.0git
MipsInstrInfo.cpp
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1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstrInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42  Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
45  if (STI.inMips16Mode())
46  return createMips16InstrInfo(STI);
47 
48  return createMipsSEInstrInfo(STI);
49 }
50 
52  return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 // FIXME: This appears to be dead code.
58 void MipsInstrInfo::
60 {
61  DebugLoc DL;
62  BuildMI(MBB, MI, DL, get(Mips::NOP));
63 }
64 
67  MachineMemOperand::Flags Flags) const {
68  MachineFunction &MF = *MBB.getParent();
69  MachineFrameInfo &MFI = MF.getFrameInfo();
70 
72  Flags, MFI.getObjectSize(FI),
73  MFI.getObjectAlign(FI));
74 }
75 
76 //===----------------------------------------------------------------------===//
77 // Branch Analysis
78 //===----------------------------------------------------------------------===//
79 
80 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
83  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
84  int NumOp = Inst->getNumExplicitOperands();
85 
86  // for both int and fp branches, the last explicit operand is the
87  // MBB.
88  BB = Inst->getOperand(NumOp-1).getMBB();
89  Cond.push_back(MachineOperand::CreateImm(Opc));
90 
91  for (int i = 0; i < NumOp-1; i++)
92  Cond.push_back(Inst->getOperand(i));
93 }
94 
96  MachineBasicBlock *&TBB,
97  MachineBasicBlock *&FBB,
99  bool AllowModify) const {
100  SmallVector<MachineInstr*, 2> BranchInstrs;
101  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
102 
103  return (BT == BT_None) || (BT == BT_Indirect);
104 }
105 
106 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
107  const DebugLoc &DL,
109  unsigned Opc = Cond[0].getImm();
110  const MCInstrDesc &MCID = get(Opc);
111  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
112 
113  for (unsigned i = 1; i < Cond.size(); ++i) {
114  assert((Cond[i].isImm() || Cond[i].isReg()) &&
115  "Cannot copy operand for conditional branch!");
116  MIB.add(Cond[i]);
117  }
118  MIB.addMBB(TBB);
119 }
120 
122  MachineBasicBlock *TBB,
123  MachineBasicBlock *FBB,
125  const DebugLoc &DL,
126  int *BytesAdded) const {
127  // Shouldn't be a fall through.
128  assert(TBB && "insertBranch must not be told to insert a fallthrough");
129  assert(!BytesAdded && "code size not handled");
130 
131  // # of condition operands:
132  // Unconditional branches: 0
133  // Floating point branches: 1 (opc)
134  // Int BranchZero: 2 (opc, reg)
135  // Int Branch: 3 (opc, reg0, reg1)
136  assert((Cond.size() <= 3) &&
137  "# of Mips branch conditions must be <= 3!");
138 
139  // Two-way Conditional branch.
140  if (FBB) {
141  BuildCondBr(MBB, TBB, DL, Cond);
142  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
143  return 2;
144  }
145 
146  // One way branch.
147  // Unconditional branch.
148  if (Cond.empty())
149  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
150  else // Conditional branch.
151  BuildCondBr(MBB, TBB, DL, Cond);
152  return 1;
153 }
154 
156  int *BytesRemoved) const {
157  assert(!BytesRemoved && "code size not handled");
158 
160  unsigned removed = 0;
161 
162  // Up to 2 branches are removed.
163  // Note that indirect branches are not removed.
164  while (I != REnd && removed < 2) {
165  // Skip past debug instructions.
166  if (I->isDebugInstr()) {
167  ++I;
168  continue;
169  }
170  if (!getAnalyzableBrOpc(I->getOpcode()))
171  break;
172  // Remove the branch.
173  I->eraseFromParent();
174  I = MBB.rbegin();
175  ++removed;
176  }
177 
178  return removed;
179 }
180 
181 /// reverseBranchCondition - Return the inverse opcode of the
182 /// specified Branch instruction.
185  assert( (Cond.size() && Cond.size() <= 3) &&
186  "Invalid Mips branch condition!");
187  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
188  return false;
189 }
190 
193  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
194  SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
196 
197  // Skip all the debug instructions.
198  while (I != REnd && I->isDebugInstr())
199  ++I;
200 
201  if (I == REnd || !isUnpredicatedTerminator(*I)) {
202  // This block ends with no branches (it just falls through to its succ).
203  // Leave TBB/FBB null.
204  TBB = FBB = nullptr;
205  return BT_NoBranch;
206  }
207 
208  MachineInstr *LastInst = &*I;
209  unsigned LastOpc = LastInst->getOpcode();
210  BranchInstrs.push_back(LastInst);
211 
212  // Not an analyzable branch (e.g., indirect jump).
213  if (!getAnalyzableBrOpc(LastOpc))
214  return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
215 
216  // Get the second to last instruction in the block.
217  unsigned SecondLastOpc = 0;
218  MachineInstr *SecondLastInst = nullptr;
219 
220  // Skip past any debug instruction to see if the second last actual
221  // is a branch.
222  ++I;
223  while (I != REnd && I->isDebugInstr())
224  ++I;
225 
226  if (I != REnd) {
227  SecondLastInst = &*I;
228  SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
229 
230  // Not an analyzable branch (must be an indirect jump).
231  if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
232  return BT_None;
233  }
234 
235  // If there is only one terminator instruction, process it.
236  if (!SecondLastOpc) {
237  // Unconditional branch.
238  if (LastInst->isUnconditionalBranch()) {
239  TBB = LastInst->getOperand(0).getMBB();
240  return BT_Uncond;
241  }
242 
243  // Conditional branch
244  AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
245  return BT_Cond;
246  }
247 
248  // If we reached here, there are two branches.
249  // If there are three terminators, we don't know what sort of block this is.
250  if (++I != REnd && isUnpredicatedTerminator(*I))
251  return BT_None;
252 
253  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
254 
255  // If second to last instruction is an unconditional branch,
256  // analyze it and remove the last instruction.
257  if (SecondLastInst->isUnconditionalBranch()) {
258  // Return if the last instruction cannot be removed.
259  if (!AllowModify)
260  return BT_None;
261 
262  TBB = SecondLastInst->getOperand(0).getMBB();
263  LastInst->eraseFromParent();
264  BranchInstrs.pop_back();
265  return BT_Uncond;
266  }
267 
268  // Conditional branch followed by an unconditional branch.
269  // The last one must be unconditional.
270  if (!LastInst->isUnconditionalBranch())
271  return BT_None;
272 
273  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
274  FBB = LastInst->getOperand(0).getMBB();
275 
276  return BT_CondUncond;
277 }
278 
279 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
280  int64_t BrOffset) const {
281  switch (BranchOpc) {
282  case Mips::B:
283  case Mips::BAL:
284  case Mips::BAL_BR:
285  case Mips::BAL_BR_MM:
286  case Mips::BC1F:
287  case Mips::BC1FL:
288  case Mips::BC1T:
289  case Mips::BC1TL:
290  case Mips::BEQ: case Mips::BEQ64:
291  case Mips::BEQL:
292  case Mips::BGEZ: case Mips::BGEZ64:
293  case Mips::BGEZL:
294  case Mips::BGEZAL:
295  case Mips::BGEZALL:
296  case Mips::BGTZ: case Mips::BGTZ64:
297  case Mips::BGTZL:
298  case Mips::BLEZ: case Mips::BLEZ64:
299  case Mips::BLEZL:
300  case Mips::BLTZ: case Mips::BLTZ64:
301  case Mips::BLTZL:
302  case Mips::BLTZAL:
303  case Mips::BLTZALL:
304  case Mips::BNE: case Mips::BNE64:
305  case Mips::BNEL:
306  return isInt<18>(BrOffset);
307 
308  // microMIPSr3 branches
309  case Mips::B_MM:
310  case Mips::BC1F_MM:
311  case Mips::BC1T_MM:
312  case Mips::BEQ_MM:
313  case Mips::BGEZ_MM:
314  case Mips::BGEZAL_MM:
315  case Mips::BGTZ_MM:
316  case Mips::BLEZ_MM:
317  case Mips::BLTZ_MM:
318  case Mips::BLTZAL_MM:
319  case Mips::BNE_MM:
320  case Mips::BEQZC_MM:
321  case Mips::BNEZC_MM:
322  return isInt<17>(BrOffset);
323 
324  // microMIPSR3 short branches.
325  case Mips::B16_MM:
326  return isInt<11>(BrOffset);
327 
328  case Mips::BEQZ16_MM:
329  case Mips::BNEZ16_MM:
330  return isInt<8>(BrOffset);
331 
332  // MIPSR6 branches.
333  case Mips::BALC:
334  case Mips::BC:
335  return isInt<28>(BrOffset);
336 
337  case Mips::BC1EQZ:
338  case Mips::BC1NEZ:
339  case Mips::BC2EQZ:
340  case Mips::BC2NEZ:
341  case Mips::BEQC: case Mips::BEQC64:
342  case Mips::BNEC: case Mips::BNEC64:
343  case Mips::BGEC: case Mips::BGEC64:
344  case Mips::BGEUC: case Mips::BGEUC64:
345  case Mips::BGEZC: case Mips::BGEZC64:
346  case Mips::BGTZC: case Mips::BGTZC64:
347  case Mips::BLEZC: case Mips::BLEZC64:
348  case Mips::BLTC: case Mips::BLTC64:
349  case Mips::BLTUC: case Mips::BLTUC64:
350  case Mips::BLTZC: case Mips::BLTZC64:
351  case Mips::BNVC:
352  case Mips::BOVC:
353  case Mips::BGEZALC:
354  case Mips::BEQZALC:
355  case Mips::BGTZALC:
356  case Mips::BLEZALC:
357  case Mips::BLTZALC:
358  case Mips::BNEZALC:
359  return isInt<18>(BrOffset);
360 
361  case Mips::BEQZC: case Mips::BEQZC64:
362  case Mips::BNEZC: case Mips::BNEZC64:
363  return isInt<23>(BrOffset);
364 
365  // microMIPSR6 branches
366  case Mips::BC16_MMR6:
367  return isInt<11>(BrOffset);
368 
369  case Mips::BEQZC16_MMR6:
370  case Mips::BNEZC16_MMR6:
371  return isInt<8>(BrOffset);
372 
373  case Mips::BALC_MMR6:
374  case Mips::BC_MMR6:
375  return isInt<27>(BrOffset);
376 
377  case Mips::BC1EQZC_MMR6:
378  case Mips::BC1NEZC_MMR6:
379  case Mips::BC2EQZC_MMR6:
380  case Mips::BC2NEZC_MMR6:
381  case Mips::BGEZALC_MMR6:
382  case Mips::BEQZALC_MMR6:
383  case Mips::BGTZALC_MMR6:
384  case Mips::BLEZALC_MMR6:
385  case Mips::BLTZALC_MMR6:
386  case Mips::BNEZALC_MMR6:
387  case Mips::BNVC_MMR6:
388  case Mips::BOVC_MMR6:
389  return isInt<17>(BrOffset);
390 
391  case Mips::BEQC_MMR6:
392  case Mips::BNEC_MMR6:
393  case Mips::BGEC_MMR6:
394  case Mips::BGEUC_MMR6:
395  case Mips::BGEZC_MMR6:
396  case Mips::BGTZC_MMR6:
397  case Mips::BLEZC_MMR6:
398  case Mips::BLTC_MMR6:
399  case Mips::BLTUC_MMR6:
400  case Mips::BLTZC_MMR6:
401  return isInt<18>(BrOffset);
402 
403  case Mips::BEQZC_MMR6:
404  case Mips::BNEZC_MMR6:
405  return isInt<23>(BrOffset);
406 
407  // DSP branches.
408  case Mips::BPOSGE32:
409  return isInt<18>(BrOffset);
410  case Mips::BPOSGE32_MM:
411  case Mips::BPOSGE32C_MMR3:
412  return isInt<17>(BrOffset);
413 
414  // cnMIPS branches.
415  case Mips::BBIT0:
416  case Mips::BBIT032:
417  case Mips::BBIT1:
418  case Mips::BBIT132:
419  return isInt<18>(BrOffset);
420 
421  // MSA branches.
422  case Mips::BZ_B:
423  case Mips::BZ_H:
424  case Mips::BZ_W:
425  case Mips::BZ_D:
426  case Mips::BZ_V:
427  case Mips::BNZ_B:
428  case Mips::BNZ_H:
429  case Mips::BNZ_W:
430  case Mips::BNZ_D:
431  case Mips::BNZ_V:
432  return isInt<18>(BrOffset);
433  }
434 
435  llvm_unreachable("Unknown branch instruction!");
436 }
437 
438 /// Return the corresponding compact (no delay slot) form of a branch.
440  const MachineBasicBlock::iterator I) const {
441  unsigned Opcode = I->getOpcode();
442  bool canUseShortMicroMipsCTI = false;
443 
444  if (Subtarget.inMicroMipsMode()) {
445  switch (Opcode) {
446  case Mips::BNE:
447  case Mips::BNE_MM:
448  case Mips::BEQ:
449  case Mips::BEQ_MM:
450  // microMIPS has NE,EQ branches that do not have delay slots provided one
451  // of the operands is zero.
452  if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
453  canUseShortMicroMipsCTI = true;
454  break;
455  // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
456  // expanded to JR_MM, so they can be replaced with JRC16_MM.
457  case Mips::JR:
458  case Mips::PseudoReturn:
459  case Mips::PseudoIndirectBranch:
460  canUseShortMicroMipsCTI = true;
461  break;
462  }
463  }
464 
465  // MIPSR6 forbids both operands being the zero register.
466  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
467  (I->getOperand(0).isReg() &&
468  (I->getOperand(0).getReg() == Mips::ZERO ||
469  I->getOperand(0).getReg() == Mips::ZERO_64)) &&
470  (I->getOperand(1).isReg() &&
471  (I->getOperand(1).getReg() == Mips::ZERO ||
472  I->getOperand(1).getReg() == Mips::ZERO_64)))
473  return 0;
474 
475  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
476  switch (Opcode) {
477  case Mips::B:
478  return Mips::BC;
479  case Mips::BAL:
480  return Mips::BALC;
481  case Mips::BEQ:
482  case Mips::BEQ_MM:
483  if (canUseShortMicroMipsCTI)
484  return Mips::BEQZC_MM;
485  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
486  return 0;
487  return Mips::BEQC;
488  case Mips::BNE:
489  case Mips::BNE_MM:
490  if (canUseShortMicroMipsCTI)
491  return Mips::BNEZC_MM;
492  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
493  return 0;
494  return Mips::BNEC;
495  case Mips::BGE:
496  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
497  return 0;
498  return Mips::BGEC;
499  case Mips::BGEU:
500  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
501  return 0;
502  return Mips::BGEUC;
503  case Mips::BGEZ:
504  return Mips::BGEZC;
505  case Mips::BGTZ:
506  return Mips::BGTZC;
507  case Mips::BLEZ:
508  return Mips::BLEZC;
509  case Mips::BLT:
510  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
511  return 0;
512  return Mips::BLTC;
513  case Mips::BLTU:
514  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
515  return 0;
516  return Mips::BLTUC;
517  case Mips::BLTZ:
518  return Mips::BLTZC;
519  case Mips::BEQ64:
520  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
521  return 0;
522  return Mips::BEQC64;
523  case Mips::BNE64:
524  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
525  return 0;
526  return Mips::BNEC64;
527  case Mips::BGTZ64:
528  return Mips::BGTZC64;
529  case Mips::BGEZ64:
530  return Mips::BGEZC64;
531  case Mips::BLTZ64:
532  return Mips::BLTZC64;
533  case Mips::BLEZ64:
534  return Mips::BLEZC64;
535  // For MIPSR6, the instruction 'jic' can be used for these cases. Some
536  // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
537  case Mips::JR:
538  case Mips::PseudoIndirectBranchR6:
539  case Mips::PseudoReturn:
540  case Mips::TAILCALLR6REG:
541  if (canUseShortMicroMipsCTI)
542  return Mips::JRC16_MM;
543  return Mips::JIC;
544  case Mips::JALRPseudo:
545  return Mips::JIALC;
546  case Mips::JR64:
547  case Mips::PseudoIndirectBranch64R6:
548  case Mips::PseudoReturn64:
549  case Mips::TAILCALL64R6REG:
550  return Mips::JIC64;
551  case Mips::JALR64Pseudo:
552  return Mips::JIALC64;
553  default:
554  return 0;
555  }
556  }
557 
558  return 0;
559 }
560 
561 /// Predicate for distingushing between control transfer instructions and all
562 /// other instructions for handling forbidden slots. Consider inline assembly
563 /// as unsafe as well.
565  if (MI.isInlineAsm())
566  return false;
567 
568  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
569 }
570 
572  const MachineInstr &FPUMI) const {
573  if (MIInSlot.isInlineAsm())
574  return false;
575 
576  if (HasFPUDelaySlot(MIInSlot))
577  return false;
578 
579  switch (MIInSlot.getOpcode()) {
580  case Mips::BC1F:
581  case Mips::BC1FL:
582  case Mips::BC1T:
583  case Mips::BC1TL:
584  return false;
585  }
586 
587  for (const MachineOperand &Op : FPUMI.defs()) {
588  if (!Op.isReg())
589  continue;
590 
591  bool Reads, Writes;
592  std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg());
593 
594  if (Reads || Writes)
595  return false;
596  }
597 
598  return true;
599 }
600 
601 /// Predicate for distingushing instructions that have forbidden slots.
603  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
604 }
605 
606 /// Predicate for distingushing instructions that have FPU delay slots.
608  switch (MI.getOpcode()) {
609  case Mips::MTC1:
610  case Mips::MFC1:
611  case Mips::MTC1_D64:
612  case Mips::MFC1_D64:
613  case Mips::DMTC1:
614  case Mips::DMFC1:
615  case Mips::FCMP_S32:
616  case Mips::FCMP_D32:
617  case Mips::FCMP_D64:
618  return true;
619 
620  default:
621  return false;
622  }
623 }
624 
625 /// Return the number of bytes of code the specified instruction may be.
627  switch (MI.getOpcode()) {
628  default:
629  return MI.getDesc().getSize();
631  case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
632  const MachineFunction *MF = MI.getParent()->getParent();
633  const char *AsmStr = MI.getOperand(0).getSymbolName();
634  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
635  }
636  case Mips::CONSTPOOL_ENTRY:
637  // If this machine instr is a constant pool entry, its size is recorded as
638  // operand #2.
639  return MI.getOperand(2).getImm();
640  }
641 }
642 
647 
648  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
649  // Pick the zero form of the branch for readable assembly and for greater
650  // branch distance in non-microMIPS mode.
651  // Additional MIPSR6 does not permit the use of register $zero for compact
652  // branches.
653  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
654  // Mips::ZERO, which is incorrect. This test should be updated to use
655  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
656  // are fixed.
657  int ZeroOperandPosition = -1;
658  bool BranchWithZeroOperand = false;
659  if (I->isBranch() && !I->isPseudo()) {
660  auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
661  ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
662  BranchWithZeroOperand = ZeroOperandPosition != -1;
663  }
664 
665  if (BranchWithZeroOperand) {
666  switch (NewOpc) {
667  case Mips::BEQC:
668  NewOpc = Mips::BEQZC;
669  break;
670  case Mips::BNEC:
671  NewOpc = Mips::BNEZC;
672  break;
673  case Mips::BGEC:
674  NewOpc = Mips::BGEZC;
675  break;
676  case Mips::BLTC:
677  NewOpc = Mips::BLTZC;
678  break;
679  case Mips::BEQC64:
680  NewOpc = Mips::BEQZC64;
681  break;
682  case Mips::BNEC64:
683  NewOpc = Mips::BNEZC64;
684  break;
685  }
686  }
687 
688  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
689 
690  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
691  // immediate 0 as an operand and requires the removal of it's implicit-def %ra
692  // implicit operand as copying the implicit operations of the instructio we're
693  // looking at will give us the correct flags.
694  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
695  NewOpc == Mips::JIALC64) {
696 
697  if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
698  MIB->RemoveOperand(0);
699 
700  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
701  MIB.add(I->getOperand(J));
702  }
703 
704  MIB.addImm(0);
705 
706  // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
707  // add it to the new instruction.
708  for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
709  J < E; ++J) {
710  const MachineOperand &MO = I->getOperand(J);
711  if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
713  }
714 
715 
716  } else {
717  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
718  if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
719  continue;
720 
721  MIB.add(I->getOperand(J));
722  }
723  }
724 
725  MIB.copyImplicitOps(*I);
726  MIB.cloneMemRefs(*I);
727  return MIB;
728 }
729 
731  unsigned &SrcOpIdx1,
732  unsigned &SrcOpIdx2) const {
733  assert(!MI.isBundle() &&
734  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
735 
736  const MCInstrDesc &MCID = MI.getDesc();
737  if (!MCID.isCommutable())
738  return false;
739 
740  switch (MI.getOpcode()) {
741  case Mips::DPADD_U_H:
742  case Mips::DPADD_U_W:
743  case Mips::DPADD_U_D:
744  case Mips::DPADD_S_H:
745  case Mips::DPADD_S_W:
746  case Mips::DPADD_S_D:
747  // The first operand is both input and output, so it should not commute
748  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
749  return false;
750 
751  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
752  return false;
753  return true;
754  }
755  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
756 }
757 
758 // ins, ext, dext*, dins have the following constraints:
759 // X <= pos < Y
760 // X < size <= Y
761 // X < pos+size <= Y
762 //
763 // dinsm and dinsu have the following constraints:
764 // X <= pos < Y
765 // X <= size <= Y
766 // X < pos+size <= Y
767 //
768 // The callee of verifyInsExtInstruction however gives the bounds of
769 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
770 // function doesn't have to vary it's behaviour based on the instruction
771 // being checked.
772 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
773  const int64_t PosLow, const int64_t PosHigh,
774  const int64_t SizeLow,
775  const int64_t SizeHigh,
776  const int64_t BothLow,
777  const int64_t BothHigh) {
778  MachineOperand MOPos = MI.getOperand(2);
779  if (!MOPos.isImm()) {
780  ErrInfo = "Position is not an immediate!";
781  return false;
782  }
783  int64_t Pos = MOPos.getImm();
784  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
785  ErrInfo = "Position operand is out of range!";
786  return false;
787  }
788 
789  MachineOperand MOSize = MI.getOperand(3);
790  if (!MOSize.isImm()) {
791  ErrInfo = "Size operand is not an immediate!";
792  return false;
793  }
794  int64_t Size = MOSize.getImm();
795  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
796  ErrInfo = "Size operand is out of range!";
797  return false;
798  }
799 
800  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
801  ErrInfo = "Position + Size is out of range!";
802  return false;
803  }
804 
805  return true;
806 }
807 
808 // Perform target specific instruction verification.
810  StringRef &ErrInfo) const {
811  // Verify that ins and ext instructions are well formed.
812  switch (MI.getOpcode()) {
813  case Mips::EXT:
814  case Mips::EXT_MM:
815  case Mips::INS:
816  case Mips::INS_MM:
817  case Mips::DINS:
818  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
819  case Mips::DINSM:
820  // The ISA spec has a subtle difference between dinsm and dextm
821  // in that it says:
822  // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
823  // To make the bounds checks similar, the range 1 < size <= 64 is checked
824  // for 'dinsm'.
825  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
826  case Mips::DINSU:
827  // The ISA spec has a subtle difference between dinsu and dextu in that
828  // the size range of dinsu is specified as 1 <= size <= 32 whereas size
829  // for dextu is 0 < size <= 32. The range checked for dinsu here is
830  // 0 < size <= 32, which is equivalent and similar to dextu.
831  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
832  case Mips::DEXT:
833  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
834  case Mips::DEXTM:
835  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
836  case Mips::DEXTU:
837  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
838  case Mips::TAILCALLREG:
839  case Mips::PseudoIndirectBranch:
840  case Mips::JR:
841  case Mips::JR64:
842  case Mips::JALR:
843  case Mips::JALR64:
844  case Mips::JALRPseudo:
846  return true;
847 
848  ErrInfo = "invalid instruction when using jump guards!";
849  return false;
850  default:
851  return true;
852  }
853 
854  return true;
855 }
856 
857 std::pair<unsigned, unsigned>
859  return std::make_pair(TF, 0u);
860 }
861 
864  using namespace MipsII;
865 
866  static const std::pair<unsigned, const char*> Flags[] = {
867  {MO_GOT, "mips-got"},
868  {MO_GOT_CALL, "mips-got-call"},
869  {MO_GPREL, "mips-gprel"},
870  {MO_ABS_HI, "mips-abs-hi"},
871  {MO_ABS_LO, "mips-abs-lo"},
872  {MO_TLSGD, "mips-tlsgd"},
873  {MO_TLSLDM, "mips-tlsldm"},
874  {MO_DTPREL_HI, "mips-dtprel-hi"},
875  {MO_DTPREL_LO, "mips-dtprel-lo"},
876  {MO_GOTTPREL, "mips-gottprel"},
877  {MO_TPREL_HI, "mips-tprel-hi"},
878  {MO_TPREL_LO, "mips-tprel-lo"},
879  {MO_GPOFF_HI, "mips-gpoff-hi"},
880  {MO_GPOFF_LO, "mips-gpoff-lo"},
881  {MO_GOT_DISP, "mips-got-disp"},
882  {MO_GOT_PAGE, "mips-got-page"},
883  {MO_GOT_OFST, "mips-got-ofst"},
884  {MO_HIGHER, "mips-higher"},
885  {MO_HIGHEST, "mips-highest"},
886  {MO_GOT_HI16, "mips-got-hi16"},
887  {MO_GOT_LO16, "mips-got-lo16"},
888  {MO_CALL_HI16, "mips-call-hi16"},
889  {MO_CALL_LO16, "mips-call-lo16"},
890  {MO_JALR, "mips-jalr"}
891  };
892  return makeArrayRef(Flags);
893 }
894 
897  DIExpression *Expr =
898  DIExpression::get(MI.getMF()->getFunction().getContext(), {});
899 
900  // TODO: Special MIPS instructions that need to be described separately.
901  if (auto RegImm = isAddImmediate(MI, Reg)) {
902  Register SrcReg = RegImm->Reg;
903  int64_t Offset = RegImm->Imm;
904  // When SrcReg is $zero, treat loaded value as immediate only.
905  // Ex. $a2 = ADDiu $zero, 10
906  if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
907  return ParamLoadedValue(MI.getOperand(2), Expr);
908  }
910  return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
911  } else if (auto DestSrc = isCopyInstr(MI)) {
912  const MachineFunction *MF = MI.getMF();
914  Register DestReg = DestSrc->Destination->getReg();
915  // TODO: Handle cases where the Reg is sub- or super-register of the
916  // DestReg.
917  if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
918  return None;
919  }
920 
922 }
923 
925  Register Reg) const {
926  // TODO: Handle cases where Reg is a super- or sub-register of the
927  // destination register.
928  const MachineOperand &Op0 = MI.getOperand(0);
929  if (!Op0.isReg() || Reg != Op0.getReg())
930  return None;
931 
932  switch (MI.getOpcode()) {
933  case Mips::ADDiu:
934  case Mips::DADDiu: {
935  const MachineOperand &Dop = MI.getOperand(0);
936  const MachineOperand &Sop1 = MI.getOperand(1);
937  const MachineOperand &Sop2 = MI.getOperand(2);
938  // Value is sum of register and immediate. Immediate value could be
939  // global string address which is not supported.
940  if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
941  return RegImmPair{Sop1.getReg(), Sop2.getImm()};
942  // TODO: Handle case where Sop1 is a frame-index.
943  }
944  }
945  return None;
946 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1305
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::MipsInstrInfo::create
static const MipsInstrInfo * create(MipsSubtarget &STI)
Definition: MipsInstrInfo.cpp:44
MipsBaseInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:861
llvm::createMipsSEInstrInfo
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:913
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MipsII::MO_GOT_LO16
@ MO_GOT_LO16
Definition: MipsBaseInfo.h:90
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:709
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:306
op
#define op(i)
llvm::MipsII::IsCTI
@ IsCTI
IsCTI - Instruction is a Control Transfer Instruction.
Definition: MipsBaseInfo.h:124
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::MipsInstrInfo::BT_Indirect
@ BT_Indirect
Definition: MipsInstrInfo.h:55
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:435
llvm::MipsInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
Definition: MipsInstrInfo.cpp:95
llvm::MipsSubtarget::getABI
const MipsABIInfo & getABI() const
Definition: MipsSubtarget.cpp:279
llvm::MipsII::MO_JALR
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:95
MachineBasicBlock.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::MipsII::MO_DTPREL_HI
@ MO_DTPREL_HI
Definition: MipsBaseInfo.h:64
llvm::MipsII::MO_TPREL_HI
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
llvm::MipsInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: MipsInstrInfo.cpp:155
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:350
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MipsII::MO_CALL_HI16
@ MO_CALL_HI16
Definition: MipsBaseInfo.h:91
llvm::Optional
Definition: APInt.h:33
llvm::LanaiII::MO_ABS_LO
@ MO_ABS_LO
Definition: LanaiBaseInfo.h:36
llvm::MipsII::MO_GOTTPREL
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::MipsSubtarget::useIndirectJumpsHazard
bool useIndirectJumpsHazard() const
Definition: MipsSubtarget.h:326
llvm::createMips16InstrInfo
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
Definition: Mips16InstrInfo.cpp:468
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2596
llvm::MipsInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: MipsInstrInfo.cpp:730
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MipsII::MO_TLSGD
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1233
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:573
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:984
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:877
llvm::MipsII::MO_GOT_OFST
@ MO_GOT_OFST
Definition: MipsBaseInfo.h:81
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MipsInstrInfo::BT_CondUncond
@ BT_CondUncond
Definition: MipsInstrInfo.h:54
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::DIExpression::ApplyOffset
@ ApplyOffset
Definition: DebugInfoMetadata.h:2803
llvm::MipsSubtarget::inMips16Mode
bool inMips16Mode() const
Definition: MipsSubtarget.h:300
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
llvm::MipsII::MO_TLSLDM
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
llvm::MipsII::MO_GOT_HI16
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:89
llvm::MipsInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: MipsInstrInfo.cpp:121
llvm::BitTracker
Definition: BitTracker.h:35
TargetOpcodes.h
llvm::MipsInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
Definition: MipsInstrInfo.cpp:626
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MipsII::MO_HIGHEST
@ MO_HIGHEST
Definition: MipsBaseInfo.h:86
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MipsInstrInfo
Definition: MipsInstrInfo.h:41
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:472
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:282
llvm::MipsInstrInfo::getEquivalentCompactForm
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
Definition: MipsInstrInfo.cpp:439
DebugLoc.h
llvm::MipsInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: MipsInstrInfo.cpp:858
llvm::None
const NoneType None
Definition: None.h:23
llvm::MipsInstrInfo::isZeroImm
bool isZeroImm(const MachineOperand &op) const
Definition: MipsInstrInfo.cpp:51
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MipsInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
Definition: MipsInstrInfo.cpp:59
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MipsInstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:924
llvm::MipsII::MO_GOT_CALL
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
llvm::MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: MipsInstrInfo.cpp:863
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::MipsSubtarget::hasMips32r6
bool hasMips32r6() const
Definition: MipsSubtarget.h:268
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:453
llvm::MipsInstrInfo::SafeInFPUDelaySlot
bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
Definition: MipsInstrInfo.cpp:571
llvm::AArch64ISD::EXT
@ EXT
Definition: AArch64ISelLowering.h:187
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:467
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::MipsABIInfo::GetZeroReg
unsigned GetZeroReg() const
Definition: MipsABIInfo.cpp:93
llvm::MipsInstrInfo::genInstrWithNewOpc
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
Definition: MipsInstrInfo.cpp:644
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:131
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:995
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1174
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:229
removed
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
Definition: README.txt:1552
llvm::MipsII::MO_GOT_DISP
@ MO_GOT_DISP
Definition: MipsBaseInfo.h:79
MipsMCTargetDesc.h
llvm::MipsInstrInfo::MipsInstrInfo
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
Definition: MipsInstrInfo.cpp:40
llvm::MipsInstrInfo::BranchType
BranchType
Definition: MipsInstrInfo.h:49
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:77
llvm::MipsInstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:896
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MipsII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: MipsBaseInfo.h:74
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:208
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
llvm::MipsInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
Definition: MipsInstrInfo.cpp:279
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:276
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1255
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MipsInstrInfo::getOppositeBranchOpc
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
llvm::MipsInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
Definition: MipsInstrInfo.cpp:809
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsInstrInfo::HasForbiddenSlot
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
Definition: MipsInstrInfo.cpp:602
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MipsSubtarget::inMicroMipsMode
bool inMicroMipsMode() const
Definition: MipsSubtarget.h:311
llvm::MipsII::HasForbiddenSlot
@ HasForbiddenSlot
HasForbiddenSlot - Instruction has a forbidden slot.
Definition: MipsBaseInfo.h:126
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsII::MO_GPOFF_LO
@ MO_GPOFF_LO
Definition: MipsBaseInfo.h:78
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
verifyInsExtInstruction
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)
Definition: MipsInstrInfo.cpp:772
llvm::MipsInstrInfo::BT_None
@ BT_None
Definition: MipsInstrInfo.h:50
MachineFrameInfo.h
llvm::MipsISD::MTC1_D64
@ MTC1_D64
Definition: MipsISelLowering.h:106
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:987
llvm::MipsInstrInfo::SafeInForbiddenSlot
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
Definition: MipsInstrInfo.cpp:564
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MipsInstrInfo::GetMemOperand
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Definition: MipsInstrInfo.cpp:66
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::MipsInstrInfo::BT_NoBranch
@ BT_NoBranch
Definition: MipsInstrInfo.h:51
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::MipsInstrInfo::BT_Uncond
@ BT_Uncond
Definition: MipsInstrInfo.h:52
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:656
MipsInstrInfo.h
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::MipsII::MO_GPOFF_HI
@ MO_GPOFF_HI
Definition: MipsBaseInfo.h:77
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::MipsII::MO_DTPREL_LO
@ MO_DTPREL_LO
Definition: MipsBaseInfo.h:65
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
MachineInstrBuilder.h
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:296
llvm::MipsInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
Definition: MipsInstrInfo.cpp:183
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MipsInstrInfo::UncondBrOpc
unsigned UncondBrOpc
Definition: MipsInstrInfo.h:46
MipsSubtarget.h
llvm::MipsInstrInfo::BT_Cond
@ BT_Cond
Definition: MipsInstrInfo.h:53
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
MachineOperand.h
llvm::MipsInstrInfo::HasFPUDelaySlot
bool HasFPUDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
Definition: MipsInstrInfo.cpp:607
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MipsII::MO_CALL_LO16
@ MO_CALL_LO16
Definition: MipsBaseInfo.h:92
llvm::MipsII::MO_HIGHER
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
MachineFunction.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MipsII::MO_GOT_PAGE
@ MO_GOT_PAGE
Definition: MipsBaseInfo.h:80
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:716
llvm::HexagonII::MO_GPREL
@ MO_GPREL
Definition: HexagonBaseInfo.h:190
MipsGenInstrInfo
llvm::LanaiII::MO_ABS_HI
@ MO_ABS_HI
Definition: LanaiBaseInfo.h:35
llvm::MipsInstrInfo::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:782