LLVM  15.0.0git
MipsInstrInfo.cpp
Go to the documentation of this file.
1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstrInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/IR/DebugLoc.h"
28 #include "llvm/MC/MCInstrDesc.h"
30 #include <cassert>
31 
32 using namespace llvm;
33 
34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
36 
37 // Pin the vtable to this file.
38 void MipsInstrInfo::anchor() {}
39 
40 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
41  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
42  Subtarget(STI), UncondBrOpc(UncondBr) {}
43 
45  if (STI.inMips16Mode())
46  return createMips16InstrInfo(STI);
47 
48  return createMipsSEInstrInfo(STI);
49 }
50 
52  return op.isImm() && op.getImm() == 0;
53 }
54 
55 /// insertNoop - If data hazard condition is found insert the target nop
56 /// instruction.
57 void MipsInstrInfo::
59 {
60  DebugLoc DL;
61  BuildMI(MBB, MI, DL, get(Mips::NOP));
62 }
63 
66  DebugLoc DL) const {
68  "insertNop does not support MIPS16e mode at this time");
69  const unsigned MMOpc =
70  Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
71  const unsigned Opc = Subtarget.inMicroMipsMode() ? MMOpc : Mips::SLL;
72  return BuildMI(MBB, MI, DL, get(Opc), Mips::ZERO)
73  .addReg(Mips::ZERO)
74  .addImm(0);
75 }
76 
79  MachineMemOperand::Flags Flags) const {
80  MachineFunction &MF = *MBB.getParent();
81  MachineFrameInfo &MFI = MF.getFrameInfo();
82 
84  Flags, MFI.getObjectSize(FI),
85  MFI.getObjectAlign(FI));
86 }
87 
88 //===----------------------------------------------------------------------===//
89 // Branch Analysis
90 //===----------------------------------------------------------------------===//
91 
92 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
95  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
96  int NumOp = Inst->getNumExplicitOperands();
97 
98  // for both int and fp branches, the last explicit operand is the
99  // MBB.
100  BB = Inst->getOperand(NumOp-1).getMBB();
101  Cond.push_back(MachineOperand::CreateImm(Opc));
102 
103  for (int i = 0; i < NumOp-1; i++)
104  Cond.push_back(Inst->getOperand(i));
105 }
106 
108  MachineBasicBlock *&TBB,
109  MachineBasicBlock *&FBB,
111  bool AllowModify) const {
112  SmallVector<MachineInstr*, 2> BranchInstrs;
113  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
114 
115  return (BT == BT_None) || (BT == BT_Indirect);
116 }
117 
118 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
119  const DebugLoc &DL,
121  unsigned Opc = Cond[0].getImm();
122  const MCInstrDesc &MCID = get(Opc);
123  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
124 
125  for (unsigned i = 1; i < Cond.size(); ++i) {
126  assert((Cond[i].isImm() || Cond[i].isReg()) &&
127  "Cannot copy operand for conditional branch!");
128  MIB.add(Cond[i]);
129  }
130  MIB.addMBB(TBB);
131 }
132 
134  MachineBasicBlock *TBB,
135  MachineBasicBlock *FBB,
137  const DebugLoc &DL,
138  int *BytesAdded) const {
139  // Shouldn't be a fall through.
140  assert(TBB && "insertBranch must not be told to insert a fallthrough");
141  assert(!BytesAdded && "code size not handled");
142 
143  // # of condition operands:
144  // Unconditional branches: 0
145  // Floating point branches: 1 (opc)
146  // Int BranchZero: 2 (opc, reg)
147  // Int Branch: 3 (opc, reg0, reg1)
148  assert((Cond.size() <= 3) &&
149  "# of Mips branch conditions must be <= 3!");
150 
151  // Two-way Conditional branch.
152  if (FBB) {
153  BuildCondBr(MBB, TBB, DL, Cond);
154  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
155  return 2;
156  }
157 
158  // One way branch.
159  // Unconditional branch.
160  if (Cond.empty())
161  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
162  else // Conditional branch.
163  BuildCondBr(MBB, TBB, DL, Cond);
164  return 1;
165 }
166 
168  int *BytesRemoved) const {
169  assert(!BytesRemoved && "code size not handled");
170 
172  unsigned removed = 0;
173 
174  // Up to 2 branches are removed.
175  // Note that indirect branches are not removed.
176  while (I != REnd && removed < 2) {
177  // Skip past debug instructions.
178  if (I->isDebugInstr()) {
179  ++I;
180  continue;
181  }
182  if (!getAnalyzableBrOpc(I->getOpcode()))
183  break;
184  // Remove the branch.
185  I->eraseFromParent();
186  I = MBB.rbegin();
187  ++removed;
188  }
189 
190  return removed;
191 }
192 
193 /// reverseBranchCondition - Return the inverse opcode of the
194 /// specified Branch instruction.
197  assert( (Cond.size() && Cond.size() <= 3) &&
198  "Invalid Mips branch condition!");
199  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
200  return false;
201 }
202 
205  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
206  SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
208 
209  // Skip all the debug instructions.
210  while (I != REnd && I->isDebugInstr())
211  ++I;
212 
213  if (I == REnd || !isUnpredicatedTerminator(*I)) {
214  // This block ends with no branches (it just falls through to its succ).
215  // Leave TBB/FBB null.
216  TBB = FBB = nullptr;
217  return BT_NoBranch;
218  }
219 
220  MachineInstr *LastInst = &*I;
221  unsigned LastOpc = LastInst->getOpcode();
222  BranchInstrs.push_back(LastInst);
223 
224  // Not an analyzable branch (e.g., indirect jump).
225  if (!getAnalyzableBrOpc(LastOpc))
226  return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
227 
228  // Get the second to last instruction in the block.
229  unsigned SecondLastOpc = 0;
230  MachineInstr *SecondLastInst = nullptr;
231 
232  // Skip past any debug instruction to see if the second last actual
233  // is a branch.
234  ++I;
235  while (I != REnd && I->isDebugInstr())
236  ++I;
237 
238  if (I != REnd) {
239  SecondLastInst = &*I;
240  SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
241 
242  // Not an analyzable branch (must be an indirect jump).
243  if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
244  return BT_None;
245  }
246 
247  // If there is only one terminator instruction, process it.
248  if (!SecondLastOpc) {
249  // Unconditional branch.
250  if (LastInst->isUnconditionalBranch()) {
251  TBB = LastInst->getOperand(0).getMBB();
252  return BT_Uncond;
253  }
254 
255  // Conditional branch
256  AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
257  return BT_Cond;
258  }
259 
260  // If we reached here, there are two branches.
261  // If there are three terminators, we don't know what sort of block this is.
262  if (++I != REnd && isUnpredicatedTerminator(*I))
263  return BT_None;
264 
265  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
266 
267  // If second to last instruction is an unconditional branch,
268  // analyze it and remove the last instruction.
269  if (SecondLastInst->isUnconditionalBranch()) {
270  // Return if the last instruction cannot be removed.
271  if (!AllowModify)
272  return BT_None;
273 
274  TBB = SecondLastInst->getOperand(0).getMBB();
275  LastInst->eraseFromParent();
276  BranchInstrs.pop_back();
277  return BT_Uncond;
278  }
279 
280  // Conditional branch followed by an unconditional branch.
281  // The last one must be unconditional.
282  if (!LastInst->isUnconditionalBranch())
283  return BT_None;
284 
285  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
286  FBB = LastInst->getOperand(0).getMBB();
287 
288  return BT_CondUncond;
289 }
290 
291 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
292  int64_t BrOffset) const {
293  switch (BranchOpc) {
294  case Mips::B:
295  case Mips::BAL:
296  case Mips::BAL_BR:
297  case Mips::BAL_BR_MM:
298  case Mips::BC1F:
299  case Mips::BC1FL:
300  case Mips::BC1T:
301  case Mips::BC1TL:
302  case Mips::BEQ: case Mips::BEQ64:
303  case Mips::BEQL:
304  case Mips::BGEZ: case Mips::BGEZ64:
305  case Mips::BGEZL:
306  case Mips::BGEZAL:
307  case Mips::BGEZALL:
308  case Mips::BGTZ: case Mips::BGTZ64:
309  case Mips::BGTZL:
310  case Mips::BLEZ: case Mips::BLEZ64:
311  case Mips::BLEZL:
312  case Mips::BLTZ: case Mips::BLTZ64:
313  case Mips::BLTZL:
314  case Mips::BLTZAL:
315  case Mips::BLTZALL:
316  case Mips::BNE: case Mips::BNE64:
317  case Mips::BNEL:
318  return isInt<18>(BrOffset);
319 
320  // microMIPSr3 branches
321  case Mips::B_MM:
322  case Mips::BC1F_MM:
323  case Mips::BC1T_MM:
324  case Mips::BEQ_MM:
325  case Mips::BGEZ_MM:
326  case Mips::BGEZAL_MM:
327  case Mips::BGTZ_MM:
328  case Mips::BLEZ_MM:
329  case Mips::BLTZ_MM:
330  case Mips::BLTZAL_MM:
331  case Mips::BNE_MM:
332  case Mips::BEQZC_MM:
333  case Mips::BNEZC_MM:
334  return isInt<17>(BrOffset);
335 
336  // microMIPSR3 short branches.
337  case Mips::B16_MM:
338  return isInt<11>(BrOffset);
339 
340  case Mips::BEQZ16_MM:
341  case Mips::BNEZ16_MM:
342  return isInt<8>(BrOffset);
343 
344  // MIPSR6 branches.
345  case Mips::BALC:
346  case Mips::BC:
347  return isInt<28>(BrOffset);
348 
349  case Mips::BC1EQZ:
350  case Mips::BC1NEZ:
351  case Mips::BC2EQZ:
352  case Mips::BC2NEZ:
353  case Mips::BEQC: case Mips::BEQC64:
354  case Mips::BNEC: case Mips::BNEC64:
355  case Mips::BGEC: case Mips::BGEC64:
356  case Mips::BGEUC: case Mips::BGEUC64:
357  case Mips::BGEZC: case Mips::BGEZC64:
358  case Mips::BGTZC: case Mips::BGTZC64:
359  case Mips::BLEZC: case Mips::BLEZC64:
360  case Mips::BLTC: case Mips::BLTC64:
361  case Mips::BLTUC: case Mips::BLTUC64:
362  case Mips::BLTZC: case Mips::BLTZC64:
363  case Mips::BNVC:
364  case Mips::BOVC:
365  case Mips::BGEZALC:
366  case Mips::BEQZALC:
367  case Mips::BGTZALC:
368  case Mips::BLEZALC:
369  case Mips::BLTZALC:
370  case Mips::BNEZALC:
371  return isInt<18>(BrOffset);
372 
373  case Mips::BEQZC: case Mips::BEQZC64:
374  case Mips::BNEZC: case Mips::BNEZC64:
375  return isInt<23>(BrOffset);
376 
377  // microMIPSR6 branches
378  case Mips::BC16_MMR6:
379  return isInt<11>(BrOffset);
380 
381  case Mips::BEQZC16_MMR6:
382  case Mips::BNEZC16_MMR6:
383  return isInt<8>(BrOffset);
384 
385  case Mips::BALC_MMR6:
386  case Mips::BC_MMR6:
387  return isInt<27>(BrOffset);
388 
389  case Mips::BC1EQZC_MMR6:
390  case Mips::BC1NEZC_MMR6:
391  case Mips::BC2EQZC_MMR6:
392  case Mips::BC2NEZC_MMR6:
393  case Mips::BGEZALC_MMR6:
394  case Mips::BEQZALC_MMR6:
395  case Mips::BGTZALC_MMR6:
396  case Mips::BLEZALC_MMR6:
397  case Mips::BLTZALC_MMR6:
398  case Mips::BNEZALC_MMR6:
399  case Mips::BNVC_MMR6:
400  case Mips::BOVC_MMR6:
401  return isInt<17>(BrOffset);
402 
403  case Mips::BEQC_MMR6:
404  case Mips::BNEC_MMR6:
405  case Mips::BGEC_MMR6:
406  case Mips::BGEUC_MMR6:
407  case Mips::BGEZC_MMR6:
408  case Mips::BGTZC_MMR6:
409  case Mips::BLEZC_MMR6:
410  case Mips::BLTC_MMR6:
411  case Mips::BLTUC_MMR6:
412  case Mips::BLTZC_MMR6:
413  return isInt<18>(BrOffset);
414 
415  case Mips::BEQZC_MMR6:
416  case Mips::BNEZC_MMR6:
417  return isInt<23>(BrOffset);
418 
419  // DSP branches.
420  case Mips::BPOSGE32:
421  return isInt<18>(BrOffset);
422  case Mips::BPOSGE32_MM:
423  case Mips::BPOSGE32C_MMR3:
424  return isInt<17>(BrOffset);
425 
426  // cnMIPS branches.
427  case Mips::BBIT0:
428  case Mips::BBIT032:
429  case Mips::BBIT1:
430  case Mips::BBIT132:
431  return isInt<18>(BrOffset);
432 
433  // MSA branches.
434  case Mips::BZ_B:
435  case Mips::BZ_H:
436  case Mips::BZ_W:
437  case Mips::BZ_D:
438  case Mips::BZ_V:
439  case Mips::BNZ_B:
440  case Mips::BNZ_H:
441  case Mips::BNZ_W:
442  case Mips::BNZ_D:
443  case Mips::BNZ_V:
444  return isInt<18>(BrOffset);
445  }
446 
447  llvm_unreachable("Unknown branch instruction!");
448 }
449 
450 /// Return the corresponding compact (no delay slot) form of a branch.
452  const MachineBasicBlock::iterator I) const {
453  unsigned Opcode = I->getOpcode();
454  bool canUseShortMicroMipsCTI = false;
455 
456  if (Subtarget.inMicroMipsMode()) {
457  switch (Opcode) {
458  case Mips::BNE:
459  case Mips::BNE_MM:
460  case Mips::BEQ:
461  case Mips::BEQ_MM:
462  // microMIPS has NE,EQ branches that do not have delay slots provided one
463  // of the operands is zero.
464  if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
465  canUseShortMicroMipsCTI = true;
466  break;
467  // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
468  // expanded to JR_MM, so they can be replaced with JRC16_MM.
469  case Mips::JR:
470  case Mips::PseudoReturn:
471  case Mips::PseudoIndirectBranch:
472  canUseShortMicroMipsCTI = true;
473  break;
474  }
475  }
476 
477  // MIPSR6 forbids both operands being the zero register.
478  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
479  (I->getOperand(0).isReg() &&
480  (I->getOperand(0).getReg() == Mips::ZERO ||
481  I->getOperand(0).getReg() == Mips::ZERO_64)) &&
482  (I->getOperand(1).isReg() &&
483  (I->getOperand(1).getReg() == Mips::ZERO ||
484  I->getOperand(1).getReg() == Mips::ZERO_64)))
485  return 0;
486 
487  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
488  switch (Opcode) {
489  case Mips::B:
490  return Mips::BC;
491  case Mips::BAL:
492  return Mips::BALC;
493  case Mips::BEQ:
494  case Mips::BEQ_MM:
495  if (canUseShortMicroMipsCTI)
496  return Mips::BEQZC_MM;
497  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
498  return 0;
499  return Mips::BEQC;
500  case Mips::BNE:
501  case Mips::BNE_MM:
502  if (canUseShortMicroMipsCTI)
503  return Mips::BNEZC_MM;
504  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
505  return 0;
506  return Mips::BNEC;
507  case Mips::BGE:
508  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509  return 0;
510  return Mips::BGEC;
511  case Mips::BGEU:
512  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513  return 0;
514  return Mips::BGEUC;
515  case Mips::BGEZ:
516  return Mips::BGEZC;
517  case Mips::BGTZ:
518  return Mips::BGTZC;
519  case Mips::BLEZ:
520  return Mips::BLEZC;
521  case Mips::BLT:
522  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523  return 0;
524  return Mips::BLTC;
525  case Mips::BLTU:
526  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
527  return 0;
528  return Mips::BLTUC;
529  case Mips::BLTZ:
530  return Mips::BLTZC;
531  case Mips::BEQ64:
532  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
533  return 0;
534  return Mips::BEQC64;
535  case Mips::BNE64:
536  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
537  return 0;
538  return Mips::BNEC64;
539  case Mips::BGTZ64:
540  return Mips::BGTZC64;
541  case Mips::BGEZ64:
542  return Mips::BGEZC64;
543  case Mips::BLTZ64:
544  return Mips::BLTZC64;
545  case Mips::BLEZ64:
546  return Mips::BLEZC64;
547  // For MIPSR6, the instruction 'jic' can be used for these cases. Some
548  // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
549  case Mips::JR:
550  case Mips::PseudoIndirectBranchR6:
551  case Mips::PseudoReturn:
552  case Mips::TAILCALLR6REG:
553  if (canUseShortMicroMipsCTI)
554  return Mips::JRC16_MM;
555  return Mips::JIC;
556  case Mips::JALRPseudo:
557  return Mips::JIALC;
558  case Mips::JR64:
559  case Mips::PseudoIndirectBranch64R6:
560  case Mips::PseudoReturn64:
561  case Mips::TAILCALL64R6REG:
562  return Mips::JIC64;
563  case Mips::JALR64Pseudo:
564  return Mips::JIALC64;
565  default:
566  return 0;
567  }
568  }
569 
570  return 0;
571 }
572 
573 /// Predicate for distingushing between control transfer instructions and all
574 /// other instructions for handling forbidden slots. Consider inline assembly
575 /// as unsafe as well.
577  if (MI.isInlineAsm())
578  return false;
579 
580  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
581 }
582 
584  const MachineInstr &FPUMI) const {
585  if (MIInSlot.isInlineAsm())
586  return false;
587 
588  if (HasFPUDelaySlot(MIInSlot))
589  return false;
590 
591  switch (MIInSlot.getOpcode()) {
592  case Mips::BC1F:
593  case Mips::BC1FL:
594  case Mips::BC1T:
595  case Mips::BC1TL:
596  return false;
597  }
598 
599  for (const MachineOperand &Op : FPUMI.defs()) {
600  if (!Op.isReg())
601  continue;
602 
603  bool Reads, Writes;
604  std::tie(Reads, Writes) = MIInSlot.readsWritesVirtualRegister(Op.getReg());
605 
606  if (Reads || Writes)
607  return false;
608  }
609 
610  return true;
611 }
612 
613 /// Predicate for distinguishing instructions that are hazardous in a load delay
614 /// slot. Consider inline assembly as unsafe as well.
616  const MachineInstr &LoadMI) const {
617  if (MIInSlot.isInlineAsm())
618  return false;
619 
620  return !llvm::any_of(LoadMI.defs(), [&](const MachineOperand &Op) {
621  return Op.isReg() && MIInSlot.readsRegister(Op.getReg());
622  });
623 }
624 
625 /// Predicate for distingushing instructions that have forbidden slots.
627  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
628 }
629 
630 /// Predicate for distingushing instructions that have FPU delay slots.
632  switch (MI.getOpcode()) {
633  case Mips::MTC1:
634  case Mips::MFC1:
635  case Mips::MTC1_D64:
636  case Mips::MFC1_D64:
637  case Mips::DMTC1:
638  case Mips::DMFC1:
639  case Mips::FCMP_S32:
640  case Mips::FCMP_D32:
641  case Mips::FCMP_D64:
642  return true;
643 
644  default:
645  return false;
646  }
647 }
648 
649 /// Predicate for distingushing instructions that have load delay slots.
651  switch (MI.getOpcode()) {
652  case Mips::LB:
653  case Mips::LBu:
654  case Mips::LH:
655  case Mips::LHu:
656  case Mips::LW:
657  case Mips::LWR:
658  case Mips::LWL:
659  return true;
660  default:
661  return false;
662  }
663 }
664 
665 /// Return the number of bytes of code the specified instruction may be.
667  switch (MI.getOpcode()) {
668  default:
669  return MI.getDesc().getSize();
671  case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
672  const MachineFunction *MF = MI.getParent()->getParent();
673  const char *AsmStr = MI.getOperand(0).getSymbolName();
674  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
675  }
676  case Mips::CONSTPOOL_ENTRY:
677  // If this machine instr is a constant pool entry, its size is recorded as
678  // operand #2.
679  return MI.getOperand(2).getImm();
680  }
681 }
682 
687 
688  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
689  // Pick the zero form of the branch for readable assembly and for greater
690  // branch distance in non-microMIPS mode.
691  // Additional MIPSR6 does not permit the use of register $zero for compact
692  // branches.
693  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
694  // Mips::ZERO, which is incorrect. This test should be updated to use
695  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
696  // are fixed.
697  int ZeroOperandPosition = -1;
698  bool BranchWithZeroOperand = false;
699  if (I->isBranch() && !I->isPseudo()) {
700  auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
701  ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
702  BranchWithZeroOperand = ZeroOperandPosition != -1;
703  }
704 
705  if (BranchWithZeroOperand) {
706  switch (NewOpc) {
707  case Mips::BEQC:
708  NewOpc = Mips::BEQZC;
709  break;
710  case Mips::BNEC:
711  NewOpc = Mips::BNEZC;
712  break;
713  case Mips::BGEC:
714  NewOpc = Mips::BGEZC;
715  break;
716  case Mips::BLTC:
717  NewOpc = Mips::BLTZC;
718  break;
719  case Mips::BEQC64:
720  NewOpc = Mips::BEQZC64;
721  break;
722  case Mips::BNEC64:
723  NewOpc = Mips::BNEZC64;
724  break;
725  }
726  }
727 
728  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
729 
730  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
731  // immediate 0 as an operand and requires the removal of it's implicit-def %ra
732  // implicit operand as copying the implicit operations of the instructio we're
733  // looking at will give us the correct flags.
734  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
735  NewOpc == Mips::JIALC64) {
736 
737  if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
738  MIB->removeOperand(0);
739 
740  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
741  MIB.add(I->getOperand(J));
742  }
743 
744  MIB.addImm(0);
745 
746  // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
747  // add it to the new instruction.
748  for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
749  J < E; ++J) {
750  const MachineOperand &MO = I->getOperand(J);
751  if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
753  }
754 
755 
756  } else {
757  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
758  if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
759  continue;
760 
761  MIB.add(I->getOperand(J));
762  }
763  }
764 
765  MIB.copyImplicitOps(*I);
766  MIB.cloneMemRefs(*I);
767  return MIB;
768 }
769 
771  unsigned &SrcOpIdx1,
772  unsigned &SrcOpIdx2) const {
773  assert(!MI.isBundle() &&
774  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
775 
776  const MCInstrDesc &MCID = MI.getDesc();
777  if (!MCID.isCommutable())
778  return false;
779 
780  switch (MI.getOpcode()) {
781  case Mips::DPADD_U_H:
782  case Mips::DPADD_U_W:
783  case Mips::DPADD_U_D:
784  case Mips::DPADD_S_H:
785  case Mips::DPADD_S_W:
786  case Mips::DPADD_S_D:
787  // The first operand is both input and output, so it should not commute
788  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
789  return false;
790 
791  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
792  return false;
793  return true;
794  }
795  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
796 }
797 
798 // ins, ext, dext*, dins have the following constraints:
799 // X <= pos < Y
800 // X < size <= Y
801 // X < pos+size <= Y
802 //
803 // dinsm and dinsu have the following constraints:
804 // X <= pos < Y
805 // X <= size <= Y
806 // X < pos+size <= Y
807 //
808 // The callee of verifyInsExtInstruction however gives the bounds of
809 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
810 // function doesn't have to vary it's behaviour based on the instruction
811 // being checked.
812 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
813  const int64_t PosLow, const int64_t PosHigh,
814  const int64_t SizeLow,
815  const int64_t SizeHigh,
816  const int64_t BothLow,
817  const int64_t BothHigh) {
818  MachineOperand MOPos = MI.getOperand(2);
819  if (!MOPos.isImm()) {
820  ErrInfo = "Position is not an immediate!";
821  return false;
822  }
823  int64_t Pos = MOPos.getImm();
824  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
825  ErrInfo = "Position operand is out of range!";
826  return false;
827  }
828 
829  MachineOperand MOSize = MI.getOperand(3);
830  if (!MOSize.isImm()) {
831  ErrInfo = "Size operand is not an immediate!";
832  return false;
833  }
834  int64_t Size = MOSize.getImm();
835  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
836  ErrInfo = "Size operand is out of range!";
837  return false;
838  }
839 
840  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
841  ErrInfo = "Position + Size is out of range!";
842  return false;
843  }
844 
845  return true;
846 }
847 
848 // Perform target specific instruction verification.
850  StringRef &ErrInfo) const {
851  // Verify that ins and ext instructions are well formed.
852  switch (MI.getOpcode()) {
853  case Mips::EXT:
854  case Mips::EXT_MM:
855  case Mips::INS:
856  case Mips::INS_MM:
857  case Mips::DINS:
858  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
859  case Mips::DINSM:
860  // The ISA spec has a subtle difference between dinsm and dextm
861  // in that it says:
862  // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
863  // To make the bounds checks similar, the range 1 < size <= 64 is checked
864  // for 'dinsm'.
865  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
866  case Mips::DINSU:
867  // The ISA spec has a subtle difference between dinsu and dextu in that
868  // the size range of dinsu is specified as 1 <= size <= 32 whereas size
869  // for dextu is 0 < size <= 32. The range checked for dinsu here is
870  // 0 < size <= 32, which is equivalent and similar to dextu.
871  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
872  case Mips::DEXT:
873  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
874  case Mips::DEXTM:
875  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
876  case Mips::DEXTU:
877  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
878  case Mips::TAILCALLREG:
879  case Mips::PseudoIndirectBranch:
880  case Mips::JR:
881  case Mips::JR64:
882  case Mips::JALR:
883  case Mips::JALR64:
884  case Mips::JALRPseudo:
886  return true;
887 
888  ErrInfo = "invalid instruction when using jump guards!";
889  return false;
890  default:
891  return true;
892  }
893 
894  return true;
895 }
896 
897 std::pair<unsigned, unsigned>
899  return std::make_pair(TF, 0u);
900 }
901 
904  using namespace MipsII;
905 
906  static const std::pair<unsigned, const char*> Flags[] = {
907  {MO_GOT, "mips-got"},
908  {MO_GOT_CALL, "mips-got-call"},
909  {MO_GPREL, "mips-gprel"},
910  {MO_ABS_HI, "mips-abs-hi"},
911  {MO_ABS_LO, "mips-abs-lo"},
912  {MO_TLSGD, "mips-tlsgd"},
913  {MO_TLSLDM, "mips-tlsldm"},
914  {MO_DTPREL_HI, "mips-dtprel-hi"},
915  {MO_DTPREL_LO, "mips-dtprel-lo"},
916  {MO_GOTTPREL, "mips-gottprel"},
917  {MO_TPREL_HI, "mips-tprel-hi"},
918  {MO_TPREL_LO, "mips-tprel-lo"},
919  {MO_GPOFF_HI, "mips-gpoff-hi"},
920  {MO_GPOFF_LO, "mips-gpoff-lo"},
921  {MO_GOT_DISP, "mips-got-disp"},
922  {MO_GOT_PAGE, "mips-got-page"},
923  {MO_GOT_OFST, "mips-got-ofst"},
924  {MO_HIGHER, "mips-higher"},
925  {MO_HIGHEST, "mips-highest"},
926  {MO_GOT_HI16, "mips-got-hi16"},
927  {MO_GOT_LO16, "mips-got-lo16"},
928  {MO_CALL_HI16, "mips-call-hi16"},
929  {MO_CALL_LO16, "mips-call-lo16"},
930  {MO_JALR, "mips-jalr"}
931  };
932  return makeArrayRef(Flags);
933 }
934 
937  DIExpression *Expr =
938  DIExpression::get(MI.getMF()->getFunction().getContext(), {});
939 
940  // TODO: Special MIPS instructions that need to be described separately.
941  if (auto RegImm = isAddImmediate(MI, Reg)) {
942  Register SrcReg = RegImm->Reg;
943  int64_t Offset = RegImm->Imm;
944  // When SrcReg is $zero, treat loaded value as immediate only.
945  // Ex. $a2 = ADDiu $zero, 10
946  if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
947  return ParamLoadedValue(MI.getOperand(2), Expr);
948  }
949  Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset);
950  return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
951  } else if (auto DestSrc = isCopyInstr(MI)) {
952  const MachineFunction *MF = MI.getMF();
954  Register DestReg = DestSrc->Destination->getReg();
955  // TODO: Handle cases where the Reg is sub- or super-register of the
956  // DestReg.
957  if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))
958  return None;
959  }
960 
962 }
963 
965  Register Reg) const {
966  // TODO: Handle cases where Reg is a super- or sub-register of the
967  // destination register.
968  const MachineOperand &Op0 = MI.getOperand(0);
969  if (!Op0.isReg() || Reg != Op0.getReg())
970  return None;
971 
972  switch (MI.getOpcode()) {
973  case Mips::ADDiu:
974  case Mips::DADDiu: {
975  const MachineOperand &Dop = MI.getOperand(0);
976  const MachineOperand &Sop1 = MI.getOperand(1);
977  const MachineOperand &Sop2 = MI.getOperand(2);
978  // Value is sum of register and immediate. Immediate value could be
979  // global string address which is not supported.
980  if (Dop.isReg() && Sop1.isReg() && Sop2.isImm())
981  return RegImmPair{Sop1.getReg(), Sop2.getImm()};
982  // TODO: Handle case where Sop1 is a frame-index.
983  }
984  }
985  return None;
986 }
llvm::DIExpression::prepend
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
Definition: DebugInfoMetadata.cpp:1451
i
i
Definition: README.txt:29
llvm::MipsInstrInfo::create
static const MipsInstrInfo * create(MipsSubtarget &STI)
Definition: MipsInstrInfo.cpp:44
MipsBaseInfo.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
llvm::MipsInstrInfo::insertNop
MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
Insert an ISA appropriate nop.
Definition: MipsInstrInfo.cpp:64
llvm::MachineInstr::isIndirectBranch
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:868
llvm::createMipsSEInstrInfo
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
Definition: MipsSEInstrInfo.cpp:913
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:800
llvm::MipsII::MO_GOT_LO16
@ MO_GOT_LO16
Definition: MipsBaseInfo.h:90
DebugInfoMetadata.h
MCInstrDesc.h
llvm::MachineInstr::getNumExplicitOperands
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
Definition: MachineInstr.cpp:679
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
op
#define op(i)
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::MipsInstrInfo::BT_Indirect
@ BT_Indirect
Definition: MipsInstrInfo.h:55
llvm::MipsInstrInfo::SafeInLoadDelaySlot
bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
Predicate to determine if an instruction can go in a load delay slot.
Definition: MipsInstrInfo.cpp:615
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:454
llvm::MipsInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
Definition: MipsInstrInfo.cpp:107
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MipsSubtarget::getABI
const MipsABIInfo & getABI() const
Definition: MipsSubtarget.cpp:284
llvm::MipsII::MO_JALR
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:95
MachineBasicBlock.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineInstr::defs
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
Definition: MachineInstr.h:656
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MipsII::MO_DTPREL_HI
@ MO_DTPREL_HI
Definition: MipsBaseInfo.h:64
llvm::MipsII::MO_TPREL_HI
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:73
llvm::MipsInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: MipsInstrInfo.cpp:167
llvm::MachineOperand::isMCSymbol
bool isMCSymbol() const
Definition: MachineOperand.h:349
llvm::MipsII::IsCTI
@ IsCTI
IsCTI - Instruction is a Control Transfer Instruction.
Definition: MipsBaseInfo.h:124
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MipsII::MO_CALL_HI16
@ MO_CALL_HI16
Definition: MipsBaseInfo.h:91
llvm::Optional
Definition: APInt.h:33
llvm::LanaiII::MO_ABS_LO
@ MO_ABS_LO
Definition: LanaiBaseInfo.h:36
llvm::MipsII::MO_GOTTPREL
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:69
llvm::MipsSubtarget::useIndirectJumpsHazard
bool useIndirectJumpsHazard() const
Definition: MipsSubtarget.h:329
llvm::createMips16InstrInfo
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
Definition: Mips16InstrInfo.cpp:468
llvm::DIExpression
DWARF expression.
Definition: DebugInfoMetadata.h:2558
llvm::MipsISD::LWR
@ LWR
Definition: MipsISelLowering.h:249
llvm::MipsInstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Definition: MipsInstrInfo.cpp:770
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MipsII::MO_TLSGD
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:58
llvm::MDNode::get
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1384
llvm::MachineOperand::getMCSymbol
MCSymbol * getMCSymbol() const
Definition: MachineOperand.h:582
isImm
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
Definition: SPIRVInstructionSelector.cpp:982
llvm::ISD::INLINEASM
@ INLINEASM
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:1025
llvm::MachineInstr::isUnconditionalBranch
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
Definition: MachineInstr.h:884
llvm::MipsII::MO_GOT_OFST
@ MO_GOT_OFST
Definition: MipsBaseInfo.h:81
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MipsInstrInfo::BT_CondUncond
@ BT_CondUncond
Definition: MipsInstrInfo.h:54
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::DIExpression::ApplyOffset
@ ApplyOffset
Definition: DebugInfoMetadata.h:2763
llvm::MipsSubtarget::inMips16Mode
bool inMips16Mode() const
Definition: MipsSubtarget.h:303
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MipsII::MO_TLSLDM
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:63
llvm::MipsII::MO_GOT_HI16
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:89
llvm::MipsInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: MipsInstrInfo.cpp:133
llvm::BitTracker
Definition: BitTracker.h:35
TargetOpcodes.h
llvm::MipsInstrInfo::getInstSizeInBytes
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
Definition: MipsInstrInfo.cpp:666
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MipsII::MO_HIGHEST
@ MO_HIGHEST
Definition: MipsBaseInfo.h:86
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MipsInstrInfo
Definition: MipsInstrInfo.h:41
llvm::MCInstrDesc::isCommutable
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
Definition: MCInstrDesc.h:478
llvm::MipsISD::LWL
@ LWL
Definition: MipsISelLowering.h:248
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:288
llvm::MipsInstrInfo::getEquivalentCompactForm
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
Definition: MipsInstrInfo.cpp:451
DebugLoc.h
llvm::MipsInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: MipsInstrInfo.cpp:898
llvm::None
const NoneType None
Definition: None.h:24
llvm::MipsInstrInfo::isZeroImm
bool isZeroImm(const MachineOperand &op) const
Definition: MipsInstrInfo.cpp:51
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MipsInstrInfo::insertNoop
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
Definition: MipsInstrInfo.cpp:58
llvm::MachineInstrBuilder::cloneMemRefs
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Definition: MachineInstrBuilder.h:213
llvm::MipsInstrInfo::isAddImmediate
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:964
llvm::MipsII::MO_GOT_CALL
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:44
llvm::MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: MipsInstrInfo.cpp:903
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MipsII::HasForbiddenSlot
@ HasForbiddenSlot
HasForbiddenSlot - Instruction has a forbidden slot.
Definition: MipsBaseInfo.h:126
llvm::MipsSubtarget::hasMips32r6
bool hasMips32r6() const
Definition: MipsSubtarget.h:271
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:469
llvm::MipsInstrInfo::SafeInFPUDelaySlot
bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
Definition: MipsInstrInfo.cpp:583
llvm::AArch64ISD::EXT
@ EXT
Definition: AArch64ISelLowering.h:189
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::MachineFrameInfo::getObjectAlign
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
Definition: MachineFrameInfo.h:483
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::MipsABIInfo::GetZeroReg
unsigned GetZeroReg() const
Definition: MipsABIInfo.cpp:95
llvm::MipsInstrInfo::genInstrWithNewOpc
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
Definition: MipsInstrInfo.cpp:684
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstr::readsWritesVirtualRegister
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
Definition: MachineInstr.cpp:965
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1174
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
removed
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
Definition: README.txt:1552
llvm::MipsII::MO_GOT_DISP
@ MO_GOT_DISP
Definition: MipsBaseInfo.h:79
MipsMCTargetDesc.h
llvm::MipsInstrInfo::MipsInstrInfo
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
Definition: MipsInstrInfo.cpp:40
llvm::MipsInstrInfo::BranchType
BranchType
Definition: MipsInstrInfo.h:49
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:77
llvm::MipsInstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: MipsInstrInfo.cpp:936
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MipsII::MO_TPREL_LO
@ MO_TPREL_LO
Definition: MipsBaseInfo.h:74
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
llvm::MipsInstrInfo::isBranchOffsetInRange
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
Definition: MipsInstrInfo.cpp:291
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:282
llvm::MachineInstr::isInlineAsm
bool isInlineAsm() const
Definition: MachineInstr.h:1262
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:491
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MipsInstrInfo::getOppositeBranchOpc
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
llvm::MipsInstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
Definition: MipsInstrInfo.cpp:849
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MipsInstrInfo::HasForbiddenSlot
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
Definition: MipsInstrInfo.cpp:626
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MipsSubtarget::inMicroMipsMode
bool inMicroMipsMode() const
Definition: MipsSubtarget.h:314
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MipsII::MO_GPOFF_LO
@ MO_GPOFF_LO
Definition: MipsBaseInfo.h:78
llvm::MipsInstrInfo::HasLoadDelaySlot
bool HasLoadDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a load delay slot.
Definition: MipsInstrInfo.cpp:650
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
verifyInsExtInstruction
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)
Definition: MipsInstrInfo.cpp:812
llvm::MipsInstrInfo::BT_None
@ BT_None
Definition: MipsInstrInfo.h:50
MachineFrameInfo.h
llvm::MipsISD::MTC1_D64
@ MTC1_D64
Definition: MipsISelLowering.h:109
llvm::ISD::INLINEASM_BR
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:1028
llvm::MipsInstrInfo::SafeInForbiddenSlot
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
Definition: MipsInstrInfo.cpp:576
llvm::MCRegisterInfo::isSubRegister
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
Definition: MCRegisterInfo.h:560
llvm::MipsInstrInfo::GetMemOperand
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
Definition: MipsInstrInfo.cpp:78
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::MipsInstrInfo::BT_NoBranch
@ BT_NoBranch
Definition: MipsInstrInfo.h:51
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::MachineInstr::removeOperand
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:276
llvm::MipsInstrInfo::BT_Uncond
@ BT_Uncond
Definition: MipsInstrInfo.h:52
llvm::MCRegisterInfo::isSuperRegister
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Definition: MCRegisterInfo.h:659
MipsInstrInfo.h
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MipsII::MO_GPOFF_HI
@ MO_GPOFF_HI
Definition: MipsBaseInfo.h:77
llvm::MachineInstrBuilder::addSym
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:267
llvm::MipsII::MO_DTPREL_LO
@ MO_DTPREL_LO
Definition: MipsBaseInfo.h:65
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
MachineInstrBuilder.h
llvm::RISCVMatInt::RegImm
@ RegImm
Definition: RISCVMatInt.h:22
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:294
llvm::MipsInstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
Definition: MipsInstrInfo.cpp:195
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MipsInstrInfo::UncondBrOpc
unsigned UncondBrOpc
Definition: MipsInstrInfo.h:46
MipsSubtarget.h
llvm::MipsInstrInfo::BT_Cond
@ BT_Cond
Definition: MipsInstrInfo.h:53
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::MipsInstrInfo::HasFPUDelaySlot
bool HasFPUDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
Definition: MipsInstrInfo.cpp:631
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MipsII::MO_CALL_LO16
@ MO_CALL_LO16
Definition: MipsBaseInfo.h:92
llvm::MipsII::MO_HIGHER
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
Definition: MipsBaseInfo.h:85
MachineFunction.h
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:650
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MipsII::MO_GOT_PAGE
@ MO_GOT_PAGE
Definition: MipsBaseInfo.h:80
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:716
llvm::HexagonII::MO_GPREL
@ MO_GPREL
Definition: HexagonBaseInfo.h:190
MipsGenInstrInfo
llvm::LanaiII::MO_ABS_HI
@ MO_ABS_HI
Definition: LanaiBaseInfo.h:35
llvm::MipsInstrInfo::Subtarget
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45
llvm::SmallVectorImpl::insert
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:792