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34 #define GET_INSTRINFO_CTOR_DTOR
35 #include "MipsGenInstrInfo.inc"
38 void MipsInstrInfo::anchor() {}
42 Subtarget(STI), UncondBrOpc(UncondBr) {}
52 return op.isImm() &&
op.getImm() == 0;
68 "insertNop does not support MIPS16e mode at this time");
69 const unsigned MMOpc =
92 void MipsInstrInfo::AnalyzeCondBr(
const MachineInstr *Inst,
unsigned Opc,
95 assert(getAnalyzableBrOpc(Opc) &&
"Not an analyzable branch");
103 for (
int i = 0;
i < NumOp-1;
i++)
111 bool AllowModify)
const {
121 unsigned Opc =
Cond[0].getImm();
125 for (
unsigned i = 1;
i <
Cond.size(); ++
i) {
127 "Cannot copy operand for conditional branch!");
138 int *BytesAdded)
const {
140 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
141 assert(!BytesAdded &&
"code size not handled");
149 "# of Mips branch conditions must be <= 3!");
168 int *BytesRemoved)
const {
169 assert(!BytesRemoved &&
"code size not handled");
178 if (
I->isDebugInstr()) {
182 if (!getAnalyzableBrOpc(
I->getOpcode()))
185 I->eraseFromParent();
198 "Invalid Mips branch condition!");
210 while (
I != REnd &&
I->isDebugInstr())
213 if (
I == REnd || !isUnpredicatedTerminator(*
I)) {
221 unsigned LastOpc = LastInst->
getOpcode();
222 BranchInstrs.push_back(LastInst);
225 if (!getAnalyzableBrOpc(LastOpc))
229 unsigned SecondLastOpc = 0;
235 while (
I != REnd &&
I->isDebugInstr())
239 SecondLastInst = &*
I;
240 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->
getOpcode());
243 if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
248 if (!SecondLastOpc) {
256 AnalyzeCondBr(LastInst, LastOpc, TBB,
Cond);
262 if (++
I != REnd && isUnpredicatedTerminator(*
I))
265 BranchInstrs.
insert(BranchInstrs.begin(), SecondLastInst);
276 BranchInstrs.pop_back();
285 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB,
Cond);
292 int64_t BrOffset)
const {
297 case Mips::BAL_BR_MM:
302 case Mips::BEQ:
case Mips::BEQ64:
304 case Mips::BGEZ:
case Mips::BGEZ64:
308 case Mips::BGTZ:
case Mips::BGTZ64:
310 case Mips::BLEZ:
case Mips::BLEZ64:
312 case Mips::BLTZ:
case Mips::BLTZ64:
316 case Mips::BNE:
case Mips::BNE64:
318 return isInt<18>(BrOffset);
326 case Mips::BGEZAL_MM:
330 case Mips::BLTZAL_MM:
334 return isInt<17>(BrOffset);
338 return isInt<11>(BrOffset);
340 case Mips::BEQZ16_MM:
341 case Mips::BNEZ16_MM:
347 return isInt<28>(BrOffset);
353 case Mips::BEQC:
case Mips::BEQC64:
354 case Mips::BNEC:
case Mips::BNEC64:
355 case Mips::BGEC:
case Mips::BGEC64:
356 case Mips::BGEUC:
case Mips::BGEUC64:
357 case Mips::BGEZC:
case Mips::BGEZC64:
358 case Mips::BGTZC:
case Mips::BGTZC64:
359 case Mips::BLEZC:
case Mips::BLEZC64:
360 case Mips::BLTC:
case Mips::BLTC64:
361 case Mips::BLTUC:
case Mips::BLTUC64:
362 case Mips::BLTZC:
case Mips::BLTZC64:
371 return isInt<18>(BrOffset);
373 case Mips::BEQZC:
case Mips::BEQZC64:
374 case Mips::BNEZC:
case Mips::BNEZC64:
375 return isInt<23>(BrOffset);
378 case Mips::BC16_MMR6:
379 return isInt<11>(BrOffset);
381 case Mips::BEQZC16_MMR6:
382 case Mips::BNEZC16_MMR6:
385 case Mips::BALC_MMR6:
387 return isInt<27>(BrOffset);
389 case Mips::BC1EQZC_MMR6:
390 case Mips::BC1NEZC_MMR6:
391 case Mips::BC2EQZC_MMR6:
392 case Mips::BC2NEZC_MMR6:
393 case Mips::BGEZALC_MMR6:
394 case Mips::BEQZALC_MMR6:
395 case Mips::BGTZALC_MMR6:
396 case Mips::BLEZALC_MMR6:
397 case Mips::BLTZALC_MMR6:
398 case Mips::BNEZALC_MMR6:
399 case Mips::BNVC_MMR6:
400 case Mips::BOVC_MMR6:
401 return isInt<17>(BrOffset);
403 case Mips::BEQC_MMR6:
404 case Mips::BNEC_MMR6:
405 case Mips::BGEC_MMR6:
406 case Mips::BGEUC_MMR6:
407 case Mips::BGEZC_MMR6:
408 case Mips::BGTZC_MMR6:
409 case Mips::BLEZC_MMR6:
410 case Mips::BLTC_MMR6:
411 case Mips::BLTUC_MMR6:
412 case Mips::BLTZC_MMR6:
413 return isInt<18>(BrOffset);
415 case Mips::BEQZC_MMR6:
416 case Mips::BNEZC_MMR6:
417 return isInt<23>(BrOffset);
421 return isInt<18>(BrOffset);
422 case Mips::BPOSGE32_MM:
423 case Mips::BPOSGE32C_MMR3:
424 return isInt<17>(BrOffset);
431 return isInt<18>(BrOffset);
444 return isInt<18>(BrOffset);
453 unsigned Opcode =
I->getOpcode();
454 bool canUseShortMicroMipsCTI =
false;
465 canUseShortMicroMipsCTI =
true;
470 case Mips::PseudoReturn:
471 case Mips::PseudoIndirectBranch:
472 canUseShortMicroMipsCTI =
true;
479 (
I->getOperand(0).isReg() &&
480 (
I->getOperand(0).getReg() == Mips::ZERO ||
481 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
482 (
I->getOperand(1).isReg() &&
483 (
I->getOperand(1).getReg() == Mips::ZERO ||
484 I->getOperand(1).getReg() == Mips::ZERO_64)))
495 if (canUseShortMicroMipsCTI)
496 return Mips::BEQZC_MM;
497 else if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
502 if (canUseShortMicroMipsCTI)
503 return Mips::BNEZC_MM;
504 else if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
508 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
512 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
522 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
526 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
532 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
536 if (
I->getOperand(0).getReg() ==
I->getOperand(1).getReg())
540 return Mips::BGTZC64;
542 return Mips::BGEZC64;
544 return Mips::BLTZC64;
546 return Mips::BLEZC64;
550 case Mips::PseudoIndirectBranchR6:
551 case Mips::PseudoReturn:
552 case Mips::TAILCALLR6REG:
553 if (canUseShortMicroMipsCTI)
554 return Mips::JRC16_MM;
556 case Mips::JALRPseudo:
559 case Mips::PseudoIndirectBranch64R6:
560 case Mips::PseudoReturn64:
561 case Mips::TAILCALL64R6REG:
563 case Mips::JALR64Pseudo:
564 return Mips::JIALC64;
577 if (
MI.isInlineAsm())
621 return Op.isReg() && MIInSlot.readsRegister(Op.getReg());
632 switch (
MI.getOpcode()) {
651 switch (
MI.getOpcode()) {
667 switch (
MI.getOpcode()) {
669 return MI.getDesc().getSize();
673 const char *AsmStr =
MI.getOperand(0).getSymbolName();
676 case Mips::CONSTPOOL_ENTRY:
679 return MI.getOperand(2).getImm();
697 int ZeroOperandPosition = -1;
698 bool BranchWithZeroOperand =
false;
699 if (
I->isBranch() && !
I->isPseudo()) {
700 auto TRI =
I->getParent()->getParent()->getSubtarget().getRegisterInfo();
701 ZeroOperandPosition =
I->findRegisterUseOperandIdx(Mips::ZERO,
false,
TRI);
702 BranchWithZeroOperand = ZeroOperandPosition != -1;
705 if (BranchWithZeroOperand) {
708 NewOpc = Mips::BEQZC;
711 NewOpc = Mips::BNEZC;
714 NewOpc = Mips::BGEZC;
717 NewOpc = Mips::BLTZC;
720 NewOpc = Mips::BEQZC64;
723 NewOpc = Mips::BNEZC64;
728 MIB =
BuildMI(*
I->getParent(),
I,
I->getDebugLoc(),
get(NewOpc));
734 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
735 NewOpc == Mips::JIALC64) {
737 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
740 for (
unsigned J = 0,
E =
I->getDesc().getNumOperands(); J <
E; ++J) {
741 MIB.
add(
I->getOperand(J));
748 for (
unsigned J =
I->getDesc().getNumOperands(),
E =
I->getNumOperands();
757 for (
unsigned J = 0,
E =
I->getDesc().getNumOperands(); J <
E; ++J) {
758 if (BranchWithZeroOperand && (
unsigned)ZeroOperandPosition == J)
761 MIB.
add(
I->getOperand(J));
772 unsigned &SrcOpIdx2)
const {
774 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
780 switch (
MI.getOpcode()) {
781 case Mips::DPADD_U_H:
782 case Mips::DPADD_U_W:
783 case Mips::DPADD_U_D:
784 case Mips::DPADD_S_H:
785 case Mips::DPADD_S_W:
786 case Mips::DPADD_S_D:
788 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
791 if (!
MI.getOperand(SrcOpIdx1).isReg() || !
MI.getOperand(SrcOpIdx2).isReg())
813 const int64_t PosLow,
const int64_t PosHigh,
814 const int64_t SizeLow,
815 const int64_t SizeHigh,
816 const int64_t BothLow,
817 const int64_t BothHigh) {
819 if (!MOPos.
isImm()) {
820 ErrInfo =
"Position is not an immediate!";
823 int64_t Pos = MOPos.
getImm();
824 if (!((PosLow <= Pos) && (Pos < PosHigh))) {
825 ErrInfo =
"Position operand is out of range!";
830 if (!MOSize.
isImm()) {
831 ErrInfo =
"Size operand is not an immediate!";
834 int64_t Size = MOSize.
getImm();
835 if (!((SizeLow < Size) && (Size <= SizeHigh))) {
836 ErrInfo =
"Size operand is out of range!";
840 if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
841 ErrInfo =
"Position + Size is out of range!";
852 switch (
MI.getOpcode()) {
878 case Mips::TAILCALLREG:
879 case Mips::PseudoIndirectBranch:
884 case Mips::JALRPseudo:
888 ErrInfo =
"invalid instruction when using jump guards!";
897 std::pair<unsigned, unsigned>
899 return std::make_pair(TF, 0u);
904 using namespace MipsII;
906 static const std::pair<unsigned, const char*> Flags[] = {
943 int64_t Offset =
RegImm->Imm;
946 if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
951 }
else if (
auto DestSrc = isCopyInstr(
MI)) {
954 Register DestReg = DestSrc->Destination->getReg();
972 switch (
MI.getOpcode()) {
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
static const MipsInstrInfo * create(MipsSubtarget &STI)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
Insert an ISA appropriate nop.
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
const MachineInstrBuilder & add(const MachineOperand &MO) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
Predicate to determine if an instruction can go in a load delay slot.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
Reg
All possible values of the reg field in the ModR/M byte.
const MipsABIInfo & getABI() const
@ MO_JALR
Helper operand used to generate R_MIPS_JALR.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
iterator_range< mop_iterator > defs()
Returns a range over all explicit operands that are register definitions.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
@ MO_TPREL_HI
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
@ IsCTI
IsCTI - Instruction is a Control Transfer Instruction.
A description of a memory reference used in the backend.
@ MO_GOTTPREL
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
bool useIndirectJumpsHazard() const
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
unsigned const TargetRegisterInfo * TRI
@ MO_TLSGD
MO_TLSGD - Represents the offset into the global offset table at which.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
MCSymbol * getMCSymbol() const
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
@ INLINEASM
INLINEASM - Represents an inline asm block.
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
static MachineOperand CreateImm(int64_t Val)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
bool inMips16Mode() const
const MachineOperand & getOperand(unsigned i) const
@ MO_TLSLDM
MO_TLSLDM - Represents the offset into the global offset table at which.
@ MO_GOT_HI16
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
Describe properties that are true of each instruction in the target description file.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
bool isCommutable() const
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool isZeroImm(const MachineOperand &op) const
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override
@ MO_GOT_CALL
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
constexpr bool isInt< 8 >(int64_t x)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
@ HasForbiddenSlot
HasForbiddenSlot - Instruction has a forbidden slot.
unsigned getTargetFlags() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
unsigned GetZeroReg() const
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
Flags
Flags values. These may be or'd together.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
currently compiles eax eax je LBB0_3 testl eax jne LBB0_4 the testl could be removed
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
Used to describe a register and immediate addition.
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
static bool isReg(const MCInst &MI, unsigned OpNo)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineBasicBlock * getMBB() const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
reverse_iterator rbegin()
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
Wrapper class representing virtual and physical registers.
bool inMicroMipsMode() const
bool HasLoadDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a load delay slot.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Should compile to something r4 addze r3 instead we get
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool HasFPUDelaySlot(const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
@ MO_HIGHER
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
const MipsSubtarget & Subtarget
iterator insert(iterator I, T &&Elt)