LLVM  9.0.0svn
MipsInstrInfo.cpp
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1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Mips implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsInstrInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/IR/DebugLoc.h"
27 #include "llvm/MC/MCInstrDesc.h"
29 #include <cassert>
30 
31 using namespace llvm;
32 
33 #define GET_INSTRINFO_CTOR_DTOR
34 #include "MipsGenInstrInfo.inc"
35 
36 // Pin the vtable to this file.
37 void MipsInstrInfo::anchor() {}
38 
39 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
40  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
41  Subtarget(STI), UncondBrOpc(UncondBr) {}
42 
44  if (STI.inMips16Mode())
45  return createMips16InstrInfo(STI);
46 
47  return createMipsSEInstrInfo(STI);
48 }
49 
51  return op.isImm() && op.getImm() == 0;
52 }
53 
54 /// insertNoop - If data hazard condition is found insert the target nop
55 /// instruction.
56 // FIXME: This appears to be dead code.
57 void MipsInstrInfo::
59 {
60  DebugLoc DL;
61  BuildMI(MBB, MI, DL, get(Mips::NOP));
62 }
63 
66  MachineMemOperand::Flags Flags) const {
67  MachineFunction &MF = *MBB.getParent();
68  MachineFrameInfo &MFI = MF.getFrameInfo();
69  unsigned Align = MFI.getObjectAlignment(FI);
70 
72  Flags, MFI.getObjectSize(FI), Align);
73 }
74 
75 //===----------------------------------------------------------------------===//
76 // Branch Analysis
77 //===----------------------------------------------------------------------===//
78 
79 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
80  MachineBasicBlock *&BB,
81  SmallVectorImpl<MachineOperand> &Cond) const {
82  assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
83  int NumOp = Inst->getNumExplicitOperands();
84 
85  // for both int and fp branches, the last explicit operand is the
86  // MBB.
87  BB = Inst->getOperand(NumOp-1).getMBB();
89 
90  for (int i = 0; i < NumOp-1; i++)
91  Cond.push_back(Inst->getOperand(i));
92 }
93 
95  MachineBasicBlock *&TBB,
96  MachineBasicBlock *&FBB,
98  bool AllowModify) const {
99  SmallVector<MachineInstr*, 2> BranchInstrs;
100  BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
101 
102  return (BT == BT_None) || (BT == BT_Indirect);
103 }
104 
105 void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
106  const DebugLoc &DL,
107  ArrayRef<MachineOperand> Cond) const {
108  unsigned Opc = Cond[0].getImm();
109  const MCInstrDesc &MCID = get(Opc);
110  MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
111 
112  for (unsigned i = 1; i < Cond.size(); ++i) {
113  assert((Cond[i].isImm() || Cond[i].isReg()) &&
114  "Cannot copy operand for conditional branch!");
115  MIB.add(Cond[i]);
116  }
117  MIB.addMBB(TBB);
118 }
119 
121  MachineBasicBlock *TBB,
122  MachineBasicBlock *FBB,
124  const DebugLoc &DL,
125  int *BytesAdded) const {
126  // Shouldn't be a fall through.
127  assert(TBB && "insertBranch must not be told to insert a fallthrough");
128  assert(!BytesAdded && "code size not handled");
129 
130  // # of condition operands:
131  // Unconditional branches: 0
132  // Floating point branches: 1 (opc)
133  // Int BranchZero: 2 (opc, reg)
134  // Int Branch: 3 (opc, reg0, reg1)
135  assert((Cond.size() <= 3) &&
136  "# of Mips branch conditions must be <= 3!");
137 
138  // Two-way Conditional branch.
139  if (FBB) {
140  BuildCondBr(MBB, TBB, DL, Cond);
141  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
142  return 2;
143  }
144 
145  // One way branch.
146  // Unconditional branch.
147  if (Cond.empty())
148  BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
149  else // Conditional branch.
150  BuildCondBr(MBB, TBB, DL, Cond);
151  return 1;
152 }
153 
155  int *BytesRemoved) const {
156  assert(!BytesRemoved && "code size not handled");
157 
158  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
159  unsigned removed = 0;
160 
161  // Up to 2 branches are removed.
162  // Note that indirect branches are not removed.
163  while (I != REnd && removed < 2) {
164  // Skip past debug instructions.
165  if (I->isDebugInstr()) {
166  ++I;
167  continue;
168  }
169  if (!getAnalyzableBrOpc(I->getOpcode()))
170  break;
171  // Remove the branch.
172  I->eraseFromParent();
173  I = MBB.rbegin();
174  ++removed;
175  }
176 
177  return removed;
178 }
179 
180 /// reverseBranchCondition - Return the inverse opcode of the
181 /// specified Branch instruction.
183  SmallVectorImpl<MachineOperand> &Cond) const {
184  assert( (Cond.size() && Cond.size() <= 3) &&
185  "Invalid Mips branch condition!");
186  Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
187  return false;
188 }
189 
192  SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
193  SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
194  MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
195 
196  // Skip all the debug instructions.
197  while (I != REnd && I->isDebugInstr())
198  ++I;
199 
200  if (I == REnd || !isUnpredicatedTerminator(*I)) {
201  // This block ends with no branches (it just falls through to its succ).
202  // Leave TBB/FBB null.
203  TBB = FBB = nullptr;
204  return BT_NoBranch;
205  }
206 
207  MachineInstr *LastInst = &*I;
208  unsigned LastOpc = LastInst->getOpcode();
209  BranchInstrs.push_back(LastInst);
210 
211  // Not an analyzable branch (e.g., indirect jump).
212  if (!getAnalyzableBrOpc(LastOpc))
213  return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
214 
215  // Get the second to last instruction in the block.
216  unsigned SecondLastOpc = 0;
217  MachineInstr *SecondLastInst = nullptr;
218 
219  // Skip past any debug instruction to see if the second last actual
220  // is a branch.
221  ++I;
222  while (I != REnd && I->isDebugInstr())
223  ++I;
224 
225  if (I != REnd) {
226  SecondLastInst = &*I;
227  SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
228 
229  // Not an analyzable branch (must be an indirect jump).
230  if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)
231  return BT_None;
232  }
233 
234  // If there is only one terminator instruction, process it.
235  if (!SecondLastOpc) {
236  // Unconditional branch.
237  if (LastInst->isUnconditionalBranch()) {
238  TBB = LastInst->getOperand(0).getMBB();
239  return BT_Uncond;
240  }
241 
242  // Conditional branch
243  AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
244  return BT_Cond;
245  }
246 
247  // If we reached here, there are two branches.
248  // If there are three terminators, we don't know what sort of block this is.
249  if (++I != REnd && isUnpredicatedTerminator(*I))
250  return BT_None;
251 
252  BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
253 
254  // If second to last instruction is an unconditional branch,
255  // analyze it and remove the last instruction.
256  if (SecondLastInst->isUnconditionalBranch()) {
257  // Return if the last instruction cannot be removed.
258  if (!AllowModify)
259  return BT_None;
260 
261  TBB = SecondLastInst->getOperand(0).getMBB();
262  LastInst->eraseFromParent();
263  BranchInstrs.pop_back();
264  return BT_Uncond;
265  }
266 
267  // Conditional branch followed by an unconditional branch.
268  // The last one must be unconditional.
269  if (!LastInst->isUnconditionalBranch())
270  return BT_None;
271 
272  AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
273  FBB = LastInst->getOperand(0).getMBB();
274 
275  return BT_CondUncond;
276 }
277 
278 bool MipsInstrInfo::isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const {
279  switch (BranchOpc) {
280  case Mips::B:
281  case Mips::BAL:
282  case Mips::BAL_BR:
283  case Mips::BAL_BR_MM:
284  case Mips::BC1F:
285  case Mips::BC1FL:
286  case Mips::BC1T:
287  case Mips::BC1TL:
288  case Mips::BEQ: case Mips::BEQ64:
289  case Mips::BEQL:
290  case Mips::BGEZ: case Mips::BGEZ64:
291  case Mips::BGEZL:
292  case Mips::BGEZAL:
293  case Mips::BGEZALL:
294  case Mips::BGTZ: case Mips::BGTZ64:
295  case Mips::BGTZL:
296  case Mips::BLEZ: case Mips::BLEZ64:
297  case Mips::BLEZL:
298  case Mips::BLTZ: case Mips::BLTZ64:
299  case Mips::BLTZL:
300  case Mips::BLTZAL:
301  case Mips::BLTZALL:
302  case Mips::BNE: case Mips::BNE64:
303  case Mips::BNEL:
304  return isInt<18>(BrOffset);
305 
306  // microMIPSr3 branches
307  case Mips::B_MM:
308  case Mips::BC1F_MM:
309  case Mips::BC1T_MM:
310  case Mips::BEQ_MM:
311  case Mips::BGEZ_MM:
312  case Mips::BGEZAL_MM:
313  case Mips::BGTZ_MM:
314  case Mips::BLEZ_MM:
315  case Mips::BLTZ_MM:
316  case Mips::BLTZAL_MM:
317  case Mips::BNE_MM:
318  case Mips::BEQZC_MM:
319  case Mips::BNEZC_MM:
320  return isInt<17>(BrOffset);
321 
322  // microMIPSR3 short branches.
323  case Mips::B16_MM:
324  return isInt<11>(BrOffset);
325 
326  case Mips::BEQZ16_MM:
327  case Mips::BNEZ16_MM:
328  return isInt<8>(BrOffset);
329 
330  // MIPSR6 branches.
331  case Mips::BALC:
332  case Mips::BC:
333  return isInt<28>(BrOffset);
334 
335  case Mips::BC1EQZ:
336  case Mips::BC1NEZ:
337  case Mips::BC2EQZ:
338  case Mips::BC2NEZ:
339  case Mips::BEQC: case Mips::BEQC64:
340  case Mips::BNEC: case Mips::BNEC64:
341  case Mips::BGEC: case Mips::BGEC64:
342  case Mips::BGEUC: case Mips::BGEUC64:
343  case Mips::BGEZC: case Mips::BGEZC64:
344  case Mips::BGTZC: case Mips::BGTZC64:
345  case Mips::BLEZC: case Mips::BLEZC64:
346  case Mips::BLTC: case Mips::BLTC64:
347  case Mips::BLTUC: case Mips::BLTUC64:
348  case Mips::BLTZC: case Mips::BLTZC64:
349  case Mips::BNVC:
350  case Mips::BOVC:
351  case Mips::BGEZALC:
352  case Mips::BEQZALC:
353  case Mips::BGTZALC:
354  case Mips::BLEZALC:
355  case Mips::BLTZALC:
356  case Mips::BNEZALC:
357  return isInt<18>(BrOffset);
358 
359  case Mips::BEQZC: case Mips::BEQZC64:
360  case Mips::BNEZC: case Mips::BNEZC64:
361  return isInt<23>(BrOffset);
362 
363  // microMIPSR6 branches
364  case Mips::BC16_MMR6:
365  return isInt<11>(BrOffset);
366 
367  case Mips::BEQZC16_MMR6:
368  case Mips::BNEZC16_MMR6:
369  return isInt<8>(BrOffset);
370 
371  case Mips::BALC_MMR6:
372  case Mips::BC_MMR6:
373  return isInt<27>(BrOffset);
374 
375  case Mips::BC1EQZC_MMR6:
376  case Mips::BC1NEZC_MMR6:
377  case Mips::BC2EQZC_MMR6:
378  case Mips::BC2NEZC_MMR6:
379  case Mips::BGEZALC_MMR6:
380  case Mips::BEQZALC_MMR6:
381  case Mips::BGTZALC_MMR6:
382  case Mips::BLEZALC_MMR6:
383  case Mips::BLTZALC_MMR6:
384  case Mips::BNEZALC_MMR6:
385  case Mips::BNVC_MMR6:
386  case Mips::BOVC_MMR6:
387  return isInt<17>(BrOffset);
388 
389  case Mips::BEQC_MMR6:
390  case Mips::BNEC_MMR6:
391  case Mips::BGEC_MMR6:
392  case Mips::BGEUC_MMR6:
393  case Mips::BGEZC_MMR6:
394  case Mips::BGTZC_MMR6:
395  case Mips::BLEZC_MMR6:
396  case Mips::BLTC_MMR6:
397  case Mips::BLTUC_MMR6:
398  case Mips::BLTZC_MMR6:
399  return isInt<18>(BrOffset);
400 
401  case Mips::BEQZC_MMR6:
402  case Mips::BNEZC_MMR6:
403  return isInt<23>(BrOffset);
404 
405  // DSP branches.
406  case Mips::BPOSGE32:
407  return isInt<18>(BrOffset);
408  case Mips::BPOSGE32_MM:
409  case Mips::BPOSGE32C_MMR3:
410  return isInt<17>(BrOffset);
411 
412  // cnMIPS branches.
413  case Mips::BBIT0:
414  case Mips::BBIT032:
415  case Mips::BBIT1:
416  case Mips::BBIT132:
417  return isInt<18>(BrOffset);
418 
419  // MSA branches.
420  case Mips::BZ_B:
421  case Mips::BZ_H:
422  case Mips::BZ_W:
423  case Mips::BZ_D:
424  case Mips::BZ_V:
425  case Mips::BNZ_B:
426  case Mips::BNZ_H:
427  case Mips::BNZ_W:
428  case Mips::BNZ_D:
429  case Mips::BNZ_V:
430  return isInt<18>(BrOffset);
431  }
432 
433  llvm_unreachable("Unknown branch instruction!");
434 }
435 
436 
437 /// Return the corresponding compact (no delay slot) form of a branch.
439  const MachineBasicBlock::iterator I) const {
440  unsigned Opcode = I->getOpcode();
441  bool canUseShortMicroMipsCTI = false;
442 
443  if (Subtarget.inMicroMipsMode()) {
444  switch (Opcode) {
445  case Mips::BNE:
446  case Mips::BNE_MM:
447  case Mips::BEQ:
448  case Mips::BEQ_MM:
449  // microMIPS has NE,EQ branches that do not have delay slots provided one
450  // of the operands is zero.
451  if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
452  canUseShortMicroMipsCTI = true;
453  break;
454  // For microMIPS the PseudoReturn and PseudoIndirectBranch are always
455  // expanded to JR_MM, so they can be replaced with JRC16_MM.
456  case Mips::JR:
457  case Mips::PseudoReturn:
458  case Mips::PseudoIndirectBranch:
459  canUseShortMicroMipsCTI = true;
460  break;
461  }
462  }
463 
464  // MIPSR6 forbids both operands being the zero register.
465  if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
466  (I->getOperand(0).isReg() &&
467  (I->getOperand(0).getReg() == Mips::ZERO ||
468  I->getOperand(0).getReg() == Mips::ZERO_64)) &&
469  (I->getOperand(1).isReg() &&
470  (I->getOperand(1).getReg() == Mips::ZERO ||
471  I->getOperand(1).getReg() == Mips::ZERO_64)))
472  return 0;
473 
474  if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
475  switch (Opcode) {
476  case Mips::B:
477  return Mips::BC;
478  case Mips::BAL:
479  return Mips::BALC;
480  case Mips::BEQ:
481  case Mips::BEQ_MM:
482  if (canUseShortMicroMipsCTI)
483  return Mips::BEQZC_MM;
484  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
485  return 0;
486  return Mips::BEQC;
487  case Mips::BNE:
488  case Mips::BNE_MM:
489  if (canUseShortMicroMipsCTI)
490  return Mips::BNEZC_MM;
491  else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
492  return 0;
493  return Mips::BNEC;
494  case Mips::BGE:
495  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
496  return 0;
497  return Mips::BGEC;
498  case Mips::BGEU:
499  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
500  return 0;
501  return Mips::BGEUC;
502  case Mips::BGEZ:
503  return Mips::BGEZC;
504  case Mips::BGTZ:
505  return Mips::BGTZC;
506  case Mips::BLEZ:
507  return Mips::BLEZC;
508  case Mips::BLT:
509  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
510  return 0;
511  return Mips::BLTC;
512  case Mips::BLTU:
513  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
514  return 0;
515  return Mips::BLTUC;
516  case Mips::BLTZ:
517  return Mips::BLTZC;
518  case Mips::BEQ64:
519  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
520  return 0;
521  return Mips::BEQC64;
522  case Mips::BNE64:
523  if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
524  return 0;
525  return Mips::BNEC64;
526  case Mips::BGTZ64:
527  return Mips::BGTZC64;
528  case Mips::BGEZ64:
529  return Mips::BGEZC64;
530  case Mips::BLTZ64:
531  return Mips::BLTZC64;
532  case Mips::BLEZ64:
533  return Mips::BLEZC64;
534  // For MIPSR6, the instruction 'jic' can be used for these cases. Some
535  // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
536  case Mips::JR:
537  case Mips::PseudoIndirectBranchR6:
538  case Mips::PseudoReturn:
539  case Mips::TAILCALLR6REG:
540  if (canUseShortMicroMipsCTI)
541  return Mips::JRC16_MM;
542  return Mips::JIC;
543  case Mips::JALRPseudo:
544  return Mips::JIALC;
545  case Mips::JR64:
546  case Mips::PseudoIndirectBranch64R6:
547  case Mips::PseudoReturn64:
548  case Mips::TAILCALL64R6REG:
549  return Mips::JIC64;
550  case Mips::JALR64Pseudo:
551  return Mips::JIALC64;
552  default:
553  return 0;
554  }
555  }
556 
557  return 0;
558 }
559 
560 /// Predicate for distingushing between control transfer instructions and all
561 /// other instructions for handling forbidden slots. Consider inline assembly
562 /// as unsafe as well.
564  if (MI.isInlineAsm())
565  return false;
566 
567  return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
568 }
569 
570 /// Predicate for distingushing instructions that have forbidden slots.
572  return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
573 }
574 
575 /// Return the number of bytes of code the specified instruction may be.
577  switch (MI.getOpcode()) {
578  default:
579  return MI.getDesc().getSize();
581  case TargetOpcode::INLINEASM_BR: { // Inline Asm: Variable size.
582  const MachineFunction *MF = MI.getParent()->getParent();
583  const char *AsmStr = MI.getOperand(0).getSymbolName();
584  return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
585  }
586  case Mips::CONSTPOOL_ENTRY:
587  // If this machine instr is a constant pool entry, its size is recorded as
588  // operand #2.
589  return MI.getOperand(2).getImm();
590  }
591 }
592 
597 
598  // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest
599  // Pick the zero form of the branch for readable assembly and for greater
600  // branch distance in non-microMIPS mode.
601  // Additional MIPSR6 does not permit the use of register $zero for compact
602  // branches.
603  // FIXME: Certain atomic sequences on mips64 generate 32bit references to
604  // Mips::ZERO, which is incorrect. This test should be updated to use
605  // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
606  // are fixed.
607  int ZeroOperandPosition = -1;
608  bool BranchWithZeroOperand = false;
609  if (I->isBranch() && !I->isPseudo()) {
610  auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
611  ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
612  BranchWithZeroOperand = ZeroOperandPosition != -1;
613  }
614 
615  if (BranchWithZeroOperand) {
616  switch (NewOpc) {
617  case Mips::BEQC:
618  NewOpc = Mips::BEQZC;
619  break;
620  case Mips::BNEC:
621  NewOpc = Mips::BNEZC;
622  break;
623  case Mips::BGEC:
624  NewOpc = Mips::BGEZC;
625  break;
626  case Mips::BLTC:
627  NewOpc = Mips::BLTZC;
628  break;
629  case Mips::BEQC64:
630  NewOpc = Mips::BEQZC64;
631  break;
632  case Mips::BNEC64:
633  NewOpc = Mips::BNEZC64;
634  break;
635  }
636  }
637 
638  MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
639 
640  // For MIPSR6 JI*C requires an immediate 0 as an operand, JIALC(64) an
641  // immediate 0 as an operand and requires the removal of it's implicit-def %ra
642  // implicit operand as copying the implicit operations of the instructio we're
643  // looking at will give us the correct flags.
644  if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
645  NewOpc == Mips::JIALC64) {
646 
647  if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
648  MIB->RemoveOperand(0);
649 
650  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
651  MIB.add(I->getOperand(J));
652  }
653 
654  MIB.addImm(0);
655 
656  // If I has an MCSymbol operand (used by asm printer, to emit R_MIPS_JALR),
657  // add it to the new instruction.
658  for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
659  J < E; ++J) {
660  const MachineOperand &MO = I->getOperand(J);
661  if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR))
663  }
664 
665 
666  } else {
667  for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
668  if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)
669  continue;
670 
671  MIB.add(I->getOperand(J));
672  }
673  }
674 
675  MIB.copyImplicitOps(*I);
676  MIB.cloneMemRefs(*I);
677  return MIB;
678 }
679 
681  unsigned &SrcOpIdx2) const {
682  assert(!MI.isBundle() &&
683  "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
684 
685  const MCInstrDesc &MCID = MI.getDesc();
686  if (!MCID.isCommutable())
687  return false;
688 
689  switch (MI.getOpcode()) {
690  case Mips::DPADD_U_H:
691  case Mips::DPADD_U_W:
692  case Mips::DPADD_U_D:
693  case Mips::DPADD_S_H:
694  case Mips::DPADD_S_W:
695  case Mips::DPADD_S_D:
696  // The first operand is both input and output, so it should not commute
697  if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))
698  return false;
699 
700  if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
701  return false;
702  return true;
703  }
704  return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
705 }
706 
707 // ins, ext, dext*, dins have the following constraints:
708 // X <= pos < Y
709 // X < size <= Y
710 // X < pos+size <= Y
711 //
712 // dinsm and dinsu have the following constraints:
713 // X <= pos < Y
714 // X <= size <= Y
715 // X < pos+size <= Y
716 //
717 // The callee of verifyInsExtInstruction however gives the bounds of
718 // dins[um] like the other (d)ins (d)ext(um) instructions, so that this
719 // function doesn't have to vary it's behaviour based on the instruction
720 // being checked.
721 static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo,
722  const int64_t PosLow, const int64_t PosHigh,
723  const int64_t SizeLow,
724  const int64_t SizeHigh,
725  const int64_t BothLow,
726  const int64_t BothHigh) {
727  MachineOperand MOPos = MI.getOperand(2);
728  if (!MOPos.isImm()) {
729  ErrInfo = "Position is not an immediate!";
730  return false;
731  }
732  int64_t Pos = MOPos.getImm();
733  if (!((PosLow <= Pos) && (Pos < PosHigh))) {
734  ErrInfo = "Position operand is out of range!";
735  return false;
736  }
737 
738  MachineOperand MOSize = MI.getOperand(3);
739  if (!MOSize.isImm()) {
740  ErrInfo = "Size operand is not an immediate!";
741  return false;
742  }
743  int64_t Size = MOSize.getImm();
744  if (!((SizeLow < Size) && (Size <= SizeHigh))) {
745  ErrInfo = "Size operand is out of range!";
746  return false;
747  }
748 
749  if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {
750  ErrInfo = "Position + Size is out of range!";
751  return false;
752  }
753 
754  return true;
755 }
756 
757 // Perform target specific instruction verification.
759  StringRef &ErrInfo) const {
760  // Verify that ins and ext instructions are well formed.
761  switch (MI.getOpcode()) {
762  case Mips::EXT:
763  case Mips::EXT_MM:
764  case Mips::INS:
765  case Mips::INS_MM:
766  case Mips::DINS:
767  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32);
768  case Mips::DINSM:
769  // The ISA spec has a subtle difference between dinsm and dextm
770  // in that it says:
771  // 2 <= size <= 64 for 'dinsm' but 'dextm' has 32 < size <= 64.
772  // To make the bounds checks similar, the range 1 < size <= 64 is checked
773  // for 'dinsm'.
774  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64);
775  case Mips::DINSU:
776  // The ISA spec has a subtle difference between dinsu and dextu in that
777  // the size range of dinsu is specified as 1 <= size <= 32 whereas size
778  // for dextu is 0 < size <= 32. The range checked for dinsu here is
779  // 0 < size <= 32, which is equivalent and similar to dextu.
780  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
781  case Mips::DEXT:
782  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63);
783  case Mips::DEXTM:
784  return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
785  case Mips::DEXTU:
786  return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
787  case Mips::TAILCALLREG:
788  case Mips::PseudoIndirectBranch:
789  case Mips::JR:
790  case Mips::JR64:
791  case Mips::JALR:
792  case Mips::JALR64:
793  case Mips::JALRPseudo:
795  return true;
796 
797  ErrInfo = "invalid instruction when using jump guards!";
798  return false;
799  default:
800  return true;
801  }
802 
803  return true;
804 }
805 
806 std::pair<unsigned, unsigned>
808  return std::make_pair(TF, 0u);
809 }
810 
813  using namespace MipsII;
814 
815  static const std::pair<unsigned, const char*> Flags[] = {
816  {MO_GOT, "mips-got"},
817  {MO_GOT_CALL, "mips-got-call"},
818  {MO_GPREL, "mips-gprel"},
819  {MO_ABS_HI, "mips-abs-hi"},
820  {MO_ABS_LO, "mips-abs-lo"},
821  {MO_TLSGD, "mips-tlsgd"},
822  {MO_TLSLDM, "mips-tlsldm"},
823  {MO_DTPREL_HI, "mips-dtprel-hi"},
824  {MO_DTPREL_LO, "mips-dtprel-lo"},
825  {MO_GOTTPREL, "mips-gottprel"},
826  {MO_TPREL_HI, "mips-tprel-hi"},
827  {MO_TPREL_LO, "mips-tprel-lo"},
828  {MO_GPOFF_HI, "mips-gpoff-hi"},
829  {MO_GPOFF_LO, "mips-gpoff-lo"},
830  {MO_GOT_DISP, "mips-got-disp"},
831  {MO_GOT_PAGE, "mips-got-page"},
832  {MO_GOT_OFST, "mips-got-ofst"},
833  {MO_HIGHER, "mips-higher"},
834  {MO_HIGHEST, "mips-highest"},
835  {MO_GOT_HI16, "mips-got-hi16"},
836  {MO_GOT_LO16, "mips-got-lo16"},
837  {MO_CALL_HI16, "mips-call-hi16"},
838  {MO_CALL_LO16, "mips-call-lo16"},
839  {MO_JALR, "mips-jalr"}
840  };
841  return makeArrayRef(Flags);
842 }
static bool isReg(const MCInst &MI, unsigned OpNo)
unsigned getTargetFlags() const
unsigned getInstSizeInBytes(const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
const MachineInstrBuilder & add(const MachineOperand &MO) const
bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
MO_TLSLDM - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:62
HasForbiddenSlot - Instruction has a forbidden slot.
Definition: MipsBaseInfo.h:125
bool inMips16Mode() const
MO_HIGHER/HIGHEST - Represents the highest or higher half word of a 64-bit symbol address...
Definition: MipsBaseInfo.h:84
MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
Definition: MipsBaseInfo.h:88
MO_TLSGD - Represents the offset into the global offset table at which.
Definition: MipsBaseInfo.h:57
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:163
bool isInlineAsm() const
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:302
bool SafeInForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
bool HasForbiddenSlot(const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
#define op(i)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)
A description of a memory reference used in the backend.
MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc)
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:450
bool inMicroMipsMode() const
bool useIndirectJumpsHazard() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
const MipsSubtarget & Subtarget
Definition: MipsInstrInfo.h:45
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool hasMips32r6() const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:408
const char * getSymbolName() const
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
INLINEASM - Represents an inline asm block.
Definition: ISDOpcodes.h:695
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:405
bool isIndirectBranch(QueryType Type=AnyInBundle) const
Return true if this is an indirect branch, such as a branch through a register.
Definition: MachineInstr.h:662
bool isBundle() const
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
reverse_iterator rend()
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
reverse_iterator rbegin()
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
MO_GOT_CALL - Represents the offset into the global offset table at which the address of a call site ...
Definition: MipsBaseInfo.h:43
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)
Create MipsInstrInfo objects.
MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode...
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
bool isZeroImm(const MachineOperand &op) const
size_t size() const
Definition: SmallVector.h:52
bool isMCSymbol() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const MipsABIInfo & getABI() const
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
MO_GOTTPREL - Represents the offset from the thread pointer (Initial.
Definition: MipsBaseInfo.h:68
bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:841
int64_t getImm() const
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool isUnconditionalBranch(QueryType Type=AnyInBundle) const
Return true if this is a branch which always transfers control flow to some other block...
Definition: MachineInstr.h:678
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
iterator insert(iterator I, T &&Elt)
Definition: SmallVector.h:471
Flags
Flags values. These may be or&#39;d together.
MO_TPREL_HI/LO - Represents the hi and low part of the offset from.
Definition: MipsBaseInfo.h:72
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:253
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Representation of each machine instruction.
Definition: MachineInstr.h:63
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
IsCTI - Instruction is a Control Transfer Instruction.
Definition: MipsBaseInfo.h:123
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
uint32_t Size
Definition: Profile.cpp:46
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned GetZeroReg() const
Definition: MipsABIInfo.cpp:93
bool isReg() const
isReg - Tests if this is a MO_Register operand.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
Definition: ISDOpcodes.h:698
MCSymbol * getMCSymbol() const
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:413
static const MipsInstrInfo * create(MipsSubtarget &STI)
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:143
unsigned getSize() const
Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...
Definition: MCInstrDesc.h:580
Helper operand used to generate R_MIPS_JALR.
Definition: MipsBaseInfo.h:94