Go to the documentation of this file.
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
31 #define GET_SUBTARGETINFO_HEADER
32 #include "MipsGenSubtargetInfo.inc"
37 class MipsTargetMachine;
40 virtual void anchor();
44 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
45 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
48 enum class CPU { P5600 };
51 static bool DspWarningPrinted;
54 static bool MSAWarningPrinted;
57 static bool CRCWarningPrinted;
60 static bool GINVWarningPrinted;
63 static bool MIPS1WarningPrinted;
66 static bool VirtWarningPrinted;
69 MipsArchEnum MipsArchVersion;
124 bool UseSmallSection;
147 bool InMips16HardFloat;
150 bool InMicroMipsMode;
153 bool HasDSP, HasDSPR2, HasDSPR3;
159 bool AllowMixed16_32;
196 bool UseIndirectJumpsHazard;
199 bool UseLongCalls =
false;
202 bool UseXGOT =
false;
206 Align stackAlignment;
215 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
222 std::unique_ptr<const MipsInstrInfo> InstrInfo;
223 std::unique_ptr<const MipsFrameLowering> FrameLowering;
224 std::unique_ptr<const MipsTargetLowering> TLInfo;
248 bool hasMips1()
const {
return MipsArchVersion >= Mips1; }
249 bool hasMips2()
const {
return MipsArchVersion >= Mips2; }
250 bool hasMips3()
const {
return MipsArchVersion >= Mips3; }
251 bool hasMips4()
const {
return MipsArchVersion >= Mips4; }
252 bool hasMips5()
const {
return MipsArchVersion >= Mips5; }
256 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
260 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
264 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
268 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
272 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
275 bool hasMips64()
const {
return MipsArchVersion >= Mips64; }
321 bool has3D()
const {
return Has3D; }
325 bool hasMT()
const {
return HasMT; }
353 bool os16()
const {
return Os16; }
387 return FrameLowering.get();
This is an optimization pass for GlobalISel generic memory operations.
bool inAbs2008Mode() const
Information about stack frame layout on the target.
bool isPositionIndependent() const
bool hasMips4_32r2() const
bool allowMixed16_32() const
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
const MipsABIInfo & getABI() const
Triple - Helper class for working with autoconf configuration names.
const CallLowering * getCallLowering() const override
unsigned getGPRSizeInBytes() const
const MipsInstrInfo * getInstrInfo() const override
bool useIndirectJumpsHazard() const
Align getStackAlignment() const
bool inMips16ModeDefault() const
static bool useConstantIslands()
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
const MipsRegisterInfo * getRegisterInfo() const override
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
const InstrItineraryData * getInstrItineraryData() const override
void setHelperClassesMipsSE()
bool inMips16Mode() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
const RegisterBankInfo * getRegBankInfo() const override
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
bool disableMadd4() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
void setHelperClassesMips16()
Holds all the information related to register banks.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
bool isSingleFloat() const
Primary interface to the complete machine description for the target machine.
bool hasExtractInsert() const
Features related to the presence of specific instructions.
std::unique_ptr< LegalizerInfo > Legalizer
bool isXRaySupported() const override
bool hasStandardEncoding() const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
StringRef - Represent a constant reference to a string, i.e.
const MipsTargetLowering * getTargetLowering() const override
std::unique_ptr< InstructionSelector > InstSelector
const LegalizerInfo * getLegalizerInfo() const override
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool inMicroMipsMode() const
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
const TargetFrameLowering * getFrameLowering() const override
std::unique_ptr< CallLowering > CallLoweringInfo
bool useSmallSection() const
bool isTargetNaCl() const
bool enableLongBranchPass() const
Level
Code generation optimization level.
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
bool useLongCalls() const
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool useSoftFloat() const
Reloc::Model getRelocationModel() const
InstructionSelector * getInstructionSelector() const override
Itinerary data supplied by a subtarget to be used by a target.
bool inMicroMips32r6Mode() const
bool inMips16HardFloat() const