LLVM  13.0.0git
MipsSubtarget.h
Go to the documentation of this file.
1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the Mips specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14 #define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15 
17 #include "MipsFrameLowering.h"
18 #include "MipsISelLowering.h"
19 #include "MipsInstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
29 #include <string>
30 
31 #define GET_SUBTARGETINFO_HEADER
32 #include "MipsGenSubtargetInfo.inc"
33 
34 namespace llvm {
35 class StringRef;
36 
37 class MipsTargetMachine;
38 
40  virtual void anchor();
41 
42  enum MipsArchEnum {
43  MipsDefault,
44  Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
45  Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
46  };
47 
48  enum class CPU { P5600 };
49 
50  // Used to avoid printing dsp warnings multiple times.
51  static bool DspWarningPrinted;
52 
53  // Used to avoid printing msa warnings multiple times.
54  static bool MSAWarningPrinted;
55 
56  // Used to avoid printing crc warnings multiple times.
57  static bool CRCWarningPrinted;
58 
59  // Used to avoid printing ginv warnings multiple times.
60  static bool GINVWarningPrinted;
61 
62  // Used to avoid printing virt warnings multiple times.
63  static bool VirtWarningPrinted;
64 
65  // Mips architecture version
66  MipsArchEnum MipsArchVersion;
67 
68  // Processor implementation (unused but required to exist by
69  // tablegen-erated code).
70  CPU ProcImpl;
71 
72  // IsLittle - The target is Little Endian
73  bool IsLittle;
74 
75  // IsSoftFloat - The target does not support any floating point instructions.
76  bool IsSoftFloat;
77 
78  // IsSingleFloat - The target only supports single precision float
79  // point operations. This enable the target to use all 32 32-bit
80  // floating point registers instead of only using even ones.
81  bool IsSingleFloat;
82 
83  // IsFPXX - MIPS O32 modeless ABI.
84  bool IsFPXX;
85 
86  // NoABICalls - Disable SVR4-style position-independent code.
87  bool NoABICalls;
88 
89  // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
90  bool Abs2008;
91 
92  // IsFP64bit - The target processor has 64-bit floating point registers.
93  bool IsFP64bit;
94 
95  /// Are odd single-precision registers permitted?
96  /// This corresponds to -modd-spreg and -mno-odd-spreg
97  bool UseOddSPReg;
98 
99  // IsNan2008 - IEEE 754-2008 NaN encoding.
100  bool IsNaN2008bit;
101 
102  // IsGP64bit - General-purpose registers are 64 bits wide
103  bool IsGP64bit;
104 
105  // IsPTR64bit - Pointers are 64 bit wide
106  bool IsPTR64bit;
107 
108  // HasVFPU - Processor has a vector floating point unit.
109  bool HasVFPU;
110 
111  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
112  bool HasCnMips;
113 
114  // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
115  bool HasCnMipsP;
116 
117  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
118  bool IsLinux;
119 
120  // UseSmallSection - Small section is used.
121  bool UseSmallSection;
122 
123  /// Features related to the presence of specific instructions.
124 
125  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
126  bool HasMips3_32;
127 
128  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
129  bool HasMips3_32r2;
130 
131  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
132  bool HasMips4_32;
133 
134  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
135  bool HasMips4_32r2;
136 
137  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
138  bool HasMips5_32r2;
139 
140  // InMips16 -- can process Mips16 instructions
141  bool InMips16Mode;
142 
143  // Mips16 hard float
144  bool InMips16HardFloat;
145 
146  // InMicroMips -- can process MicroMips instructions
147  bool InMicroMipsMode;
148 
149  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
150  bool HasDSP, HasDSPR2, HasDSPR3;
151 
152  // Has3D -- Supports Mips3D ASE.
153  bool Has3D;
154 
155  // Allow mixed Mips16 and Mips32 in one source file
156  bool AllowMixed16_32;
157 
158  // Optimize for space by compiling all functions as Mips 16 unless
159  // it needs floating point. Functions needing floating point are
160  // compiled as Mips32
161  bool Os16;
162 
163  // HasMSA -- supports MSA ASE.
164  bool HasMSA;
165 
166  // UseTCCInDIV -- Enables the use of trapping in the assembler.
167  bool UseTCCInDIV;
168 
169  // Sym32 -- On Mips64 symbols are 32 bits.
170  bool HasSym32;
171 
172  // HasEVA -- supports EVA ASE.
173  bool HasEVA;
174 
175  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
176  // related instructions.
177  bool DisableMadd4;
178 
179  // HasMT -- support MT ASE.
180  bool HasMT;
181 
182  // HasCRC -- supports R6 CRC ASE
183  bool HasCRC;
184 
185  // HasVirt -- supports Virtualization ASE
186  bool HasVirt;
187 
188  // HasGINV -- supports R6 Global INValidate ASE
189  bool HasGINV;
190 
191  // Use hazard variants of the jump register instructions for indirect
192  // function calls and jump tables.
193  bool UseIndirectJumpsHazard;
194 
195  // Disable use of the `jal` instruction.
196  bool UseLongCalls = false;
197 
198  // Assume 32-bit GOT.
199  bool UseXGOT = false;
200 
201  /// The minimum alignment known to hold of the stack frame on
202  /// entry to the function and which must be maintained by every function.
203  Align stackAlignment;
204 
205  /// The overridden stack alignment.
206  MaybeAlign StackAlignOverride;
207 
208  InstrItineraryData InstrItins;
209 
210  // We can override the determination of whether we are in mips16 mode
211  // as from the command line
212  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
213 
214  const MipsTargetMachine &TM;
215 
216  Triple TargetTriple;
217 
218  const SelectionDAGTargetInfo TSInfo;
219  std::unique_ptr<const MipsInstrInfo> InstrInfo;
220  std::unique_ptr<const MipsFrameLowering> FrameLowering;
221  std::unique_ptr<const MipsTargetLowering> TLInfo;
222 
223 public:
224  bool isPositionIndependent() const;
225  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
226  bool enablePostRAScheduler() const override;
227  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
229 
230  bool isABI_N64() const;
231  bool isABI_N32() const;
232  bool isABI_O32() const;
233  const MipsABIInfo &getABI() const;
234  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
235 
236  /// This constructor initializes the data members to match that
237  /// of the specified triple.
238  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
239  const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
240 
241  /// ParseSubtargetFeatures - Parses features string setting specified
242  /// subtarget options. Definition of function is auto generated by tblgen.
244 
245  bool hasMips1() const { return MipsArchVersion >= Mips1; }
246  bool hasMips2() const { return MipsArchVersion >= Mips2; }
247  bool hasMips3() const { return MipsArchVersion >= Mips3; }
248  bool hasMips4() const { return MipsArchVersion >= Mips4; }
249  bool hasMips5() const { return MipsArchVersion >= Mips5; }
250  bool hasMips4_32() const { return HasMips4_32; }
251  bool hasMips4_32r2() const { return HasMips4_32r2; }
252  bool hasMips32() const {
253  return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
254  hasMips64();
255  }
256  bool hasMips32r2() const {
257  return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
258  hasMips64r2();
259  }
260  bool hasMips32r3() const {
261  return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
262  hasMips64r2();
263  }
264  bool hasMips32r5() const {
265  return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
266  hasMips64r5();
267  }
268  bool hasMips32r6() const {
269  return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
270  hasMips64r6();
271  }
272  bool hasMips64() const { return MipsArchVersion >= Mips64; }
273  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
274  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
275  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
276  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
277 
278  bool hasCnMips() const { return HasCnMips; }
279  bool hasCnMipsP() const { return HasCnMipsP; }
280 
281  bool isLittle() const { return IsLittle; }
282  bool isABICalls() const { return !NoABICalls; }
283  bool isFPXX() const { return IsFPXX; }
284  bool isFP64bit() const { return IsFP64bit; }
285  bool useOddSPReg() const { return UseOddSPReg; }
286  bool noOddSPReg() const { return !UseOddSPReg; }
287  bool isNaN2008() const { return IsNaN2008bit; }
288  bool inAbs2008Mode() const { return Abs2008; }
289  bool isGP64bit() const { return IsGP64bit; }
290  bool isGP32bit() const { return !IsGP64bit; }
291  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
292  bool isPTR64bit() const { return IsPTR64bit; }
293  bool isPTR32bit() const { return !IsPTR64bit; }
294  bool hasSym32() const {
295  return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
296  }
297  bool isSingleFloat() const { return IsSingleFloat; }
298  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
299  bool hasVFPU() const { return HasVFPU; }
300  bool inMips16Mode() const { return InMips16Mode; }
301  bool inMips16ModeDefault() const {
302  return InMips16Mode;
303  }
304  // Hard float for mips16 means essentially to compile as soft float
305  // but to use a runtime library for soft float that is written with
306  // native mips32 floating point instructions (those runtime routines
307  // run in mips32 hard float mode).
308  bool inMips16HardFloat() const {
309  return inMips16Mode() && InMips16HardFloat;
310  }
311  bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
312  bool inMicroMips32r6Mode() const {
313  return inMicroMipsMode() && hasMips32r6();
314  }
315  bool hasDSP() const { return HasDSP; }
316  bool hasDSPR2() const { return HasDSPR2; }
317  bool hasDSPR3() const { return HasDSPR3; }
318  bool has3D() const { return Has3D; }
319  bool hasMSA() const { return HasMSA; }
320  bool disableMadd4() const { return DisableMadd4; }
321  bool hasEVA() const { return HasEVA; }
322  bool hasMT() const { return HasMT; }
323  bool hasCRC() const { return HasCRC; }
324  bool hasVirt() const { return HasVirt; }
325  bool hasGINV() const { return HasGINV; }
326  bool useIndirectJumpsHazard() const {
327  return UseIndirectJumpsHazard && hasMips32r2();
328  }
329  bool useSmallSection() const { return UseSmallSection; }
330 
331  bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
332 
333  bool useSoftFloat() const { return IsSoftFloat; }
334 
335  bool useLongCalls() const { return UseLongCalls; }
336 
337  bool useXGOT() const { return UseXGOT; }
338 
339  bool enableLongBranchPass() const {
341  }
342 
343  /// Features related to the presence of specific instructions.
344  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
345  bool hasMTHC1() const { return hasMips32r2(); }
346 
347  bool allowMixed16_32() const { return inMips16ModeDefault() |
348  AllowMixed16_32; }
349 
350  bool os16() const { return Os16; }
351 
352  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
353 
354  bool isXRaySupported() const override { return true; }
355 
356  // for now constant islands are on for the whole compilation unit but we only
357  // really use them if in addition we are in mips16 mode
358  static bool useConstantIslands();
359 
360  Align getStackAlignment() const { return stackAlignment; }
361 
362  // Grab relocation model
364 
366  const TargetMachine &TM);
367 
368  /// Does the system support unaligned memory access.
369  ///
370  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
371  /// specify which component of the system provides it. Hardware, software, and
372  /// hybrid implementations are all valid.
373  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
374 
375  // Set helper classes
376  void setHelperClassesMips16();
377  void setHelperClassesMipsSE();
378 
379  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
380  return &TSInfo;
381  }
382  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
383  const TargetFrameLowering *getFrameLowering() const override {
384  return FrameLowering.get();
385  }
386  const MipsRegisterInfo *getRegisterInfo() const override {
387  return &InstrInfo->getRegisterInfo();
388  }
389  const MipsTargetLowering *getTargetLowering() const override {
390  return TLInfo.get();
391  }
392  const InstrItineraryData *getInstrItineraryData() const override {
393  return &InstrItins;
394  }
395 
396 protected:
397  // GlobalISel related APIs.
398  std::unique_ptr<CallLowering> CallLoweringInfo;
399  std::unique_ptr<LegalizerInfo> Legalizer;
400  std::unique_ptr<RegisterBankInfo> RegBankInfo;
401  std::unique_ptr<InstructionSelector> InstSelector;
402 
403 public:
404  const CallLowering *getCallLowering() const override;
405  const LegalizerInfo *getLegalizerInfo() const override;
406  const RegisterBankInfo *getRegBankInfo() const override;
408 };
409 } // End llvm namespace
410 
411 #endif
MipsGenSubtargetInfo
llvm::MipsTargetMachine
Definition: MipsTargetMachine.h:27
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::MipsSubtarget::noOddSPReg
bool noOddSPReg() const
Definition: MipsSubtarget.h:286
llvm::MipsSubtarget::inAbs2008Mode
bool inAbs2008Mode() const
Definition: MipsSubtarget.h:288
llvm::MipsSubtarget::hasMips32r2
bool hasMips32r2() const
Definition: MipsSubtarget.h:256
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:42
CallLowering.h
llvm::MipsSubtarget::hasMips32r3
bool hasMips32r3() const
Definition: MipsSubtarget.h:260
llvm::MipsABIInfo
Definition: MipsABIInfo.h:22
llvm::MipsSubtarget::isTargetELF
bool isTargetELF() const
Definition: MipsSubtarget.h:298
llvm::MipsSubtarget::isPositionIndependent
bool isPositionIndependent() const
Definition: MipsSubtarget.cpp:220
llvm::MipsSubtarget::hasMips4_32r2
bool hasMips4_32r2() const
Definition: MipsSubtarget.h:251
llvm::MipsSubtarget::allowMixed16_32
bool allowMixed16_32() const
Definition: MipsSubtarget.h:347
llvm::MipsSubtarget::systemSupportsUnalignedAccess
bool systemSupportsUnalignedAccess() const
Does the system support unaligned memory access.
Definition: MipsSubtarget.h:373
llvm::MipsSubtarget::hasMips3
bool hasMips3() const
Definition: MipsSubtarget.h:247
ErrorHandling.h
llvm::MipsSubtarget::hasMips5
bool hasMips5() const
Definition: MipsSubtarget.h:249
llvm::MipsSubtarget::hasMips4_32
bool hasMips4_32() const
Definition: MipsSubtarget.h:250
llvm::MipsSubtarget::hasMips64r6
bool hasMips64r6() const
Definition: MipsSubtarget.h:276
RegisterBankInfo.h
llvm::MipsSubtarget::getABI
const MipsABIInfo & getABI() const
Definition: MipsSubtarget.cpp:279
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::MipsSubtarget::getCallLowering
const CallLowering * getCallLowering() const override
Definition: MipsSubtarget.cpp:281
llvm::MipsSubtarget::hasMips64
bool hasMips64() const
Definition: MipsSubtarget.h:272
llvm::MipsSubtarget::getGPRSizeInBytes
unsigned getGPRSizeInBytes() const
Definition: MipsSubtarget.h:291
llvm::MipsSubtarget::hasSym32
bool hasSym32() const
Definition: MipsSubtarget.h:294
llvm::MipsSubtarget::getInstrInfo
const MipsInstrInfo * getInstrInfo() const override
Definition: MipsSubtarget.h:382
llvm::MipsSubtarget::useOddSPReg
bool useOddSPReg() const
Definition: MipsSubtarget.h:285
llvm::MipsSubtarget::useIndirectJumpsHazard
bool useIndirectJumpsHazard() const
Definition: MipsSubtarget.h:326
llvm::MipsSubtarget::hasDSPR3
bool hasDSPR3() const
Definition: MipsSubtarget.h:317
llvm::MipsSubtarget::getStackAlignment
Align getStackAlignment() const
Definition: MipsSubtarget.h:360
llvm::MipsSubtarget::isFPXX
bool isFPXX() const
Definition: MipsSubtarget.h:283
llvm::MipsSubtarget::isNaN2008
bool isNaN2008() const
Definition: MipsSubtarget.h:287
llvm::X86AS::FS
@ FS
Definition: X86.h:182
LegalizerInfo.h
llvm::MipsSubtarget::hasMT
bool hasMT() const
Definition: MipsSubtarget.h:322
llvm::MipsSubtarget::inMips16ModeDefault
bool inMips16ModeDefault() const
Definition: MipsSubtarget.h:301
llvm::MipsSubtarget::useConstantIslands
static bool useConstantIslands()
Definition: MipsSubtarget.cpp:266
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::MipsSubtarget::initializeSubtargetDependencies
MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)
Definition: MipsSubtarget.cpp:238
llvm::MipsSubtarget::getRegisterInfo
const MipsRegisterInfo * getRegisterInfo() const override
Definition: MipsSubtarget.h:386
llvm::MipsSubtarget::hasMTHC1
bool hasMTHC1() const
Definition: MipsSubtarget.h:345
MCInstrItineraries.h
llvm::Triple::isOSBinFormatELF
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:630
llvm::MipsSubtarget::getInstrItineraryData
const InstrItineraryData * getInstrItineraryData() const override
Definition: MipsSubtarget.h:392
llvm::MipsSubtarget::hasMips1
bool hasMips1() const
Definition: MipsSubtarget.h:245
llvm::MipsSubtarget::setHelperClassesMipsSE
void setHelperClassesMipsSE()
llvm::MipsSubtarget::isGP32bit
bool isGP32bit() const
Definition: MipsSubtarget.h:290
llvm::support::little
@ little
Definition: Endian.h:27
llvm::MipsSubtarget::os16
bool os16() const
Definition: MipsSubtarget.h:350
llvm::MipsSubtarget::inMips16Mode
bool inMips16Mode() const
Definition: MipsSubtarget.h:300
llvm::MipsSubtarget::hasMips2
bool hasMips2() const
Definition: MipsSubtarget.h:246
llvm::SelectionDAGTargetInfo
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Definition: SelectionDAGTargetInfo.h:31
llvm::MipsSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: MipsSubtarget.cpp:289
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
llvm::MipsInstrInfo
Definition: MipsInstrInfo.h:41
llvm::MipsSubtarget::isPTR64bit
bool isPTR64bit() const
Definition: MipsSubtarget.h:292
llvm::MipsSubtarget::hasMips64r3
bool hasMips64r3() const
Definition: MipsSubtarget.h:274
llvm::MipsSubtarget::disableMadd4
bool disableMadd4() const
Definition: MipsSubtarget.h:320
llvm::MipsSubtarget::hasMips32r5
bool hasMips32r5() const
Definition: MipsSubtarget.h:264
llvm::MipsSubtarget::hasMips64r5
bool hasMips64r5() const
Definition: MipsSubtarget.h:275
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::MipsSubtarget::hasCRC
bool hasCRC() const
Definition: MipsSubtarget.h:323
llvm::Triple::isOSNaCl
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:588
llvm::MipsSubtarget::isPTR32bit
bool isPTR32bit() const
Definition: MipsSubtarget.h:293
llvm::MipsSubtarget::isABI_FPXX
bool isABI_FPXX() const
Definition: MipsSubtarget.h:234
llvm::MipsSubtarget::hasMips32
bool hasMips32() const
Definition: MipsSubtarget.h:252
llvm::MipsSubtarget::isLittle
bool isLittle() const
Definition: MipsSubtarget.h:281
llvm::MipsSubtarget::setHelperClassesMips16
void setHelperClassesMips16()
InstructionSelector.h
llvm::MipsSubtarget::hasCnMips
bool hasCnMips() const
Definition: MipsSubtarget.h:278
llvm::RegisterBankInfo
Holds all the information related to register banks.
Definition: RegisterBankInfo.h:39
llvm::MipsSubtarget::RegBankInfo
std::unique_ptr< RegisterBankInfo > RegBankInfo
Definition: MipsSubtarget.h:400
llvm::InstructionSelector
Provides the logic to select generic machine instructions.
Definition: InstructionSelector.h:418
llvm::MipsSubtarget::hasMips32r6
bool hasMips32r6() const
Definition: MipsSubtarget.h:268
llvm::MipsSubtarget::getOptLevelToEnablePostRAScheduler
CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override
Definition: MipsSubtarget.cpp:233
MipsFrameLowering.h
llvm::MipsSubtarget::isABI_N32
bool isABI_N32() const
Definition: MipsSubtarget.cpp:277
llvm::MipsRegisterInfo
Definition: MipsRegisterInfo.h:27
llvm::MipsSubtarget::isSingleFloat
bool isSingleFloat() const
Definition: MipsSubtarget.h:297
llvm::MipsSubtarget::hasEVA
bool hasEVA() const
Definition: MipsSubtarget.h:321
llvm::MipsSubtarget::hasVFPU
bool hasVFPU() const
Definition: MipsSubtarget.h:299
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MipsSubtarget::isABI_N64
bool isABI_N64() const
Definition: MipsSubtarget.cpp:276
llvm::MipsSubtarget::hasCnMipsP
bool hasCnMipsP() const
Definition: MipsSubtarget.h:279
llvm::MipsSubtarget::hasExtractInsert
bool hasExtractInsert() const
Features related to the presence of specific instructions.
Definition: MipsSubtarget.h:344
llvm::MipsSubtarget::Legalizer
std::unique_ptr< LegalizerInfo > Legalizer
Definition: MipsSubtarget.h:399
llvm::MipsSubtarget::isXRaySupported
bool isXRaySupported() const override
Definition: MipsSubtarget.h:354
llvm::MipsSubtarget::hasStandardEncoding
bool hasStandardEncoding() const
Definition: MipsSubtarget.h:331
llvm::MipsSubtarget::hasDSP
bool hasDSP() const
Definition: MipsSubtarget.h:315
llvm::MipsSubtarget::getSelectionDAGInfo
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
Definition: MipsSubtarget.h:379
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MipsSubtarget::getTargetLowering
const MipsTargetLowering * getTargetLowering() const override
Definition: MipsSubtarget.h:389
llvm::MipsSubtarget::hasDSPR2
bool hasDSPR2() const
Definition: MipsSubtarget.h:316
llvm::MipsSubtarget::InstSelector
std::unique_ptr< InstructionSelector > InstSelector
Definition: MipsSubtarget.h:401
llvm::MipsSubtarget::getLegalizerInfo
const LegalizerInfo * getLegalizerInfo() const override
Definition: MipsSubtarget.cpp:285
TargetSubtargetInfo.h
llvm::MipsSubtarget::useXGOT
bool useXGOT() const
Definition: MipsSubtarget.h:337
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::MipsSubtarget
Definition: MipsSubtarget.h:39
llvm::MipsSubtarget::ParseSubtargetFeatures
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
llvm::MipsTargetLowering
Definition: MipsISelLowering.h:261
llvm::MipsSubtarget::hasVirt
bool hasVirt() const
Definition: MipsSubtarget.h:324
llvm::MipsSubtarget::inMicroMipsMode
bool inMicroMipsMode() const
Definition: MipsSubtarget.h:311
llvm::MipsSubtarget::enablePostRAScheduler
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
Definition: MipsSubtarget.cpp:225
llvm::MipsSubtarget::hasMSA
bool hasMSA() const
Definition: MipsSubtarget.h:319
llvm::MipsSubtarget::isGP64bit
bool isGP64bit() const
Definition: MipsSubtarget.h:289
MipsISelLowering.h
MipsABIInfo.h
llvm::MipsSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition: MipsSubtarget.h:383
llvm::MipsSubtarget::isABI_O32
bool isABI_O32() const
Definition: MipsSubtarget.cpp:278
llvm::MipsSubtarget::isABICalls
bool isABICalls() const
Definition: MipsSubtarget.h:282
llvm::MipsSubtarget::has3D
bool has3D() const
Definition: MipsSubtarget.h:318
llvm::MipsSubtarget::CallLoweringInfo
std::unique_ptr< CallLowering > CallLoweringInfo
Definition: MipsSubtarget.h:398
llvm::MipsSubtarget::hasMips4
bool hasMips4() const
Definition: MipsSubtarget.h:248
llvm::MipsSubtarget::useSmallSection
bool useSmallSection() const
Definition: MipsSubtarget.h:329
MipsInstrInfo.h
SelectionDAGTargetInfo.h
llvm::MipsSubtarget::isTargetNaCl
bool isTargetNaCl() const
Definition: MipsSubtarget.h:352
llvm::MipsSubtarget::isFP64bit
bool isFP64bit() const
Definition: MipsSubtarget.h:284
llvm::LegalizerInfo
Definition: LegalizerInfo.h:1041
llvm::MipsSubtarget::enableLongBranchPass
bool enableLongBranchPass() const
Definition: MipsSubtarget.h:339
llvm::MipsSubtarget::MipsSubtarget
MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)
This constructor initializes the data members to match that of the specified triple.
Definition: MipsSubtarget.cpp:70
llvm::MipsSubtarget::useLongCalls
bool useLongCalls() const
Definition: MipsSubtarget.h:335
llvm::MipsSubtarget::getCriticalPathRCs
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
Definition: MipsSubtarget.cpp:227
llvm::MipsSubtarget::useSoftFloat
bool useSoftFloat() const
Definition: MipsSubtarget.h:333
llvm::MipsSubtarget::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: MipsSubtarget.cpp:272
llvm::CallLowering
Definition: CallLowering.h:42
llvm::MipsSubtarget::hasMips64r2
bool hasMips64r2() const
Definition: MipsSubtarget.h:273
llvm::MipsSubtarget::getInstructionSelector
InstructionSelector * getInstructionSelector() const override
Definition: MipsSubtarget.cpp:293
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::MipsSubtarget::inMicroMips32r6Mode
bool inMicroMips32r6Mode() const
Definition: MipsSubtarget.h:312
llvm::MipsSubtarget::hasGINV
bool hasGINV() const
Definition: MipsSubtarget.h:325
llvm::MipsSubtarget::inMips16HardFloat
bool inMips16HardFloat() const
Definition: MipsSubtarget.h:308