36 #define DEBUG_TYPE "ve-asmparser"
48 #define GET_ASSEMBLER_HEADER
49 #include "VEGenAsmMatcher.inc"
54 bool MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
57 bool MatchingInlineAsm)
override;
59 SMLoc &EndLoc)
override;
60 int parseRegisterName(
unsigned (*matchFn)(
StringRef));
62 SMLoc &EndLoc)
override;
65 bool ParseDirective(
AsmToken DirectiveID)
override;
68 unsigned Kind)
override;
83 bool parseExpression(
const MCExpr *&EVal);
89 bool parseLiteralValues(
unsigned Size,
SMLoc L);
96 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
103 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
104 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
105 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
106 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
107 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
108 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
109 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
110 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
111 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
115 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
116 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
117 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
118 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
119 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
120 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
121 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
122 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
123 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
127 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
128 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
129 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
130 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
133 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
136 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
137 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
138 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
139 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
140 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
141 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
142 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
143 VE::PMC12, VE::PMC13, VE::PMC14};
169 SMLoc StartLoc, EndLoc;
215 VEOperand(KindTy K) :
Kind(K) {}
217 bool isToken()
const override {
return Kind == k_Token; }
218 bool isReg()
const override {
return Kind == k_Register; }
219 bool isImm()
const override {
return Kind == k_Immediate; }
220 bool isMem()
const override {
221 return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||
224 bool isMEMrri()
const {
return Kind == k_MemoryRegRegImm; }
225 bool isMEMrii()
const {
return Kind == k_MemoryRegImmImm; }
226 bool isMEMzri()
const {
return Kind == k_MemoryZeroRegImm; }
227 bool isMEMzii()
const {
return Kind == k_MemoryZeroImmImm; }
228 bool isMEMri()
const {
return Kind == k_MemoryRegImm; }
229 bool isMEMzi()
const {
return Kind == k_MemoryZeroImm; }
230 bool isCCOp()
const {
return Kind == k_CCOp; }
231 bool isRDOp()
const {
return Kind == k_RDOp; }
237 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
238 int64_t
Value = ConstExpr->getValue();
248 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
249 int64_t
Value = ConstExpr->getValue();
259 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
260 int64_t
Value = ConstExpr->getValue();
261 return isUInt<1>(
Value);
270 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
271 int64_t
Value = ConstExpr->getValue();
272 return isUInt<2>(
Value);
281 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
282 int64_t
Value = ConstExpr->getValue();
283 return isUInt<3>(
Value);
292 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
293 int64_t
Value = ConstExpr->getValue();
294 return isUInt<4>(
Value);
303 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
304 int64_t
Value = ConstExpr->getValue();
305 return isUInt<6>(
Value);
314 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
315 int64_t
Value = ConstExpr->getValue();
316 return isUInt<7>(
Value);
325 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Imm.Val)) {
326 int64_t
Value = ConstExpr->getValue();
327 return isInt<7>(
Value);
332 if (
Kind != k_MImmOp)
336 if (
const auto *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
337 int64_t
Value = ConstExpr->getValue();
338 return isUInt<6>(
Value);
348 unsigned getReg()
const override {
349 assert((
Kind == k_Register) &&
"Invalid access!");
353 const MCExpr *getImm()
const {
354 assert((
Kind == k_Immediate) &&
"Invalid access!");
358 unsigned getMemBase()
const {
360 Kind == k_MemoryRegImm) &&
365 unsigned getMemIndexReg()
const {
366 assert((
Kind == k_MemoryRegRegImm ||
Kind == k_MemoryZeroRegImm) &&
371 const MCExpr *getMemIndex()
const {
372 assert((
Kind == k_MemoryRegImmImm ||
Kind == k_MemoryZeroImmImm) &&
377 const MCExpr *getMemOffset()
const {
379 Kind == k_MemoryZeroImmImm ||
Kind == k_MemoryZeroRegImm ||
380 Kind == k_MemoryRegImm ||
Kind == k_MemoryZeroImm) &&
385 void setMemOffset(
const MCExpr *off) {
387 Kind == k_MemoryZeroImmImm ||
Kind == k_MemoryZeroRegImm ||
388 Kind == k_MemoryRegImm ||
Kind == k_MemoryZeroImm) &&
393 unsigned getCCVal()
const {
394 assert((
Kind == k_CCOp) &&
"Invalid access!");
398 unsigned getRDVal()
const {
399 assert((
Kind == k_RDOp) &&
"Invalid access!");
403 const MCExpr *getMImmVal()
const {
404 assert((
Kind == k_MImmOp) &&
"Invalid access!");
407 bool getM0Flag()
const {
408 assert((
Kind == k_MImmOp) &&
"Invalid access!");
413 SMLoc getStartLoc()
const override {
return StartLoc; }
415 SMLoc getEndLoc()
const override {
return EndLoc; }
420 OS <<
"Token: " << getToken() <<
"\n";
423 OS <<
"Reg: #" <<
getReg() <<
"\n";
426 OS <<
"Imm: " << getImm() <<
"\n";
428 case k_MemoryRegRegImm:
429 assert(getMemOffset() !=
nullptr);
430 OS <<
"Mem: #" << getMemBase() <<
"+#" << getMemIndexReg() <<
"+"
431 << *getMemOffset() <<
"\n";
433 case k_MemoryRegImmImm:
434 assert(getMemIndex() !=
nullptr && getMemOffset() !=
nullptr);
435 OS <<
"Mem: #" << getMemBase() <<
"+" << *getMemIndex() <<
"+"
436 << *getMemOffset() <<
"\n";
438 case k_MemoryZeroRegImm:
439 assert(getMemOffset() !=
nullptr);
440 OS <<
"Mem: 0+#" << getMemIndexReg() <<
"+" << *getMemOffset() <<
"\n";
442 case k_MemoryZeroImmImm:
443 assert(getMemIndex() !=
nullptr && getMemOffset() !=
nullptr);
444 OS <<
"Mem: 0+" << *getMemIndex() <<
"+" << *getMemOffset() <<
"\n";
447 assert(getMemOffset() !=
nullptr);
448 OS <<
"Mem: #" << getMemBase() <<
"+" << *getMemOffset() <<
"\n";
450 case k_MemoryZeroImm:
451 assert(getMemOffset() !=
nullptr);
452 OS <<
"Mem: 0+" << *getMemOffset() <<
"\n";
455 OS <<
"CCOp: " << getCCVal() <<
"\n";
458 OS <<
"RDOp: " << getRDVal() <<
"\n";
461 OS <<
"MImm: (" << getMImmVal() << (getM0Flag() ?
")0" :
")1") <<
"\n";
466 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
467 assert(
N == 1 &&
"Invalid number of operands!");
471 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
472 assert(
N == 1 &&
"Invalid number of operands!");
473 const MCExpr *Expr = getImm();
477 void addZeroOperands(
MCInst &Inst,
unsigned N)
const {
478 addImmOperands(Inst,
N);
481 void addUImm0to2Operands(
MCInst &Inst,
unsigned N)
const {
482 addImmOperands(Inst,
N);
485 void addUImm1Operands(
MCInst &Inst,
unsigned N)
const {
486 addImmOperands(Inst,
N);
489 void addUImm2Operands(
MCInst &Inst,
unsigned N)
const {
490 addImmOperands(Inst,
N);
493 void addUImm3Operands(
MCInst &Inst,
unsigned N)
const {
494 addImmOperands(Inst,
N);
497 void addUImm4Operands(
MCInst &Inst,
unsigned N)
const {
498 addImmOperands(Inst,
N);
501 void addUImm6Operands(
MCInst &Inst,
unsigned N)
const {
502 addImmOperands(Inst,
N);
505 void addUImm7Operands(
MCInst &Inst,
unsigned N)
const {
506 addImmOperands(Inst,
N);
509 void addSImm7Operands(
MCInst &Inst,
unsigned N)
const {
510 addImmOperands(Inst,
N);
517 else if (
const auto *CE = dyn_cast<MCConstantExpr>(Expr))
523 void addMEMrriOperands(
MCInst &Inst,
unsigned N)
const {
524 assert(
N == 3 &&
"Invalid number of operands!");
528 addExpr(Inst, getMemOffset());
531 void addMEMriiOperands(
MCInst &Inst,
unsigned N)
const {
532 assert(
N == 3 &&
"Invalid number of operands!");
535 addExpr(Inst, getMemIndex());
536 addExpr(Inst, getMemOffset());
539 void addMEMzriOperands(
MCInst &Inst,
unsigned N)
const {
540 assert(
N == 3 &&
"Invalid number of operands!");
544 addExpr(Inst, getMemOffset());
547 void addMEMziiOperands(
MCInst &Inst,
unsigned N)
const {
548 assert(
N == 3 &&
"Invalid number of operands!");
551 addExpr(Inst, getMemIndex());
552 addExpr(Inst, getMemOffset());
555 void addMEMriOperands(
MCInst &Inst,
unsigned N)
const {
556 assert(
N == 2 &&
"Invalid number of operands!");
559 addExpr(Inst, getMemOffset());
562 void addMEMziOperands(
MCInst &Inst,
unsigned N)
const {
563 assert(
N == 2 &&
"Invalid number of operands!");
566 addExpr(Inst, getMemOffset());
569 void addCCOpOperands(
MCInst &Inst,
unsigned N)
const {
570 assert(
N == 1 &&
"Invalid number of operands!");
575 void addRDOpOperands(
MCInst &Inst,
unsigned N)
const {
576 assert(
N == 1 &&
"Invalid number of operands!");
581 void addMImmOperands(
MCInst &Inst,
unsigned N)
const {
582 assert(
N == 1 &&
"Invalid number of operands!");
583 const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());
584 assert(ConstExpr &&
"Null operands!");
585 int64_t
Value = ConstExpr->getValue();
591 static std::unique_ptr<VEOperand> CreateToken(
StringRef Str,
SMLoc S) {
592 auto Op = std::make_unique<VEOperand>(k_Token);
593 Op->Tok.Data = Str.data();
594 Op->Tok.Length = Str.size();
600 static std::unique_ptr<VEOperand> CreateReg(
unsigned RegNum,
SMLoc S,
602 auto Op = std::make_unique<VEOperand>(k_Register);
603 Op->Reg.RegNum = RegNum;
609 static std::unique_ptr<VEOperand> CreateImm(
const MCExpr *Val,
SMLoc S,
611 auto Op = std::make_unique<VEOperand>(k_Immediate);
618 static std::unique_ptr<VEOperand> CreateCCOp(
unsigned CCVal,
SMLoc S,
620 auto Op = std::make_unique<VEOperand>(k_CCOp);
621 Op->CC.CCVal = CCVal;
627 static std::unique_ptr<VEOperand> CreateRDOp(
unsigned RDVal,
SMLoc S,
629 auto Op = std::make_unique<VEOperand>(k_RDOp);
630 Op->RD.RDVal = RDVal;
636 static std::unique_ptr<VEOperand> CreateMImm(
const MCExpr *Val,
bool Flag,
638 auto Op = std::make_unique<VEOperand>(k_MImmOp);
646 static bool MorphToI32Reg(VEOperand &
Op) {
647 unsigned Reg =
Op.getReg();
648 unsigned regIdx =
Reg - VE::SX0;
655 static bool MorphToF32Reg(VEOperand &
Op) {
656 unsigned Reg =
Op.getReg();
657 unsigned regIdx =
Reg - VE::SX0;
664 static bool MorphToF128Reg(VEOperand &
Op) {
665 unsigned Reg =
Op.getReg();
666 unsigned regIdx =
Reg - VE::SX0;
667 if (regIdx % 2 || regIdx > 63)
673 static bool MorphToVM512Reg(VEOperand &
Op) {
674 unsigned Reg =
Op.getReg();
675 unsigned regIdx =
Reg - VE::VM0;
676 if (regIdx % 2 || regIdx > 15)
682 static bool MorphToMISCReg(VEOperand &
Op) {
683 const auto *ConstExpr = dyn_cast<MCConstantExpr>(
Op.getImm());
686 unsigned regIdx = ConstExpr->getValue();
687 if (regIdx > 31 ||
MISCRegs[regIdx] == VE::NoRegister)
689 Op.Kind = k_Register;
694 static std::unique_ptr<VEOperand>
695 MorphToMEMri(
unsigned Base, std::unique_ptr<VEOperand>
Op) {
697 Op->Kind = k_MemoryRegImm;
699 Op->Mem.IndexReg = 0;
700 Op->Mem.Index =
nullptr;
701 Op->Mem.Offset =
Imm;
705 static std::unique_ptr<VEOperand>
706 MorphToMEMzi(std::unique_ptr<VEOperand>
Op) {
708 Op->Kind = k_MemoryZeroImm;
710 Op->Mem.IndexReg = 0;
711 Op->Mem.Index =
nullptr;
712 Op->Mem.Offset =
Imm;
716 static std::unique_ptr<VEOperand>
717 MorphToMEMrri(
unsigned Base,
unsigned Index, std::unique_ptr<VEOperand>
Op) {
719 Op->Kind = k_MemoryRegRegImm;
722 Op->Mem.Index =
nullptr;
723 Op->Mem.Offset =
Imm;
727 static std::unique_ptr<VEOperand>
729 std::unique_ptr<VEOperand>
Op) {
731 Op->Kind = k_MemoryRegImmImm;
733 Op->Mem.IndexReg = 0;
735 Op->Mem.Offset =
Imm;
739 static std::unique_ptr<VEOperand>
740 MorphToMEMzri(
unsigned Index, std::unique_ptr<VEOperand>
Op) {
742 Op->Kind = k_MemoryZeroRegImm;
745 Op->Mem.Index =
nullptr;
746 Op->Mem.Offset =
Imm;
750 static std::unique_ptr<VEOperand>
751 MorphToMEMzii(
const MCExpr *
Index, std::unique_ptr<VEOperand>
Op) {
753 Op->Kind = k_MemoryZeroImmImm;
755 Op->Mem.IndexReg = 0;
757 Op->Mem.Offset =
Imm;
764 bool VEAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
767 bool MatchingInlineAsm) {
769 unsigned MatchResult =
771 switch (MatchResult) {
777 case Match_MissingFeature:
779 "instruction requires a CPU feature not currently enabled");
781 case Match_InvalidOperand: {
782 SMLoc ErrorLoc = IDLoc;
785 return Error(IDLoc,
"too few operands for instruction");
788 if (ErrorLoc ==
SMLoc())
792 return Error(ErrorLoc,
"invalid operand for instruction");
794 case Match_MnemonicFail:
795 return Error(IDLoc,
"invalid instruction mnemonic");
803 return Error(StartLoc,
"invalid register name");
809 int VEAsmParser::parseRegisterName(
unsigned (*matchFn)(
StringRef)) {
812 int RegNum = matchFn(
Name);
816 if (RegNum == VE::NoRegister) {
817 RegNum = matchFn(
Name.lower());
843 if (RegNo == VE::NoRegister)
846 if (RegNo != VE::NoRegister) {
851 getLexer().UnLex(Tok);
856 bool IntegerCC,
bool OmitCC,
SMLoc NameLoc,
870 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
876 if (!SuffixStr.
empty())
877 Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));
879 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
894 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
903 Operands->push_back(VEOperand::CreateToken(
Name, NameLoc));
915 if (
Name[0] ==
'b') {
918 size_t Next =
Name.find(
'.');
920 if (
Name.size() > 1 &&
Name[1] ==
'r')
924 if (Next + 1 <
Name.size() &&
925 (
Name[Next + 1] ==
'd' ||
Name[Next + 1] ==
's'))
928 }
else if (
Name.startswith(
"cmov.l.") ||
Name.startswith(
"cmov.w.") ||
929 Name.startswith(
"cmov.d.") ||
Name.startswith(
"cmov.s.")) {
930 bool ICC =
Name[5] ==
'l' ||
Name[5] ==
'w';
932 }
else if (
Name.startswith(
"cvt.w.d.sx") ||
Name.startswith(
"cvt.w.d.zx") ||
933 Name.startswith(
"cvt.w.s.sx") ||
Name.startswith(
"cvt.w.s.zx")) {
935 }
else if (
Name.startswith(
"cvt.l.d")) {
937 }
else if (
Name.startswith(
"vcvt.w.d.sx") ||
Name.startswith(
"vcvt.w.d.zx") ||
938 Name.startswith(
"vcvt.w.s.sx") ||
Name.startswith(
"vcvt.w.s.zx")) {
940 }
else if (
Name.startswith(
"vcvt.l.d")) {
942 }
else if (
Name.startswith(
"pvcvt.w.s.lo") ||
943 Name.startswith(
"pvcvt.w.s.up")) {
945 }
else if (
Name.startswith(
"pvcvt.w.s")) {
947 }
else if (
Name.startswith(
"vfmk.l.") ||
Name.startswith(
"vfmk.w.") ||
948 Name.startswith(
"vfmk.d.") ||
Name.startswith(
"vfmk.s.")) {
949 bool ICC =
Name[5] ==
'l' ||
Name[5] ==
'w' ?
true :
false;
951 }
else if (
Name.startswith(
"pvfmk.w.lo.") ||
Name.startswith(
"pvfmk.w.up.") ||
952 Name.startswith(
"pvfmk.s.lo.") ||
Name.startswith(
"pvfmk.s.up.")) {
953 bool ICC =
Name[6] ==
'l' ||
Name[6] ==
'w' ?
true :
false;
956 Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));
980 SMLoc Loc = getLexer().getLoc();
981 return Error(Loc,
"unexpected token");
988 SMLoc Loc = getLexer().getLoc();
989 return Error(Loc,
"unexpected token");
994 SMLoc Loc = getLexer().getLoc();
995 return Error(Loc,
"unexpected token");
1001 bool VEAsmParser::ParseDirective(
AsmToken DirectiveID) {
1009 if (IDVal ==
".word")
1010 return parseLiteralValues(4, DirectiveID.
getLoc());
1013 if (IDVal ==
".long")
1014 return parseLiteralValues(8, DirectiveID.
getLoc());
1017 if (IDVal ==
".llong")
1018 return parseLiteralValues(8, DirectiveID.
getLoc());
1028 bool VEAsmParser::parseLiteralValues(
unsigned Size,
SMLoc L) {
1029 auto parseOne = [&]() ->
bool {
1031 if (getParser().parseExpression(
Value))
1033 getParser().getStreamer().emitValue(
Value,
Size, L);
1036 return (parseMany(parseOne));
1046 VEAsmParser::extractModifierFromExpr(
const MCExpr *
E,
1051 switch (
E->getKind()) {
1124 const MCExpr *
LHS = extractModifierFromExpr(BE->
getLHS(), LHSVariant);
1125 const MCExpr *
RHS = extractModifierFromExpr(BE->
getRHS(), RHSVariant);
1139 else if (LHSVariant == RHSVariant)
1151 const MCExpr *VEAsmParser::fixupVariantKind(
const MCExpr *
E) {
1154 switch (
E->getKind()) {
1183 bool VEAsmParser::parseExpression(
const MCExpr *&EVal) {
1185 if (getParser().parseExpression(EVal))
1189 EVal = fixupVariantKind(EVal);
1191 const MCExpr *
E = extractModifierFromExpr(EVal, Variant);
1212 std::unique_ptr<VEOperand>
Offset;
1213 switch (getLexer().getKind()) {
1222 if (!parseExpression(EVal))
1223 Offset = VEOperand::CreateImm(EVal,
S,
E);
1236 switch (getLexer().getKind()) {
1241 Operands.push_back(VEOperand::MorphToMEMzii(
1250 const MCExpr *IndexValue =
nullptr;
1253 switch (getLexer().getKind()) {
1255 if (parseRegister(IndexReg,
S,
E))
1262 if (getParser().parseExpression(IndexValue,
E))
1272 switch (getLexer().getKind()) {
1289 if (parseRegister(BaseReg,
S,
E))
1319 std::unique_ptr<VEOperand>
Offset;
1320 switch (getLexer().getKind()) {
1329 if (!parseExpression(EVal))
1330 Offset = VEOperand::CreateImm(EVal,
S,
E);
1337 if (parseRegister(BaseReg,
S,
E))
1350 switch (getLexer().getKind()) {
1356 Operands.push_back(BaseReg != VE::NoRegister
1362 if (BaseReg != VE::NoRegister)
1368 switch (getLexer().getKind()) {
1370 if (parseRegister(BaseReg,
S,
E))
1376 if (parseRegister(BaseReg,
S,
E))
1388 Operands.push_back(BaseReg != VE::NoRegister
1409 getLexer().UnLex(Tok1);
1415 getLexer().UnLex(Tok2);
1416 getLexer().UnLex(Tok1);
1423 if (Suffix !=
"1" && Suffix !=
"0") {
1424 getLexer().UnLex(Tok3);
1425 getLexer().UnLex(Tok2);
1426 getLexer().UnLex(Tok1);
1432 VEOperand::CreateMImm(EVal, Suffix ==
"0", Tok1.
getLoc(), EndLoc));
1447 switch (getLexer().getKind()) {
1456 getLexer().UnLex(Tok1);
1473 Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1));
1474 Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2));
1481 std::unique_ptr<VEOperand>
Op;
1482 ResTy = parseVEAsmOperand(
Op);
1493 std::unique_ptr<VEOperand> Op1 = VEOperand::CreateToken(
1497 std::unique_ptr<VEOperand> Op2;
1498 ResTy = parseVEAsmOperand(Op2);
1518 VEAsmParser::parseVEAsmOperand(std::unique_ptr<VEOperand> &
Op) {
1525 switch (getLexer().getKind()) {
1532 Op = VEOperand::CreateReg(RegNo,
S,
E);
1539 if (!parseExpression(EVal))
1540 Op = VEOperand::CreateImm(EVal,
S,
E);
1551 #define GET_REGISTER_MATCHER
1552 #define GET_MATCHER_IMPLEMENTATION
1553 #include "VEGenAsmMatcher.inc"
1557 VEOperand &
Op = (VEOperand &)GOp;
1566 if (
Op.isReg() && VEOperand::MorphToF32Reg(
Op))
1570 if (
Op.isReg() && VEOperand::MorphToI32Reg(
Op))
1574 if (
Op.isReg() && VEOperand::MorphToF128Reg(
Op))
1578 if (
Op.isReg() && VEOperand::MorphToVM512Reg(
Op))
1582 if (
Op.isImm() && VEOperand::MorphToMISCReg(
Op))
1586 return Match_InvalidOperand;