LLVM 18.0.0git
VEAsmParser.cpp
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1//===-- VEAsmParser.cpp - Parse VE assembly to MCInst instructions --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
12#include "VE.h"
13#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/StringRef.h"
16#include "llvm/ADT/Twine.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCExpr.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCStreamer.h"
28#include "llvm/MC/MCSymbol.h"
31#include <algorithm>
32#include <memory>
33
34using namespace llvm;
35
36#define DEBUG_TYPE "ve-asmparser"
37
38namespace {
39
40class VEOperand;
41
42class VEAsmParser : public MCTargetAsmParser {
43 MCAsmParser &Parser;
44
45 /// @name Auto-generated Match Functions
46 /// {
47
48#define GET_ASSEMBLER_HEADER
49#include "VEGenAsmMatcher.inc"
50
51 /// }
52
53 // public interface of the MCTargetAsmParser.
54 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
57 bool MatchingInlineAsm) override;
58 bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override;
59 int parseRegisterName(unsigned (*matchFn)(StringRef));
61 SMLoc &EndLoc) override;
63 SMLoc NameLoc, OperandVector &Operands) override;
64 ParseStatus parseDirective(AsmToken DirectiveID) override;
65
67 unsigned Kind) override;
68
69 // Custom parse functions for VE specific operands.
70 ParseStatus parseMEMOperand(OperandVector &Operands);
71 ParseStatus parseMEMAsOperand(OperandVector &Operands);
72 ParseStatus parseCCOpOperand(OperandVector &Operands);
73 ParseStatus parseRDOpOperand(OperandVector &Operands);
74 ParseStatus parseMImmOperand(OperandVector &Operands);
76 ParseStatus parseVEAsmOperand(std::unique_ptr<VEOperand> &Operand);
77
78 // Helper function to parse expression with a symbol.
79 const MCExpr *extractModifierFromExpr(const MCExpr *E,
80 VEMCExpr::VariantKind &Variant);
81 const MCExpr *fixupVariantKind(const MCExpr *E);
82 bool parseExpression(const MCExpr *&EVal);
83
84 // Split the mnemonic stripping conditional code and quantifiers
85 StringRef splitMnemonic(StringRef Name, SMLoc NameLoc,
87
88 bool parseLiteralValues(unsigned Size, SMLoc L);
89
90public:
91 VEAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
92 const MCInstrInfo &MII, const MCTargetOptions &Options)
93 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
94 // Initialize the set of available features.
95 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
96 }
97};
98
99} // end anonymous namespace
100
101static const MCPhysReg I32Regs[64] = {
102 VE::SW0, VE::SW1, VE::SW2, VE::SW3, VE::SW4, VE::SW5, VE::SW6,
103 VE::SW7, VE::SW8, VE::SW9, VE::SW10, VE::SW11, VE::SW12, VE::SW13,
104 VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
105 VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
106 VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
107 VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
108 VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
109 VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
110 VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
111 VE::SW63};
112
113static const MCPhysReg F32Regs[64] = {
114 VE::SF0, VE::SF1, VE::SF2, VE::SF3, VE::SF4, VE::SF5, VE::SF6,
115 VE::SF7, VE::SF8, VE::SF9, VE::SF10, VE::SF11, VE::SF12, VE::SF13,
116 VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
117 VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
118 VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
119 VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
120 VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
121 VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
122 VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
123 VE::SF63};
124
125static const MCPhysReg F128Regs[32] = {
126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
127 VE::Q8, VE::Q9, VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
128 VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
129 VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
130
131static const MCPhysReg VM512Regs[8] = {VE::VMP0, VE::VMP1, VE::VMP2, VE::VMP3,
132 VE::VMP4, VE::VMP5, VE::VMP6, VE::VMP7};
133
134static const MCPhysReg MISCRegs[31] = {
135 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
136 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
137 VE::PMCR0, VE::PMCR1, VE::PMCR2, VE::PMCR3,
138 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
139 VE::PMC0, VE::PMC1, VE::PMC2, VE::PMC3,
140 VE::PMC4, VE::PMC5, VE::PMC6, VE::PMC7,
141 VE::PMC8, VE::PMC9, VE::PMC10, VE::PMC11,
142 VE::PMC12, VE::PMC13, VE::PMC14};
143
144namespace {
145
146/// VEOperand - Instances of this class represent a parsed VE machine
147/// instruction.
148class VEOperand : public MCParsedAsmOperand {
149private:
150 enum KindTy {
151 k_Token,
152 k_Register,
153 k_Immediate,
154 // SX-Aurora ASX form is disp(index, base).
155 k_MemoryRegRegImm, // base=reg, index=reg, disp=imm
156 k_MemoryRegImmImm, // base=reg, index=imm, disp=imm
157 k_MemoryZeroRegImm, // base=0, index=reg, disp=imm
158 k_MemoryZeroImmImm, // base=0, index=imm, disp=imm
159 // SX-Aurora AS form is disp(base).
160 k_MemoryRegImm, // base=reg, disp=imm
161 k_MemoryZeroImm, // base=0, disp=imm
162 // Other special cases for Aurora VE
163 k_CCOp, // condition code
164 k_RDOp, // rounding mode
165 k_MImmOp, // Special immediate value of sequential bit stream of 0 or 1.
166 } Kind;
167
168 SMLoc StartLoc, EndLoc;
169
170 struct Token {
171 const char *Data;
172 unsigned Length;
173 };
174
175 struct RegOp {
176 unsigned RegNum;
177 };
178
179 struct ImmOp {
180 const MCExpr *Val;
181 };
182
183 struct MemOp {
184 unsigned Base;
185 unsigned IndexReg;
186 const MCExpr *Index;
187 const MCExpr *Offset;
188 };
189
190 struct CCOp {
191 unsigned CCVal;
192 };
193
194 struct RDOp {
195 unsigned RDVal;
196 };
197
198 struct MImmOp {
199 const MCExpr *Val;
200 bool M0Flag;
201 };
202
203 union {
204 struct Token Tok;
205 struct RegOp Reg;
206 struct ImmOp Imm;
207 struct MemOp Mem;
208 struct CCOp CC;
209 struct RDOp RD;
210 struct MImmOp MImm;
211 };
212
213public:
214 VEOperand(KindTy K) : Kind(K) {}
215
216 bool isToken() const override { return Kind == k_Token; }
217 bool isReg() const override { return Kind == k_Register; }
218 bool isImm() const override { return Kind == k_Immediate; }
219 bool isMem() const override {
220 return isMEMrri() || isMEMrii() || isMEMzri() || isMEMzii() || isMEMri() ||
221 isMEMzi();
222 }
223 bool isMEMrri() const { return Kind == k_MemoryRegRegImm; }
224 bool isMEMrii() const { return Kind == k_MemoryRegImmImm; }
225 bool isMEMzri() const { return Kind == k_MemoryZeroRegImm; }
226 bool isMEMzii() const { return Kind == k_MemoryZeroImmImm; }
227 bool isMEMri() const { return Kind == k_MemoryRegImm; }
228 bool isMEMzi() const { return Kind == k_MemoryZeroImm; }
229 bool isCCOp() const { return Kind == k_CCOp; }
230 bool isRDOp() const { return Kind == k_RDOp; }
231 bool isZero() {
232 if (!isImm())
233 return false;
234
235 // Constant case
236 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
237 int64_t Value = ConstExpr->getValue();
238 return Value == 0;
239 }
240 return false;
241 }
242 bool isUImm0to2() {
243 if (!isImm())
244 return false;
245
246 // Constant case
247 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
248 int64_t Value = ConstExpr->getValue();
249 return Value >= 0 && Value < 3;
250 }
251 return false;
252 }
253 bool isUImm1() {
254 if (!isImm())
255 return false;
256
257 // Constant case
258 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
259 int64_t Value = ConstExpr->getValue();
260 return isUInt<1>(Value);
261 }
262 return false;
263 }
264 bool isUImm2() {
265 if (!isImm())
266 return false;
267
268 // Constant case
269 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
270 int64_t Value = ConstExpr->getValue();
271 return isUInt<2>(Value);
272 }
273 return false;
274 }
275 bool isUImm3() {
276 if (!isImm())
277 return false;
278
279 // Constant case
280 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
281 int64_t Value = ConstExpr->getValue();
282 return isUInt<3>(Value);
283 }
284 return false;
285 }
286 bool isUImm4() {
287 if (!isImm())
288 return false;
289
290 // Constant case
291 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
292 int64_t Value = ConstExpr->getValue();
293 return isUInt<4>(Value);
294 }
295 return false;
296 }
297 bool isUImm6() {
298 if (!isImm())
299 return false;
300
301 // Constant case
302 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
303 int64_t Value = ConstExpr->getValue();
304 return isUInt<6>(Value);
305 }
306 return false;
307 }
308 bool isUImm7() {
309 if (!isImm())
310 return false;
311
312 // Constant case
313 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
314 int64_t Value = ConstExpr->getValue();
315 return isUInt<7>(Value);
316 }
317 return false;
318 }
319 bool isSImm7() {
320 if (!isImm())
321 return false;
322
323 // Constant case
324 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
325 int64_t Value = ConstExpr->getValue();
326 return isInt<7>(Value);
327 }
328 return false;
329 }
330 bool isMImm() const {
331 if (Kind != k_MImmOp)
332 return false;
333
334 // Constant case
335 if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(MImm.Val)) {
336 int64_t Value = ConstExpr->getValue();
337 return isUInt<6>(Value);
338 }
339 return false;
340 }
341
342 StringRef getToken() const {
343 assert(Kind == k_Token && "Invalid access!");
344 return StringRef(Tok.Data, Tok.Length);
345 }
346
347 unsigned getReg() const override {
348 assert((Kind == k_Register) && "Invalid access!");
349 return Reg.RegNum;
350 }
351
352 const MCExpr *getImm() const {
353 assert((Kind == k_Immediate) && "Invalid access!");
354 return Imm.Val;
355 }
356
357 unsigned getMemBase() const {
358 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
359 Kind == k_MemoryRegImm) &&
360 "Invalid access!");
361 return Mem.Base;
362 }
363
364 unsigned getMemIndexReg() const {
365 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryZeroRegImm) &&
366 "Invalid access!");
367 return Mem.IndexReg;
368 }
369
370 const MCExpr *getMemIndex() const {
371 assert((Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm) &&
372 "Invalid access!");
373 return Mem.Index;
374 }
375
376 const MCExpr *getMemOffset() const {
377 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
378 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||
379 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&
380 "Invalid access!");
381 return Mem.Offset;
382 }
383
384 void setMemOffset(const MCExpr *off) {
385 assert((Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm ||
386 Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ||
387 Kind == k_MemoryRegImm || Kind == k_MemoryZeroImm) &&
388 "Invalid access!");
389 Mem.Offset = off;
390 }
391
392 unsigned getCCVal() const {
393 assert((Kind == k_CCOp) && "Invalid access!");
394 return CC.CCVal;
395 }
396
397 unsigned getRDVal() const {
398 assert((Kind == k_RDOp) && "Invalid access!");
399 return RD.RDVal;
400 }
401
402 const MCExpr *getMImmVal() const {
403 assert((Kind == k_MImmOp) && "Invalid access!");
404 return MImm.Val;
405 }
406 bool getM0Flag() const {
407 assert((Kind == k_MImmOp) && "Invalid access!");
408 return MImm.M0Flag;
409 }
410
411 /// getStartLoc - Get the location of the first token of this operand.
412 SMLoc getStartLoc() const override { return StartLoc; }
413 /// getEndLoc - Get the location of the last token of this operand.
414 SMLoc getEndLoc() const override { return EndLoc; }
415
416 void print(raw_ostream &OS) const override {
417 switch (Kind) {
418 case k_Token:
419 OS << "Token: " << getToken() << "\n";
420 break;
421 case k_Register:
422 OS << "Reg: #" << getReg() << "\n";
423 break;
424 case k_Immediate:
425 OS << "Imm: " << getImm() << "\n";
426 break;
427 case k_MemoryRegRegImm:
428 assert(getMemOffset() != nullptr);
429 OS << "Mem: #" << getMemBase() << "+#" << getMemIndexReg() << "+"
430 << *getMemOffset() << "\n";
431 break;
432 case k_MemoryRegImmImm:
433 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
434 OS << "Mem: #" << getMemBase() << "+" << *getMemIndex() << "+"
435 << *getMemOffset() << "\n";
436 break;
437 case k_MemoryZeroRegImm:
438 assert(getMemOffset() != nullptr);
439 OS << "Mem: 0+#" << getMemIndexReg() << "+" << *getMemOffset() << "\n";
440 break;
441 case k_MemoryZeroImmImm:
442 assert(getMemIndex() != nullptr && getMemOffset() != nullptr);
443 OS << "Mem: 0+" << *getMemIndex() << "+" << *getMemOffset() << "\n";
444 break;
445 case k_MemoryRegImm:
446 assert(getMemOffset() != nullptr);
447 OS << "Mem: #" << getMemBase() << "+" << *getMemOffset() << "\n";
448 break;
449 case k_MemoryZeroImm:
450 assert(getMemOffset() != nullptr);
451 OS << "Mem: 0+" << *getMemOffset() << "\n";
452 break;
453 case k_CCOp:
454 OS << "CCOp: " << getCCVal() << "\n";
455 break;
456 case k_RDOp:
457 OS << "RDOp: " << getRDVal() << "\n";
458 break;
459 case k_MImmOp:
460 OS << "MImm: (" << getMImmVal() << (getM0Flag() ? ")0" : ")1") << "\n";
461 break;
462 }
463 }
464
465 void addRegOperands(MCInst &Inst, unsigned N) const {
466 assert(N == 1 && "Invalid number of operands!");
468 }
469
470 void addImmOperands(MCInst &Inst, unsigned N) const {
471 assert(N == 1 && "Invalid number of operands!");
472 const MCExpr *Expr = getImm();
473 addExpr(Inst, Expr);
474 }
475
476 void addZeroOperands(MCInst &Inst, unsigned N) const {
477 addImmOperands(Inst, N);
478 }
479
480 void addUImm0to2Operands(MCInst &Inst, unsigned N) const {
481 addImmOperands(Inst, N);
482 }
483
484 void addUImm1Operands(MCInst &Inst, unsigned N) const {
485 addImmOperands(Inst, N);
486 }
487
488 void addUImm2Operands(MCInst &Inst, unsigned N) const {
489 addImmOperands(Inst, N);
490 }
491
492 void addUImm3Operands(MCInst &Inst, unsigned N) const {
493 addImmOperands(Inst, N);
494 }
495
496 void addUImm4Operands(MCInst &Inst, unsigned N) const {
497 addImmOperands(Inst, N);
498 }
499
500 void addUImm6Operands(MCInst &Inst, unsigned N) const {
501 addImmOperands(Inst, N);
502 }
503
504 void addUImm7Operands(MCInst &Inst, unsigned N) const {
505 addImmOperands(Inst, N);
506 }
507
508 void addSImm7Operands(MCInst &Inst, unsigned N) const {
509 addImmOperands(Inst, N);
510 }
511
512 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
513 // Add as immediate when possible. Null MCExpr = 0.
514 if (!Expr)
516 else if (const auto *CE = dyn_cast<MCConstantExpr>(Expr))
517 Inst.addOperand(MCOperand::createImm(CE->getValue()));
518 else
520 }
521
522 void addMEMrriOperands(MCInst &Inst, unsigned N) const {
523 assert(N == 3 && "Invalid number of operands!");
524
525 Inst.addOperand(MCOperand::createReg(getMemBase()));
526 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
527 addExpr(Inst, getMemOffset());
528 }
529
530 void addMEMriiOperands(MCInst &Inst, unsigned N) const {
531 assert(N == 3 && "Invalid number of operands!");
532
533 Inst.addOperand(MCOperand::createReg(getMemBase()));
534 addExpr(Inst, getMemIndex());
535 addExpr(Inst, getMemOffset());
536 }
537
538 void addMEMzriOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 3 && "Invalid number of operands!");
540
542 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
543 addExpr(Inst, getMemOffset());
544 }
545
546 void addMEMziiOperands(MCInst &Inst, unsigned N) const {
547 assert(N == 3 && "Invalid number of operands!");
548
550 addExpr(Inst, getMemIndex());
551 addExpr(Inst, getMemOffset());
552 }
553
554 void addMEMriOperands(MCInst &Inst, unsigned N) const {
555 assert(N == 2 && "Invalid number of operands!");
556
557 Inst.addOperand(MCOperand::createReg(getMemBase()));
558 addExpr(Inst, getMemOffset());
559 }
560
561 void addMEMziOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 2 && "Invalid number of operands!");
563
565 addExpr(Inst, getMemOffset());
566 }
567
568 void addCCOpOperands(MCInst &Inst, unsigned N) const {
569 assert(N == 1 && "Invalid number of operands!");
570
571 Inst.addOperand(MCOperand::createImm(getCCVal()));
572 }
573
574 void addRDOpOperands(MCInst &Inst, unsigned N) const {
575 assert(N == 1 && "Invalid number of operands!");
576
577 Inst.addOperand(MCOperand::createImm(getRDVal()));
578 }
579
580 void addMImmOperands(MCInst &Inst, unsigned N) const {
581 assert(N == 1 && "Invalid number of operands!");
582 const auto *ConstExpr = dyn_cast<MCConstantExpr>(getMImmVal());
583 assert(ConstExpr && "Null operands!");
584 int64_t Value = ConstExpr->getValue();
585 if (getM0Flag())
586 Value += 64;
588 }
589
590 static std::unique_ptr<VEOperand> CreateToken(StringRef Str, SMLoc S) {
591 auto Op = std::make_unique<VEOperand>(k_Token);
592 Op->Tok.Data = Str.data();
593 Op->Tok.Length = Str.size();
594 Op->StartLoc = S;
595 Op->EndLoc = S;
596 return Op;
597 }
598
599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S,
600 SMLoc E) {
601 auto Op = std::make_unique<VEOperand>(k_Register);
602 Op->Reg.RegNum = RegNum;
603 Op->StartLoc = S;
604 Op->EndLoc = E;
605 return Op;
606 }
607
608 static std::unique_ptr<VEOperand> CreateImm(const MCExpr *Val, SMLoc S,
609 SMLoc E) {
610 auto Op = std::make_unique<VEOperand>(k_Immediate);
611 Op->Imm.Val = Val;
612 Op->StartLoc = S;
613 Op->EndLoc = E;
614 return Op;
615 }
616
617 static std::unique_ptr<VEOperand> CreateCCOp(unsigned CCVal, SMLoc S,
618 SMLoc E) {
619 auto Op = std::make_unique<VEOperand>(k_CCOp);
620 Op->CC.CCVal = CCVal;
621 Op->StartLoc = S;
622 Op->EndLoc = E;
623 return Op;
624 }
625
626 static std::unique_ptr<VEOperand> CreateRDOp(unsigned RDVal, SMLoc S,
627 SMLoc E) {
628 auto Op = std::make_unique<VEOperand>(k_RDOp);
629 Op->RD.RDVal = RDVal;
630 Op->StartLoc = S;
631 Op->EndLoc = E;
632 return Op;
633 }
634
635 static std::unique_ptr<VEOperand> CreateMImm(const MCExpr *Val, bool Flag,
636 SMLoc S, SMLoc E) {
637 auto Op = std::make_unique<VEOperand>(k_MImmOp);
638 Op->MImm.Val = Val;
639 Op->MImm.M0Flag = Flag;
640 Op->StartLoc = S;
641 Op->EndLoc = E;
642 return Op;
643 }
644
645 static bool MorphToI32Reg(VEOperand &Op) {
646 unsigned Reg = Op.getReg();
647 unsigned regIdx = Reg - VE::SX0;
648 if (regIdx > 63)
649 return false;
650 Op.Reg.RegNum = I32Regs[regIdx];
651 return true;
652 }
653
654 static bool MorphToF32Reg(VEOperand &Op) {
655 unsigned Reg = Op.getReg();
656 unsigned regIdx = Reg - VE::SX0;
657 if (regIdx > 63)
658 return false;
659 Op.Reg.RegNum = F32Regs[regIdx];
660 return true;
661 }
662
663 static bool MorphToF128Reg(VEOperand &Op) {
664 unsigned Reg = Op.getReg();
665 unsigned regIdx = Reg - VE::SX0;
666 if (regIdx % 2 || regIdx > 63)
667 return false;
668 Op.Reg.RegNum = F128Regs[regIdx / 2];
669 return true;
670 }
671
672 static bool MorphToVM512Reg(VEOperand &Op) {
673 unsigned Reg = Op.getReg();
674 unsigned regIdx = Reg - VE::VM0;
675 if (regIdx % 2 || regIdx > 15)
676 return false;
677 Op.Reg.RegNum = VM512Regs[regIdx / 2];
678 return true;
679 }
680
681 static bool MorphToMISCReg(VEOperand &Op) {
682 const auto *ConstExpr = dyn_cast<MCConstantExpr>(Op.getImm());
683 if (!ConstExpr)
684 return false;
685 unsigned regIdx = ConstExpr->getValue();
686 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
687 return false;
688 Op.Kind = k_Register;
689 Op.Reg.RegNum = MISCRegs[regIdx];
690 return true;
691 }
692
693 static std::unique_ptr<VEOperand>
694 MorphToMEMri(unsigned Base, std::unique_ptr<VEOperand> Op) {
695 const MCExpr *Imm = Op->getImm();
696 Op->Kind = k_MemoryRegImm;
697 Op->Mem.Base = Base;
698 Op->Mem.IndexReg = 0;
699 Op->Mem.Index = nullptr;
700 Op->Mem.Offset = Imm;
701 return Op;
702 }
703
704 static std::unique_ptr<VEOperand>
705 MorphToMEMzi(std::unique_ptr<VEOperand> Op) {
706 const MCExpr *Imm = Op->getImm();
707 Op->Kind = k_MemoryZeroImm;
708 Op->Mem.Base = 0;
709 Op->Mem.IndexReg = 0;
710 Op->Mem.Index = nullptr;
711 Op->Mem.Offset = Imm;
712 return Op;
713 }
714
715 static std::unique_ptr<VEOperand>
716 MorphToMEMrri(unsigned Base, unsigned Index, std::unique_ptr<VEOperand> Op) {
717 const MCExpr *Imm = Op->getImm();
718 Op->Kind = k_MemoryRegRegImm;
719 Op->Mem.Base = Base;
720 Op->Mem.IndexReg = Index;
721 Op->Mem.Index = nullptr;
722 Op->Mem.Offset = Imm;
723 return Op;
724 }
725
726 static std::unique_ptr<VEOperand>
727 MorphToMEMrii(unsigned Base, const MCExpr *Index,
728 std::unique_ptr<VEOperand> Op) {
729 const MCExpr *Imm = Op->getImm();
730 Op->Kind = k_MemoryRegImmImm;
731 Op->Mem.Base = Base;
732 Op->Mem.IndexReg = 0;
733 Op->Mem.Index = Index;
734 Op->Mem.Offset = Imm;
735 return Op;
736 }
737
738 static std::unique_ptr<VEOperand>
739 MorphToMEMzri(unsigned Index, std::unique_ptr<VEOperand> Op) {
740 const MCExpr *Imm = Op->getImm();
741 Op->Kind = k_MemoryZeroRegImm;
742 Op->Mem.Base = 0;
743 Op->Mem.IndexReg = Index;
744 Op->Mem.Index = nullptr;
745 Op->Mem.Offset = Imm;
746 return Op;
747 }
748
749 static std::unique_ptr<VEOperand>
750 MorphToMEMzii(const MCExpr *Index, std::unique_ptr<VEOperand> Op) {
751 const MCExpr *Imm = Op->getImm();
752 Op->Kind = k_MemoryZeroImmImm;
753 Op->Mem.Base = 0;
754 Op->Mem.IndexReg = 0;
755 Op->Mem.Index = Index;
756 Op->Mem.Offset = Imm;
757 return Op;
758 }
759};
760
761} // end anonymous namespace
762
763bool VEAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
766 bool MatchingInlineAsm) {
767 MCInst Inst;
768 unsigned MatchResult =
769 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
770 switch (MatchResult) {
771 case Match_Success:
772 Inst.setLoc(IDLoc);
773 Out.emitInstruction(Inst, getSTI());
774 return false;
775
776 case Match_MissingFeature:
777 return Error(IDLoc,
778 "instruction requires a CPU feature not currently enabled");
779
780 case Match_InvalidOperand: {
781 SMLoc ErrorLoc = IDLoc;
782 if (ErrorInfo != ~0ULL) {
783 if (ErrorInfo >= Operands.size())
784 return Error(IDLoc, "too few operands for instruction");
785
786 ErrorLoc = ((VEOperand &)*Operands[ErrorInfo]).getStartLoc();
787 if (ErrorLoc == SMLoc())
788 ErrorLoc = IDLoc;
789 }
790
791 return Error(ErrorLoc, "invalid operand for instruction");
792 }
793 case Match_MnemonicFail:
794 return Error(IDLoc, "invalid instruction mnemonic");
795 }
796 llvm_unreachable("Implement any new match types added!");
797}
798
799bool VEAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
800 SMLoc &EndLoc) {
801 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
802 return Error(StartLoc, "invalid register name");
803 return false;
804}
805
806/// Parses a register name using a given matching function.
807/// Checks for lowercase or uppercase if necessary.
808int VEAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
809 StringRef Name = Parser.getTok().getString();
810
811 int RegNum = matchFn(Name);
812
813 // GCC supports case insensitive register names. All of the VE registers
814 // are all lower case.
815 if (RegNum == VE::NoRegister) {
816 RegNum = matchFn(Name.lower());
817 }
818
819 return RegNum;
820}
821
822/// Maps from the set of all register names to a register number.
823/// \note Generated by TableGen.
825
826/// Maps from the set of all alternative registernames to a register number.
827/// \note Generated by TableGen.
829
830ParseStatus VEAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
831 SMLoc &EndLoc) {
832 const AsmToken Tok = Parser.getTok();
833 StartLoc = Tok.getLoc();
834 EndLoc = Tok.getEndLoc();
835 Reg = VE::NoRegister;
836 if (getLexer().getKind() != AsmToken::Percent)
838 Parser.Lex();
839
840 Reg = parseRegisterName(&MatchRegisterName);
841 if (Reg == VE::NoRegister)
842 Reg = parseRegisterName(&MatchRegisterAltName);
843
844 if (Reg != VE::NoRegister) {
845 Parser.Lex();
847 }
848
849 getLexer().UnLex(Tok);
851}
852
853static StringRef parseCC(StringRef Name, unsigned Prefix, unsigned Suffix,
854 bool IntegerCC, bool OmitCC, SMLoc NameLoc,
856 // Parse instructions with a conditional code. For example, 'bne' is
857 // converted into two operands 'b' and 'ne'.
858 StringRef Cond = Name.slice(Prefix, Suffix);
859 VECC::CondCode CondCode =
861
862 // If OmitCC is enabled, CC_AT and CC_AF is treated as a part of mnemonic.
863 if (CondCode != VECC::UNKNOWN &&
864 (!OmitCC || (CondCode != VECC::CC_AT && CondCode != VECC::CC_AF))) {
865 StringRef SuffixStr = Name.substr(Suffix);
866 // Push "b".
867 Name = Name.slice(0, Prefix);
868 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
869 // Push $cond part.
870 SMLoc CondLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Prefix);
871 SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Suffix);
872 Operands->push_back(VEOperand::CreateCCOp(CondCode, CondLoc, SuffixLoc));
873 // push suffix like ".l.t"
874 if (!SuffixStr.empty())
875 Operands->push_back(VEOperand::CreateToken(SuffixStr, SuffixLoc));
876 } else {
877 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
878 }
879 return Name;
880}
881
882static StringRef parseRD(StringRef Name, unsigned Prefix, SMLoc NameLoc,
884 // Parse instructions with a conditional code. For example, 'cvt.w.d.sx.rz'
885 // is converted into two operands 'cvt.w.d.sx' and '.rz'.
886 StringRef RD = Name.substr(Prefix);
888
890 Name = Name.slice(0, Prefix);
891 // push 1st like `cvt.w.d.sx`
892 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
893 SMLoc SuffixLoc =
894 SMLoc::getFromPointer(NameLoc.getPointer() + (RD.data() - Name.data()));
896 SMLoc::getFromPointer(NameLoc.getPointer() + (RD.end() - Name.data()));
897 // push $round if it has rounding mode
898 Operands->push_back(
899 VEOperand::CreateRDOp(RoundingMode, SuffixLoc, SuffixEnd));
900 } else {
901 Operands->push_back(VEOperand::CreateToken(Name, NameLoc));
902 }
903 return Name;
904}
905
906// Split the mnemonic into ASM operand, conditional code and instruction
907// qualifier (half-word, byte).
908StringRef VEAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,
910 // Create the leading tokens for the mnemonic
911 StringRef Mnemonic = Name;
912
913 if (Name[0] == 'b') {
914 // Match b?? or br??.
915 size_t Start = 1;
916 size_t Next = Name.find('.');
917 // Adjust position of CondCode.
918 if (Name.size() > 1 && Name[1] == 'r')
919 Start = 2;
920 // Check suffix.
921 bool ICC = true;
922 if (Next + 1 < Name.size() &&
923 (Name[Next + 1] == 'd' || Name[Next + 1] == 's'))
924 ICC = false;
925 Mnemonic = parseCC(Name, Start, Next, ICC, true, NameLoc, Operands);
926 } else if (Name.startswith("cmov.l.") || Name.startswith("cmov.w.") ||
927 Name.startswith("cmov.d.") || Name.startswith("cmov.s.")) {
928 bool ICC = Name[5] == 'l' || Name[5] == 'w';
929 Mnemonic = parseCC(Name, 7, Name.size(), ICC, false, NameLoc, Operands);
930 } else if (Name.startswith("cvt.w.d.sx") || Name.startswith("cvt.w.d.zx") ||
931 Name.startswith("cvt.w.s.sx") || Name.startswith("cvt.w.s.zx")) {
932 Mnemonic = parseRD(Name, 10, NameLoc, Operands);
933 } else if (Name.startswith("cvt.l.d")) {
934 Mnemonic = parseRD(Name, 7, NameLoc, Operands);
935 } else if (Name.startswith("vcvt.w.d.sx") || Name.startswith("vcvt.w.d.zx") ||
936 Name.startswith("vcvt.w.s.sx") || Name.startswith("vcvt.w.s.zx")) {
937 Mnemonic = parseRD(Name, 11, NameLoc, Operands);
938 } else if (Name.startswith("vcvt.l.d")) {
939 Mnemonic = parseRD(Name, 8, NameLoc, Operands);
940 } else if (Name.startswith("pvcvt.w.s.lo") ||
941 Name.startswith("pvcvt.w.s.up")) {
942 Mnemonic = parseRD(Name, 12, NameLoc, Operands);
943 } else if (Name.startswith("pvcvt.w.s")) {
944 Mnemonic = parseRD(Name, 9, NameLoc, Operands);
945 } else if (Name.startswith("vfmk.l.") || Name.startswith("vfmk.w.") ||
946 Name.startswith("vfmk.d.") || Name.startswith("vfmk.s.")) {
947 bool ICC = Name[5] == 'l' || Name[5] == 'w' ? true : false;
948 Mnemonic = parseCC(Name, 7, Name.size(), ICC, true, NameLoc, Operands);
949 } else if (Name.startswith("pvfmk.w.lo.") || Name.startswith("pvfmk.w.up.") ||
950 Name.startswith("pvfmk.s.lo.") || Name.startswith("pvfmk.s.up.")) {
951 bool ICC = Name[6] == 'l' || Name[6] == 'w' ? true : false;
952 Mnemonic = parseCC(Name, 11, Name.size(), ICC, true, NameLoc, Operands);
953 } else {
954 Operands->push_back(VEOperand::CreateToken(Mnemonic, NameLoc));
955 }
956
957 return Mnemonic;
958}
959
960static void applyMnemonicAliases(StringRef &Mnemonic,
961 const FeatureBitset &Features,
962 unsigned VariantID);
963
964bool VEAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
965 SMLoc NameLoc, OperandVector &Operands) {
966 // If the target architecture uses MnemonicAlias, call it here to parse
967 // operands correctly.
968 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
969
970 // Split name to first token and the rest, e.g. "bgt.l.t" to "b", "gt", and
971 // ".l.t". We treat "b" as a mnemonic, "gt" as first operand, and ".l.t"
972 // as second operand.
973 StringRef Mnemonic = splitMnemonic(Name, NameLoc, &Operands);
974
975 if (getLexer().isNot(AsmToken::EndOfStatement)) {
976 // Read the first operand.
977 if (!parseOperand(Operands, Mnemonic).isSuccess()) {
978 SMLoc Loc = getLexer().getLoc();
979 return Error(Loc, "unexpected token");
980 }
981
982 while (getLexer().is(AsmToken::Comma)) {
983 Parser.Lex(); // Eat the comma.
984 // Parse and remember the operand.
985 if (!parseOperand(Operands, Mnemonic).isSuccess()) {
986 SMLoc Loc = getLexer().getLoc();
987 return Error(Loc, "unexpected token");
988 }
989 }
990 }
991 if (getLexer().isNot(AsmToken::EndOfStatement)) {
992 SMLoc Loc = getLexer().getLoc();
993 return Error(Loc, "unexpected token");
994 }
995 Parser.Lex(); // Consume the EndOfStatement.
996 return false;
997}
998
999ParseStatus VEAsmParser::parseDirective(AsmToken DirectiveID) {
1000 std::string IDVal = DirectiveID.getIdentifier().lower();
1001
1002 // Defines VE specific directives. Reference is "Vector Engine Assembly
1003 // Language Reference Manual":
1004 // https://www.hpc.nec/documents/sdk/pdfs/VectorEngine-as-manual-v1.3.pdf
1005
1006 // The .word is 4 bytes long on VE.
1007 if (IDVal == ".word")
1008 return parseLiteralValues(4, DirectiveID.getLoc());
1009
1010 // The .long is 8 bytes long on VE.
1011 if (IDVal == ".long")
1012 return parseLiteralValues(8, DirectiveID.getLoc());
1013
1014 // The .llong is 8 bytes long on VE.
1015 if (IDVal == ".llong")
1016 return parseLiteralValues(8, DirectiveID.getLoc());
1017
1018 // Let the MC layer to handle other directives.
1019 return ParseStatus::NoMatch;
1020}
1021
1022/// parseLiteralValues
1023/// ::= .word expression [, expression]*
1024/// ::= .long expression [, expression]*
1025/// ::= .llong expression [, expression]*
1026bool VEAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
1027 auto parseOne = [&]() -> bool {
1028 const MCExpr *Value;
1029 if (getParser().parseExpression(Value))
1030 return true;
1031 getParser().getStreamer().emitValue(Value, Size, L);
1032 return false;
1033 };
1034 return (parseMany(parseOne));
1035}
1036
1037/// Extract \code @lo32/@hi32/etc \endcode modifier from expression.
1038/// Recursively scan the expression and check for VK_VE_HI32/LO32/etc
1039/// symbol variants. If all symbols with modifier use the same
1040/// variant, return the corresponding VEMCExpr::VariantKind,
1041/// and a modified expression using the default symbol variant.
1042/// Otherwise, return NULL.
1043const MCExpr *
1044VEAsmParser::extractModifierFromExpr(const MCExpr *E,
1045 VEMCExpr::VariantKind &Variant) {
1046 MCContext &Context = getParser().getContext();
1048
1049 switch (E->getKind()) {
1050 case MCExpr::Target:
1051 case MCExpr::Constant:
1052 return nullptr;
1053
1054 case MCExpr::SymbolRef: {
1055 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1056
1057 switch (SRE->getKind()) {
1059 // Use VK_VE_REFLONG to a symbol without modifiers.
1061 break;
1064 break;
1067 break;
1070 break;
1073 break;
1076 break;
1079 break;
1082 break;
1085 break;
1088 break;
1091 break;
1094 break;
1097 break;
1100 break;
1103 break;
1104 default:
1105 return nullptr;
1106 }
1107
1108 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1109 }
1110
1111 case MCExpr::Unary: {
1112 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1113 const MCExpr *Sub = extractModifierFromExpr(UE->getSubExpr(), Variant);
1114 if (!Sub)
1115 return nullptr;
1116 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1117 }
1118
1119 case MCExpr::Binary: {
1120 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1121 VEMCExpr::VariantKind LHSVariant, RHSVariant;
1122 const MCExpr *LHS = extractModifierFromExpr(BE->getLHS(), LHSVariant);
1123 const MCExpr *RHS = extractModifierFromExpr(BE->getRHS(), RHSVariant);
1124
1125 if (!LHS && !RHS)
1126 return nullptr;
1127
1128 if (!LHS)
1129 LHS = BE->getLHS();
1130 if (!RHS)
1131 RHS = BE->getRHS();
1132
1133 if (LHSVariant == VEMCExpr::VK_VE_None)
1134 Variant = RHSVariant;
1135 else if (RHSVariant == VEMCExpr::VK_VE_None)
1136 Variant = LHSVariant;
1137 else if (LHSVariant == RHSVariant)
1138 Variant = LHSVariant;
1139 else
1140 return nullptr;
1141
1142 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1143 }
1144 }
1145
1146 llvm_unreachable("Invalid expression kind!");
1147}
1148
1149const MCExpr *VEAsmParser::fixupVariantKind(const MCExpr *E) {
1150 MCContext &Context = getParser().getContext();
1151
1152 switch (E->getKind()) {
1153 case MCExpr::Target:
1154 case MCExpr::Constant:
1155 case MCExpr::SymbolRef:
1156 return E;
1157
1158 case MCExpr::Unary: {
1159 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1160 const MCExpr *Sub = fixupVariantKind(UE->getSubExpr());
1161 if (Sub == UE->getSubExpr())
1162 return E;
1163 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1164 }
1165
1166 case MCExpr::Binary: {
1167 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1168 const MCExpr *LHS = fixupVariantKind(BE->getLHS());
1169 const MCExpr *RHS = fixupVariantKind(BE->getRHS());
1170 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1171 return E;
1172 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1173 }
1174 }
1175
1176 llvm_unreachable("Invalid expression kind!");
1177}
1178
1179/// ParseExpression. This differs from the default "parseExpression" in that
1180/// it handles modifiers.
1181bool VEAsmParser::parseExpression(const MCExpr *&EVal) {
1182 // Handle \code symbol @lo32/@hi32/etc \endcode.
1183 if (getParser().parseExpression(EVal))
1184 return true;
1185
1186 // Convert MCSymbolRefExpr with VK_* to MCExpr with VK_*.
1187 EVal = fixupVariantKind(EVal);
1189 const MCExpr *E = extractModifierFromExpr(EVal, Variant);
1190 if (E)
1191 EVal = VEMCExpr::create(Variant, E, getParser().getContext());
1192
1193 return false;
1194}
1195
1196ParseStatus VEAsmParser::parseMEMOperand(OperandVector &Operands) {
1197 LLVM_DEBUG(dbgs() << "parseMEMOperand\n");
1198 const AsmToken &Tok = Parser.getTok();
1199 SMLoc S = Tok.getLoc();
1200 SMLoc E = Tok.getEndLoc();
1201 // Parse ASX format
1202 // disp
1203 // disp(, base)
1204 // disp(index)
1205 // disp(index, base)
1206 // (, base)
1207 // (index)
1208 // (index, base)
1209
1210 std::unique_ptr<VEOperand> Offset;
1211 switch (getLexer().getKind()) {
1212 default:
1213 return ParseStatus::NoMatch;
1214
1215 case AsmToken::Minus:
1216 case AsmToken::Integer:
1217 case AsmToken::Dot:
1218 case AsmToken::Identifier: {
1219 const MCExpr *EVal;
1220 if (!parseExpression(EVal))
1221 Offset = VEOperand::CreateImm(EVal, S, E);
1222 else
1223 return ParseStatus::NoMatch;
1224 break;
1225 }
1226
1227 case AsmToken::LParen:
1228 // empty disp (= 0)
1229 Offset =
1230 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);
1231 break;
1232 }
1233
1234 switch (getLexer().getKind()) {
1235 default:
1236 return ParseStatus::Failure;
1237
1239 Operands.push_back(VEOperand::MorphToMEMzii(
1240 MCConstantExpr::create(0, getContext()), std::move(Offset)));
1241 return ParseStatus::Success;
1242
1243 case AsmToken::LParen:
1244 Parser.Lex(); // Eat the (
1245 break;
1246 }
1247
1248 const MCExpr *IndexValue = nullptr;
1249 MCRegister IndexReg;
1250
1251 switch (getLexer().getKind()) {
1252 default:
1253 if (parseRegister(IndexReg, S, E))
1254 return ParseStatus::Failure;
1255 break;
1256
1257 case AsmToken::Minus:
1258 case AsmToken::Integer:
1259 case AsmToken::Dot:
1260 if (getParser().parseExpression(IndexValue, E))
1261 return ParseStatus::Failure;
1262 break;
1263
1264 case AsmToken::Comma:
1265 // empty index
1266 IndexValue = MCConstantExpr::create(0, getContext());
1267 break;
1268 }
1269
1270 switch (getLexer().getKind()) {
1271 default:
1272 return ParseStatus::Failure;
1273
1274 case AsmToken::RParen:
1275 Parser.Lex(); // Eat the )
1276 Operands.push_back(
1277 IndexValue ? VEOperand::MorphToMEMzii(IndexValue, std::move(Offset))
1278 : VEOperand::MorphToMEMzri(IndexReg, std::move(Offset)));
1279 return ParseStatus::Success;
1280
1281 case AsmToken::Comma:
1282 Parser.Lex(); // Eat the ,
1283 break;
1284 }
1285
1286 MCRegister BaseReg;
1287 if (parseRegister(BaseReg, S, E))
1288 return ParseStatus::Failure;
1289
1290 if (!Parser.getTok().is(AsmToken::RParen))
1291 return ParseStatus::Failure;
1292
1293 Parser.Lex(); // Eat the )
1294 Operands.push_back(
1295 IndexValue
1296 ? VEOperand::MorphToMEMrii(BaseReg, IndexValue, std::move(Offset))
1297 : VEOperand::MorphToMEMrri(BaseReg, IndexReg, std::move(Offset)));
1298
1299 return ParseStatus::Success;
1300}
1301
1302ParseStatus VEAsmParser::parseMEMAsOperand(OperandVector &Operands) {
1303 LLVM_DEBUG(dbgs() << "parseMEMAsOperand\n");
1304 const AsmToken &Tok = Parser.getTok();
1305 SMLoc S = Tok.getLoc();
1306 SMLoc E = Tok.getEndLoc();
1307 // Parse AS format
1308 // disp
1309 // disp(, base)
1310 // disp(base)
1311 // disp()
1312 // (, base)
1313 // (base)
1314 // base
1315
1316 MCRegister BaseReg;
1317 std::unique_ptr<VEOperand> Offset;
1318 switch (getLexer().getKind()) {
1319 default:
1320 return ParseStatus::NoMatch;
1321
1322 case AsmToken::Minus:
1323 case AsmToken::Integer:
1324 case AsmToken::Dot:
1325 case AsmToken::Identifier: {
1326 const MCExpr *EVal;
1327 if (!parseExpression(EVal))
1328 Offset = VEOperand::CreateImm(EVal, S, E);
1329 else
1330 return ParseStatus::NoMatch;
1331 break;
1332 }
1333
1334 case AsmToken::Percent:
1335 if (parseRegister(BaseReg, S, E))
1336 return ParseStatus::NoMatch;
1337 Offset =
1338 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);
1339 break;
1340
1341 case AsmToken::LParen:
1342 // empty disp (= 0)
1343 Offset =
1344 VEOperand::CreateImm(MCConstantExpr::create(0, getContext()), S, E);
1345 break;
1346 }
1347
1348 switch (getLexer().getKind()) {
1349 default:
1350 return ParseStatus::Failure;
1351
1353 case AsmToken::Comma:
1354 Operands.push_back(BaseReg != VE::NoRegister
1355 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))
1356 : VEOperand::MorphToMEMzi(std::move(Offset)));
1357 return ParseStatus::Success;
1358
1359 case AsmToken::LParen:
1360 if (BaseReg != VE::NoRegister)
1361 return ParseStatus::Failure;
1362 Parser.Lex(); // Eat the (
1363 break;
1364 }
1365
1366 switch (getLexer().getKind()) {
1367 default:
1368 if (parseRegister(BaseReg, S, E))
1369 return ParseStatus::Failure;
1370 break;
1371
1372 case AsmToken::Comma:
1373 Parser.Lex(); // Eat the ,
1374 if (parseRegister(BaseReg, S, E))
1375 return ParseStatus::Failure;
1376 break;
1377
1378 case AsmToken::RParen:
1379 break;
1380 }
1381
1382 if (!Parser.getTok().is(AsmToken::RParen))
1383 return ParseStatus::Failure;
1384
1385 Parser.Lex(); // Eat the )
1386 Operands.push_back(BaseReg != VE::NoRegister
1387 ? VEOperand::MorphToMEMri(BaseReg, std::move(Offset))
1388 : VEOperand::MorphToMEMzi(std::move(Offset)));
1389
1390 return ParseStatus::Success;
1391}
1392
1393ParseStatus VEAsmParser::parseMImmOperand(OperandVector &Operands) {
1394 LLVM_DEBUG(dbgs() << "parseMImmOperand\n");
1395
1396 // Parsing "(" + number + ")0/1"
1397 const AsmToken Tok1 = Parser.getTok();
1398 if (!Tok1.is(AsmToken::LParen))
1399 return ParseStatus::NoMatch;
1400
1401 Parser.Lex(); // Eat the '('.
1402
1403 const AsmToken Tok2 = Parser.getTok();
1404 SMLoc E;
1405 const MCExpr *EVal;
1406 if (!Tok2.is(AsmToken::Integer) || getParser().parseExpression(EVal, E)) {
1407 getLexer().UnLex(Tok1);
1408 return ParseStatus::NoMatch;
1409 }
1410
1411 const AsmToken Tok3 = Parser.getTok();
1412 if (!Tok3.is(AsmToken::RParen)) {
1413 getLexer().UnLex(Tok2);
1414 getLexer().UnLex(Tok1);
1415 return ParseStatus::NoMatch;
1416 }
1417 Parser.Lex(); // Eat the ')'.
1418
1419 const AsmToken &Tok4 = Parser.getTok();
1420 StringRef Suffix = Tok4.getString();
1421 if (Suffix != "1" && Suffix != "0") {
1422 getLexer().UnLex(Tok3);
1423 getLexer().UnLex(Tok2);
1424 getLexer().UnLex(Tok1);
1425 return ParseStatus::NoMatch;
1426 }
1427 Parser.Lex(); // Eat the value.
1428 SMLoc EndLoc = SMLoc::getFromPointer(Suffix.end());
1429 Operands.push_back(
1430 VEOperand::CreateMImm(EVal, Suffix == "0", Tok1.getLoc(), EndLoc));
1431 return ParseStatus::Success;
1432}
1433
1434ParseStatus VEAsmParser::parseOperand(OperandVector &Operands,
1435 StringRef Mnemonic) {
1436 LLVM_DEBUG(dbgs() << "parseOperand\n");
1437 ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);
1438
1439 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1440 // there was a match, but an error occurred, in which case, just return that
1441 // the operand parsing failed.
1442 if (Res.isSuccess() || Res.isFailure())
1443 return Res;
1444
1445 switch (getLexer().getKind()) {
1446 case AsmToken::LParen: {
1447 // Parsing "(" + %vreg + ", " + %vreg + ")"
1448 const AsmToken Tok1 = Parser.getTok();
1449 Parser.Lex(); // Eat the '('.
1450
1451 MCRegister Reg1;
1452 SMLoc S1, E1;
1453 if (!tryParseRegister(Reg1, S1, E1).isSuccess()) {
1454 getLexer().UnLex(Tok1);
1455 return ParseStatus::NoMatch;
1456 }
1457
1458 if (!Parser.getTok().is(AsmToken::Comma))
1459 return ParseStatus::Failure;
1460 Parser.Lex(); // Eat the ','.
1461
1462 MCRegister Reg2;
1463 SMLoc S2, E2;
1464 if (!tryParseRegister(Reg2, S2, E2).isSuccess())
1465 return ParseStatus::Failure;
1466
1467 if (!Parser.getTok().is(AsmToken::RParen))
1468 return ParseStatus::Failure;
1469
1470 Operands.push_back(VEOperand::CreateToken(Tok1.getString(), Tok1.getLoc()));
1471 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1));
1472 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2));
1473 Operands.push_back(VEOperand::CreateToken(Parser.getTok().getString(),
1474 Parser.getTok().getLoc()));
1475 Parser.Lex(); // Eat the ')'.
1476 break;
1477 }
1478 default: {
1479 std::unique_ptr<VEOperand> Op;
1480 Res = parseVEAsmOperand(Op);
1481 if (!Res.isSuccess() || !Op)
1482 return ParseStatus::Failure;
1483
1484 // Push the parsed operand into the list of operands
1485 Operands.push_back(std::move(Op));
1486
1487 if (!Parser.getTok().is(AsmToken::LParen))
1488 break;
1489
1490 // Parsing %vec-reg + "(" + %sclar-reg/number + ")"
1491 std::unique_ptr<VEOperand> Op1 = VEOperand::CreateToken(
1492 Parser.getTok().getString(), Parser.getTok().getLoc());
1493 Parser.Lex(); // Eat the '('.
1494
1495 std::unique_ptr<VEOperand> Op2;
1496 Res = parseVEAsmOperand(Op2);
1497 if (!Res.isSuccess() || !Op2)
1498 return ParseStatus::Failure;
1499
1500 if (!Parser.getTok().is(AsmToken::RParen))
1501 return ParseStatus::Failure;
1502
1503 Operands.push_back(std::move(Op1));
1504 Operands.push_back(std::move(Op2));
1505 Operands.push_back(VEOperand::CreateToken(Parser.getTok().getString(),
1506 Parser.getTok().getLoc()));
1507 Parser.Lex(); // Eat the ')'.
1508 break;
1509 }
1510 }
1511
1512 return ParseStatus::Success;
1513}
1514
1515ParseStatus VEAsmParser::parseVEAsmOperand(std::unique_ptr<VEOperand> &Op) {
1516 LLVM_DEBUG(dbgs() << "parseVEAsmOperand\n");
1517 SMLoc S = Parser.getTok().getLoc();
1519 const MCExpr *EVal;
1520
1521 Op = nullptr;
1522 switch (getLexer().getKind()) {
1523 default:
1524 break;
1525
1526 case AsmToken::Percent: {
1528 if (tryParseRegister(Reg, S, E).isSuccess())
1529 Op = VEOperand::CreateReg(Reg, S, E);
1530 break;
1531 }
1532 case AsmToken::Minus:
1533 case AsmToken::Integer:
1534 case AsmToken::Dot:
1536 if (!parseExpression(EVal))
1537 Op = VEOperand::CreateImm(EVal, S, E);
1538 break;
1539 }
1541}
1542
1543// Force static initialization.
1546}
1547
1548#define GET_REGISTER_MATCHER
1549#define GET_MATCHER_IMPLEMENTATION
1550#include "VEGenAsmMatcher.inc"
1551
1552unsigned VEAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1553 unsigned Kind) {
1554 VEOperand &Op = (VEOperand &)GOp;
1555
1556 // VE uses identical register name for all registers like both
1557 // F32 and I32 uses "%s23". Need to convert the name of them
1558 // for validation.
1559 switch (Kind) {
1560 default:
1561 break;
1562 case MCK_F32:
1563 if (Op.isReg() && VEOperand::MorphToF32Reg(Op))
1565 break;
1566 case MCK_I32:
1567 if (Op.isReg() && VEOperand::MorphToI32Reg(Op))
1569 break;
1570 case MCK_F128:
1571 if (Op.isReg() && VEOperand::MorphToF128Reg(Op))
1573 break;
1574 case MCK_VM512:
1575 if (Op.isReg() && VEOperand::MorphToVM512Reg(Op))
1577 break;
1578 case MCK_MISC:
1579 if (Op.isImm() && VEOperand::MorphToMISCReg(Op))
1581 break;
1582 }
1583 return Match_InvalidOperand;
1584}
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
basic Basic Alias true
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
#define LLVM_DEBUG(X)
Definition: Debug.h:101
constexpr char SuffixEnd
Definition: ELFEmitter.cpp:686
std::string Name
uint64_t Size
static LVOptions Options
Definition: LVOptions.cpp:25
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
Definition: Lint.cpp:526
mir Rename Register Operands
unsigned Reg
LLVMContext & Context
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
This file defines the SmallVector class.
static const MCPhysReg MISCRegs[31]
static const MCPhysReg F128Regs[32]
static const MCPhysReg F32Regs[64]
static unsigned MatchRegisterAltName(StringRef Name)
Maps from the set of all alternative registernames to a register number.
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
static StringRef parseCC(StringRef Name, unsigned Prefix, unsigned Suffix, bool IntegerCC, bool OmitCC, SMLoc NameLoc, OperandVector *Operands)
static const MCPhysReg VM512Regs[8]
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEAsmParser()
static unsigned MatchRegisterName(StringRef Name)
Maps from the set of all register names to a register number.
static const MCPhysReg I32Regs[64]
static StringRef parseRD(StringRef Name, unsigned Prefix, SMLoc NameLoc, OperandVector *Operands)
static bool isMImm(SDValue V)
Value * RHS
Value * LHS
static constexpr uint32_t Opcode
Definition: aarch32.h:200
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
StringRef getString() const
Get the string for the current token, this includes all characters (for example, the quotes on string...
Definition: MCAsmMacro.h:110
bool is(TokenKind K) const
Definition: MCAsmMacro.h:82
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
StringRef getIdentifier() const
Get the identifier string for the current token, which should be an identifier or a string.
Definition: MCAsmMacro.h:99
This class represents an Operation in the Expression.
Base class for user error types.
Definition: Error.h:352
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Container class for subtarget features.
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:123
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
virtual const AsmToken & Lex()=0
Get the next AsmToken in the stream, possibly handling file inclusion first.
Binary assembler expressions.
Definition: MCExpr.h:484
const MCExpr * getLHS() const
Get the left-hand side expression of the binary operator.
Definition: MCExpr.h:631
const MCExpr * getRHS() const
Get the right-hand side expression of the binary operator.
Definition: MCExpr.h:634
Opcode getOpcode() const
Get the kind of this binary expression.
Definition: MCExpr.h:628
static const MCBinaryExpr * create(Opcode Op, const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:183
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Context object for machine code objects.
Definition: MCContext.h:76
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
@ Unary
Unary expressions.
Definition: MCExpr.h:41
@ Constant
Constant expressions.
Definition: MCExpr.h:39
@ SymbolRef
References to labels and assigned expressions.
Definition: MCExpr.h:40
@ Target
Target specific expression.
Definition: MCExpr.h:42
@ Binary
Binary expressions.
Definition: MCExpr.h:38
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void setLoc(SMLoc loc)
Definition: MCInst.h:203
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
virtual unsigned getReg() const =0
virtual SMLoc getStartLoc() const =0
getStartLoc - Get the location of the first token of this operand.
virtual bool isReg() const =0
isReg - Is this a register operand?
virtual bool isMem() const =0
isMem - Is this a memory operand?
virtual void print(raw_ostream &OS) const =0
print - Print a debug representation of the operand to the given stream.
virtual bool isToken() const =0
isToken - Is this a token operand?
virtual bool isImm() const =0
isImm - Is this an immediate operand?
virtual SMLoc getEndLoc() const =0
getEndLoc - Get the location of the last token of this operand.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
Represent a reference to a symbol from inside an expression.
Definition: MCExpr.h:192
const MCSymbol & getSymbol() const
Definition: MCExpr.h:402
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389
VariantKind getKind() const
Definition: MCExpr.h:404
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual ParseStatus parseDirective(AsmToken DirectiveID)
Parses a target-specific assembler directive.
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
void setAvailableFeatures(const FeatureBitset &Value)
const MCSubtargetInfo & getSTI() const
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind)
Allow a target to add special case operand matching for things that tblgen doesn't/can't handle effec...
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
Unary assembler expressions.
Definition: MCExpr.h:428
Opcode getOpcode() const
Get the kind of this unary expression.
Definition: MCExpr.h:471
static const MCUnaryExpr * create(Opcode Op, const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
Definition: MCExpr.cpp:189
const MCExpr * getSubExpr() const
Get the child of this unary expression.
Definition: MCExpr.h:474
Ternary parse status returned by various parse* methods.
constexpr bool isFailure() const
static constexpr StatusTy Failure
constexpr bool isSuccess() const
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
Represents a location in source code.
Definition: SMLoc.h:23
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
constexpr const char * getPointer() const
Definition: SMLoc.h:34
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
iterator end() const
Definition: StringRef.h:113
std::string lower() const
Definition: StringRef.cpp:111
const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Definition: StringRef.h:131
static const VEMCExpr * create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx)
Definition: VEMCExpr.cpp:27
@ VK_VE_TLS_GD_HI32
Definition: VEMCExpr.h:38
@ VK_VE_TPOFF_HI32
Definition: VEMCExpr.h:40
@ VK_VE_TPOFF_LO32
Definition: VEMCExpr.h:41
@ VK_VE_TLS_GD_LO32
Definition: VEMCExpr.h:39
@ VK_VE_GOTOFF_HI32
Definition: VEMCExpr.h:34
@ VK_VE_GOTOFF_LO32
Definition: VEMCExpr.h:35
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
std::variant< std::monostate, Loc::Single, Loc::Multi, Loc::MMI, Loc::EntryValue > Variant
Alias for the std::variant specialization base class of DbgVariable.
Definition: DwarfDebug.h:190
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:148
CondCode
Definition: VE.h:42
@ CC_AF
Definition: VE.h:52
@ UNKNOWN
Definition: VE.h:68
@ CC_AT
Definition: VE.h:67
RoundingMode
Definition: VE.h:74
@ UNKNOWN
Definition: VE.h:81
@ CE
Windows NT (Windows on ARM)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
@ Length
Definition: DWP.cpp:440
Target & getTheVETarget()
static VECC::CondCode stringToVEFCondCode(StringRef S)
Definition: VE.h:128
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
DWARFExpression::Operation Op
RoundingMode
Rounding mode.
static VERD::RoundingMode stringToVERD(StringRef S)
Definition: VE.h:283
static VECC::CondCode stringToVEICondCode(StringRef S)
Definition: VE.h:114
#define N
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...