LLVM  14.0.0git
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AArch64InstructionSelector.cpp File Reference
#include "AArch64GlobalISelUtils.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64RegisterBankInfo.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/ADT/Optional.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/IntrinsicsAArch64.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "AArch64GenGlobalISel.inc"
Include dependency graph for AArch64InstructionSelector.cpp:

Go to the source code of this file.

Namespaces

 llvm
 This file implements support for optimizing divisions by a constant.
 

Macros

#define DEBUG_TYPE   "aarch64-isel"
 
#define GET_GLOBALISEL_PREDICATE_BITSET
 
#define GET_GLOBALISEL_PREDICATES_DECL
 
#define GET_GLOBALISEL_TEMPORARIES_DECL
 
#define GET_GLOBALISEL_IMPL
 
#define GET_GLOBALISEL_PREDICATES_INIT
 
#define GET_GLOBALISEL_TEMPORARIES_INIT
 

Functions

static const TargetRegisterClassgetMinClassForRegBank (const RegisterBank &RB, unsigned SizeInBits, bool GetAllRegSet=false)
 Given a register bank, and size in bits, return the smallest register class that can represent that combination. More...
 
static bool getSubRegForClass (const TargetRegisterClass *RC, const TargetRegisterInfo &TRI, unsigned &SubReg)
 Returns the correct subregister to use for a given register class. More...
 
static unsigned getMinSizeForRegBank (const RegisterBank &RB)
 Returns the minimum size the given register bank can hold. More...
 
static Register createTuple (ArrayRef< Register > Regs, const unsigned RegClassIDs[], const unsigned SubRegs[], MachineIRBuilder &MIB)
 Create a REG_SEQUENCE instruction using the registers in Regs. More...
 
static Register createDTuple (ArrayRef< Register > Regs, MachineIRBuilder &MIB)
 Create a tuple of D-registers using the registers in Regs. More...
 
static Register createQTuple (ArrayRef< Register > Regs, MachineIRBuilder &MIB)
 Create a tuple of Q-registers using the registers in Regs. More...
 
static Optional< uint64_tgetImmedFromMO (const MachineOperand &Root)
 
static bool unsupportedBinOp (const MachineInstr &I, const AArch64RegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const AArch64RegisterInfo &TRI)
 Check whether I is a currently unsupported binary operation: More...
 
static unsigned selectBinaryOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize. More...
 
static unsigned selectLoadStoreUIOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
 Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize. More...
 
static bool isValidCopy (const MachineInstr &I, const RegisterBank &DstBank, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 Helper function that verifies that we have a valid copy at the end of selectCopy. More...
 
static bool copySubReg (MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register SrcReg, const TargetRegisterClass *To, unsigned SubReg)
 Helper function for selectCopy. More...
 
static std::pair< const TargetRegisterClass *, const TargetRegisterClass * > getRegClassesForCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 Helper function to get the source and destination register classes for a copy. More...
 
static bool selectCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
 
static unsigned selectFPConvOpc (unsigned GenericOpc, LLT DstTy, LLT SrcTy)
 
static AArch64CC::CondCode changeICMPPredToAArch64CC (CmpInst::Predicate P)
 
static Register getTestBitReg (Register Reg, uint64_t &Bit, bool &Invert, MachineRegisterInfo &MRI)
 Return a register which can be used as a bit to test in a TB(N)Z. More...
 
static Optional< int64_t > getVectorShiftImm (Register Reg, MachineRegisterInfo &MRI)
 Returns the element immediate value of a vector shift operand if found. More...
 
static Optional< int64_t > getVectorSHLImm (LLT SrcTy, Register Reg, MachineRegisterInfo &MRI)
 Matches and returns the shift immediate value for a SHL instruction given a shift operand. More...
 
static bool getLaneCopyOpcode (unsigned &CopyOpc, unsigned &ExtractSubReg, const unsigned EltSize)
 
static std::pair< unsigned, unsigned > getInsertVecEltOpInfo (const RegisterBank &RB, unsigned EltSize)
 Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given size and RB. More...
 
static bool isSignExtendShiftType (AArch64_AM::ShiftExtendType Type)
 
static AArch64_AM::ShiftExtendType getShiftTypeForInst (MachineInstr &MI)
 Given a shift instruction, return the correct shift type for that instruction. More...
 
static void fixupPHIOpBanks (MachineInstr &MI, MachineRegisterInfo &MRI, const AArch64RegisterBankInfo &RBI)
 
InstructionSelectorllvm::createAArch64InstructionSelector (const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
 

Detailed Description

This file implements the targeting of the InstructionSelector class for AArch64.

Todo:
This should be generated by TableGen.

Definition in file AArch64InstructionSelector.cpp.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-isel"

Definition at line 49 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

Definition at line 468 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

Definition at line 62 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

Definition at line 455 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

Definition at line 461 of file AArch64InstructionSelector.cpp.

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

Function Documentation

◆ changeICMPPredToAArch64CC()

static AArch64CC::CondCode changeICMPPredToAArch64CC ( CmpInst::Predicate  P)
static

◆ copySubReg()

static bool copySubReg ( MachineInstr I,
MachineRegisterInfo MRI,
const RegisterBankInfo RBI,
Register  SrcReg,
const TargetRegisterClass To,
unsigned  SubReg 
)
static

Helper function for selectCopy.

Inserts a subregister copy from SrcReg to *To.

E.g "To = COPY SrcReg:SubReg"

Definition at line 868 of file AArch64InstructionSelector.cpp.

References assert(), llvm::MachineIRBuilder::buildInstr(), llvm::RegisterBankInfo::constrainGenericRegister(), I, llvm::Register::isValid(), MRI, llvm::MachineOperand::setReg(), and SubReg.

Referenced by selectCopy().

◆ createDTuple()

static Register createDTuple ( ArrayRef< Register Regs,
MachineIRBuilder MIB 
)
static

Create a tuple of D-registers using the registers in Regs.

Definition at line 636 of file AArch64InstructionSelector.cpp.

References createTuple().

◆ createQTuple()

static Register createQTuple ( ArrayRef< Register Regs,
MachineIRBuilder MIB 
)
static

Create a tuple of Q-registers using the registers in Regs.

Definition at line 645 of file AArch64InstructionSelector.cpp.

References createTuple().

◆ createTuple()

static Register createTuple ( ArrayRef< Register Regs,
const unsigned  RegClassIDs[],
const unsigned  SubRegs[],
MachineIRBuilder MIB 
)
static

Create a REG_SEQUENCE instruction using the registers in Regs.

Helper function for functions like createDTuple and createQTuple.

RegClassIDs - The list of register class IDs available for some tuple of a scalar class. E.g. QQRegClassID, QQQRegClassID, QQQQRegClassID. This is expected to contain between 2 and 4 tuple classes.

SubRegs - The list of subregister classes associated with each register class ID in RegClassIDs. E.g., QQRegClassID should use the qsub0 subregister class. The index of each subregister class is expected to correspond with the index of each register class.

Returns
Either the destination register of REG_SEQUENCE instruction that was created, or the 0th element of Regs if Regs contains a single element.

Definition at line 616 of file AArch64InstructionSelector.cpp.

References assert(), llvm::MachineIRBuilder::buildInstr(), E, llvm::MachineIRBuilder::getMF(), llvm::TargetRegisterInfo::getRegClass(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), I, llvm::MCID::RegSequence, llvm::ArrayRef< T >::size(), and TRI.

Referenced by createDTuple(), and createQTuple().

◆ fixupPHIOpBanks()

static void fixupPHIOpBanks ( MachineInstr MI,
MachineRegisterInfo MRI,
const AArch64RegisterBankInfo RBI 
)
static

◆ getImmedFromMO()

static Optional<uint64_t> getImmedFromMO ( const MachineOperand Root)
static

◆ getInsertVecEltOpInfo()

static std::pair<unsigned, unsigned> getInsertVecEltOpInfo ( const RegisterBank RB,
unsigned  EltSize 
)
static

Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given size and RB.

Definition at line 4290 of file AArch64InstructionSelector.cpp.

References llvm::RegisterBank::getID(), and llvm_unreachable.

◆ getLaneCopyOpcode()

static bool getLaneCopyOpcode ( unsigned &  CopyOpc,
unsigned &  ExtractSubReg,
const unsigned  EltSize 
)
static

Definition at line 3933 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), and LLVM_DEBUG.

◆ getMinClassForRegBank()

static const TargetRegisterClass* getMinClassForRegBank ( const RegisterBank RB,
unsigned  SizeInBits,
bool  GetAllRegSet = false 
)
static

Given a register bank, and size in bits, return the smallest register class that can represent that combination.

Definition at line 526 of file AArch64InstructionSelector.cpp.

References llvm::RegisterBank::getID().

Referenced by getRegClassesForCopy(), and selectCopy().

◆ getMinSizeForRegBank()

static unsigned getMinSizeForRegBank ( const RegisterBank RB)
static

Returns the minimum size the given register bank can hold.

Definition at line 590 of file AArch64InstructionSelector.cpp.

References llvm::RegisterBank::getID(), and llvm_unreachable.

Referenced by selectCopy().

◆ getRegClassesForCopy()

static std::pair<const TargetRegisterClass *, const TargetRegisterClass *> getRegClassesForCopy ( MachineInstr I,
const TargetInstrInfo TII,
MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

Helper function to get the source and destination register classes for a copy.

Returns a std::pair containing the source register class for the copy, and the destination register class for the copy. If a register class cannot be determined, then it will be nullptr.

Definition at line 894 of file AArch64InstructionSelector.cpp.

References getMinClassForRegBank(), llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::getSizeInBits(), I, MRI, and TRI.

Referenced by selectCopy().

◆ getShiftTypeForInst()

static AArch64_AM::ShiftExtendType getShiftTypeForInst ( MachineInstr MI)
static

Given a shift instruction, return the correct shift type for that instruction.

Definition at line 6122 of file AArch64InstructionSelector.cpp.

References llvm::AArch64_AM::ASR, llvm::AArch64_AM::InvalidShiftExtend, llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, MI, and llvm::AArch64_AM::ROR.

◆ getSubRegForClass()

static bool getSubRegForClass ( const TargetRegisterClass RC,
const TargetRegisterInfo TRI,
unsigned &  SubReg 
)
static

Returns the correct subregister to use for a given register class.

Definition at line 562 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), llvm::TargetRegisterInfo::getRegSizeInBits(), LLVM_DEBUG, SubReg, and TRI.

Referenced by selectCopy().

◆ getTestBitReg()

static Register getTestBitReg ( Register  Reg,
uint64_t Bit,
bool &  Invert,
MachineRegisterInfo MRI 
)
static

◆ getVectorShiftImm()

static Optional<int64_t> getVectorShiftImm ( Register  Reg,
MachineRegisterInfo MRI 
)
static

Returns the element immediate value of a vector shift operand if found.

This needs to detect a splat-like operation, e.g. a G_BUILD_VECTOR.

Definition at line 1702 of file AArch64InstructionSelector.cpp.

References assert(), llvm::AArch64GISelUtils::getAArch64VectorSplatScalar(), llvm::MachineRegisterInfo::getType(), llvm::MachineRegisterInfo::getVRegDef(), llvm::LLT::isVector(), MRI, and Reg.

Referenced by getVectorSHLImm().

◆ getVectorSHLImm()

static Optional<int64_t> getVectorSHLImm ( LLT  SrcTy,
Register  Reg,
MachineRegisterInfo MRI 
)
static

Matches and returns the shift immediate value for a SHL instruction given a shift operand.

Definition at line 1712 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), llvm::LLT::getElementType(), llvm::LLT::getSizeInBits(), getVectorShiftImm(), LLVM_DEBUG, MRI, llvm::None, and Reg.

◆ isSignExtendShiftType()

static bool isSignExtendShiftType ( AArch64_AM::ShiftExtendType  Type)
static

◆ isValidCopy()

static bool isValidCopy ( const MachineInstr I,
const RegisterBank DstBank,
const MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

Helper function that verifies that we have a valid copy at the end of selectCopy.

Verifies that the source and dest have the expected sizes and then returns true.

Definition at line 835 of file AArch64InstructionSelector.cpp.

References assert(), llvm::RegisterBank::getID(), llvm::RegisterBankInfo::getSizeInBits(), I, MRI, and TRI.

Referenced by selectCopy().

◆ selectBinaryOp()

static unsigned selectBinaryOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize.

Returns
GenericOpc if the combination is unsupported.

Definition at line 726 of file AArch64InstructionSelector.cpp.

Referenced by llvm::FastISel::selectOperator().

◆ selectCopy()

static bool selectCopy ( MachineInstr I,
const TargetInstrInfo TII,
MachineRegisterInfo MRI,
const TargetRegisterInfo TRI,
const RegisterBankInfo RBI 
)
static

◆ selectFPConvOpc()

static unsigned selectFPConvOpc ( unsigned  GenericOpc,
LLT  DstTy,
LLT  SrcTy 
)
static

◆ selectLoadStoreUIOp()

static unsigned selectLoadStoreUIOp ( unsigned  GenericOpc,
unsigned  RegBankID,
unsigned  OpSize 
)
static

Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize.

This returns the variant with the base+unsigned-immediate addressing mode (e.g., LDRXui).

Returns
GenericOpc if the combination is unsupported.

Definition at line 797 of file AArch64InstructionSelector.cpp.

References isStore().

◆ unsupportedBinOp()

static bool unsupportedBinOp ( const MachineInstr I,
const AArch64RegisterBankInfo RBI,
const MachineRegisterInfo MRI,
const AArch64RegisterInfo TRI 
)
static

Check whether I is a currently unsupported binary operation:

  • it has an unsized type
  • an operand is not a vreg
  • all operands are not in the same bank These are checks that should someday live in the verifier, but right now, these are mostly limitations of the aarch64 selector.

Definition at line 680 of file AArch64InstructionSelector.cpp.

References llvm::dbgs(), llvm::RegisterBankInfo::getRegBank(), llvm::MachineRegisterInfo::getType(), I, llvm::LLT::isValid(), LLVM_DEBUG, MRI, and TRI.