LLVM 17.0.0git
AArch64GlobalISelUtils.h
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1//===- AArch64GlobalISelUtils.h ----------------------------------*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file APIs for AArch64-specific helper functions used in the GlobalISel
9/// pipeline.
10//===----------------------------------------------------------------------===//
11
12#ifndef LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
13#define LLVM_LIB_TARGET_AARCH64_GISEL_AARCH64GLOBALISELUTILS_H
19#include "llvm/IR/InstrTypes.h"
20#include <cstdint>
21
22namespace llvm {
23
24namespace AArch64GISelUtils {
25
26/// \returns true if \p C is a legal immediate operand for an arithmetic
27/// instruction.
28constexpr bool isLegalArithImmed(const uint64_t C) {
29 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
30}
31
32/// \returns A value when \p MI is a vector splat of a Register or constant.
33/// Checks for generic opcodes and AArch64-specific generic opcodes.
34std::optional<RegOrConstant>
36
37/// \returns A value when \p MI is a constant vector splat.
38/// Checks for generic opcodes and AArch64-specific generic opcodes.
39std::optional<int64_t>
42
43/// \returns true if \p MaybeSub and \p Pred are part of a CMN tree for an
44/// integer compare.
45bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred,
47
48/// Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is
49/// supported and beneficial to do so.
50///
51/// \note This only applies on Darwin.
52///
53/// \returns true if \p MI was replaced with a G_BZERO.
54bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize);
55
56/// Find the AArch64 condition codes necessary to represent \p P for a scalar
57/// floating point comparison.
58///
59/// \param [out] CondCode is the first condition code.
60/// \param [out] CondCode2 is the second condition code if necessary.
61/// AArch64CC::AL otherwise.
63 AArch64CC::CondCode &CondCode,
64 AArch64CC::CondCode &CondCode2);
65
66/// Find the AArch64 condition codes necessary to represent \p P for a vector
67/// floating point comparison.
68///
69/// \param [out] CondCode - The first condition code.
70/// \param [out] CondCode2 - The second condition code if necessary.
71/// AArch64CC::AL otherwise.
72/// \param [out] Invert - True if the comparison must be inverted with a NOT.
74 AArch64CC::CondCode &CondCode,
75 AArch64CC::CondCode &CondCode2,
76 bool &Invert);
77
78} // namespace AArch64GISelUtils
79} // namespace llvm
80
81#endif
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
This file declares the MachineIRBuilder class.
#define P(N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
Helper class to build MachineInstr.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
std::optional< RegOrConstant > getAArch64VectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI)
constexpr bool isLegalArithImmed(const uint64_t C)
void changeFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
Find the AArch64 condition codes necessary to represent P for a scalar floating point comparison.
bool tryEmitBZero(MachineInstr &MI, MachineIRBuilder &MIRBuilder, bool MinSize)
Replace a G_MEMSET with a value of 0 with a G_BZERO instruction if it is supported and beneficial to ...
void changeVectorFCMPPredToAArch64CC(const CmpInst::Predicate P, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
Find the AArch64 condition codes necessary to represent P for a vector floating point comparison.
bool isCMN(const MachineInstr *MaybeSub, const CmpInst::Predicate &Pred, const MachineRegisterInfo &MRI)
std::optional< int64_t > getAArch64VectorSplatScalar(const MachineInstr &MI, const MachineRegisterInfo &MRI)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18