LLVM  12.0.0git
ProcessImplicitDefs.cpp
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1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/ADT/SetVector.h"
14 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/InitializePasses.h"
18 #include "llvm/Support/Debug.h"
20 
21 using namespace llvm;
22 
23 #define DEBUG_TYPE "processimpdefs"
24 
25 namespace {
26 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def
27 /// for each use. Add isUndef marker to implicit_def defs and their uses.
28 class ProcessImplicitDefs : public MachineFunctionPass {
29  const TargetInstrInfo *TII;
30  const TargetRegisterInfo *TRI;
32 
34 
35  void processImplicitDef(MachineInstr *MI);
36  bool canTurnIntoImplicitDef(MachineInstr *MI);
37 
38 public:
39  static char ID;
40 
41  ProcessImplicitDefs() : MachineFunctionPass(ID) {
43  }
44 
45  void getAnalysisUsage(AnalysisUsage &au) const override;
46 
47  bool runOnMachineFunction(MachineFunction &MF) override;
48 };
49 } // end anonymous namespace
50 
53 
54 INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE,
55  "Process Implicit Definitions", false, false)
56 
57 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
58  AU.setPreservesCFG();
59  AU.addPreserved<AAResultsWrapperPass>();
61 }
62 
63 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
64  if (!MI->isCopyLike() &&
65  !MI->isInsertSubreg() &&
66  !MI->isRegSequence() &&
67  !MI->isPHI())
68  return false;
69  for (const MachineOperand &MO : MI->operands())
70  if (MO.isReg() && MO.isUse() && MO.readsReg())
71  return false;
72  return true;
73 }
74 
75 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
76  LLVM_DEBUG(dbgs() << "Processing " << *MI);
77  Register Reg = MI->getOperand(0).getReg();
78 
79  if (Register::isVirtualRegister(Reg)) {
80  // For virtual registers, mark all uses as <undef>, and convert users to
81  // implicit-def when possible.
82  for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
83  MO.setIsUndef();
84  MachineInstr *UserMI = MO.getParent();
85  if (!canTurnIntoImplicitDef(UserMI))
86  continue;
87  LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
88  UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
89  WorkList.insert(UserMI);
90  }
91  MI->eraseFromParent();
92  return;
93  }
94 
95  // This is a physreg implicit-def.
96  // Look for the first instruction to use or define an alias.
99  bool Found = false;
100  for (++UserMI; UserMI != UserE; ++UserMI) {
101  for (MachineOperand &MO : UserMI->operands()) {
102  if (!MO.isReg())
103  continue;
104  Register UserReg = MO.getReg();
105  if (!Register::isPhysicalRegister(UserReg) ||
106  !TRI->regsOverlap(Reg, UserReg))
107  continue;
108  // UserMI uses or redefines Reg. Set <undef> flags on all uses.
109  Found = true;
110  if (MO.isUse())
111  MO.setIsUndef();
112  }
113  if (Found)
114  break;
115  }
116 
117  // If we found the using MI, we can erase the IMPLICIT_DEF.
118  if (Found) {
119  LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
120  MI->eraseFromParent();
121  return;
122  }
123 
124  // Using instr wasn't found, it could be in another block.
125  // Leave the physreg IMPLICIT_DEF, but trim any extra operands.
126  for (unsigned i = MI->getNumOperands() - 1; i; --i)
127  MI->RemoveOperand(i);
128  LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
129 }
130 
131 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
132 /// <undef> operands.
133 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
134 
135  LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
136  << "********** Function: " << MF.getName() << '\n');
137 
138  bool Changed = false;
139 
140  TII = MF.getSubtarget().getInstrInfo();
142  MRI = &MF.getRegInfo();
143  assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
144  assert(WorkList.empty() && "Inconsistent worklist state");
145 
146  for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end();
147  MFI != MFE; ++MFI) {
148  // Scan the basic block for implicit defs.
150  MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI)
151  if (MBBI->isImplicitDef())
152  WorkList.insert(&*MBBI);
153 
154  if (WorkList.empty())
155  continue;
156 
157  LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
158  << " implicit defs.\n");
159  Changed = true;
160 
161  // Drain the WorkList to recursively process any new implicit defs.
162  do processImplicitDef(WorkList.pop_back_val());
163  while (!WorkList.empty());
164  }
165  return Changed;
166 }
#define DEBUG_TYPE
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
instr_iterator instr_begin()
instr_iterator instr_end()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
unsigned Reg
bool isRegSequence() const
unsigned const TargetRegisterInfo * TRI
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:559
bool isCopyLike() const
Return true if the instruction behaves like a copy.
bool isPHI() const
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:459
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
virtual const TargetInstrInfo * getInstrInfo() const
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
TargetInstrInfo - Interface to description of machine instruction set.
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE, "Process Implicit Definitions", false, false) void ProcessImplicitDefs
Represent the analysis usage information of a pass.
void initializeProcessImplicitDefsPass(PassRegistry &)
self_iterator getIterator()
Definition: ilist_node.h:81
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A SetVector that performs no allocations if smaller than a certain size.
Definition: SetVector.h:302
Iterator for intrusive lists based on ilist_node.
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one...
MachineOperand class - Representation of each machine instruction operand.
bool isInsertSubreg() const
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:280
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
Representation of each machine instruction.
Definition: MachineInstr.h:62
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
IRTranslator LLVM IR MI
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with...
Register getReg() const
getReg - Returns the register number.
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object...
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
MachineBasicBlock MachineBasicBlock::iterator MBBI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19