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90 #define DEBUG_TYPE "shrink-wrap"
92 STATISTIC(NumFunc,
"Number of functions");
93 STATISTIC(NumCandidates,
"Number of shrink-wrapping candidates");
95 "Number of shrink-wrapping candidates dropped because of frequency");
99 cl::desc(
"enable the shrink-wrapping pass"));
141 unsigned FrameSetupOpcode;
144 unsigned FrameDestroyOpcode;
155 mutable SetOfRegs CurrentCSRs;
165 const SetOfRegs &getCurrentCSRs(
RegScavenger *RS)
const {
166 if (CurrentCSRs.empty()) {
175 CurrentCSRs.insert((
unsigned)
Reg);
190 MDT = &getAnalysis<MachineDominatorTree>();
191 MPDT = &getAnalysis<MachinePostDominatorTree>();
194 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
195 MLI = &getAnalysis<MachineLoopInfo>();
196 ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
200 FrameSetupOpcode =
TII.getCallFrameSetupOpcode();
201 FrameDestroyOpcode =
TII.getCallFrameDestroyOpcode();
212 bool ArePointsInteresting()
const {
return Save != Entry && Save && Restore; }
239 StringRef getPassName()
const override {
return "Shrink Wrapping analysis"; }
268 if (
MI.mayLoadOrStore())
271 if (
MI.getOpcode() == FrameSetupOpcode ||
272 MI.getOpcode() == FrameDestroyOpcode) {
279 bool UseOrDefCSR =
false;
282 if (!MO.isDef() && !MO.readsReg())
298 (!
MI.isCall() && PhysReg == SP) ||
301 }
else if (MO.isRegMask()) {
303 for (
unsigned Reg : getCurrentCSRs(RS)) {
304 if (MO.clobbersPhysReg(
Reg)) {
311 if (UseOrDefCSR || (MO.isFI() && !
MI.isDebugValue())) {
312 LLVM_DEBUG(
dbgs() <<
"Use or define CSR(" << UseOrDefCSR <<
") or FI("
313 << MO.isFI() <<
"): " <<
MI <<
'\n');
321 template <
typename ListOfBBs,
typename DominanceAnalysis>
323 DominanceAnalysis &Dom) {
326 IDom = Dom.findNearestCommonDominator(IDom,
BB);
357 if (Restore == &
MBB) {
368 Restore = FindIDom<>(*Restore, Restore->
successors(), *MPDT);
375 dbgs() <<
"Restore point needs to be spanned on several blocks\n");
386 bool SaveDominatesRestore =
false;
387 bool RestorePostDominatesSave =
false;
389 (!(SaveDominatesRestore = MDT->
dominates(Save, Restore)) ||
390 !(RestorePostDominatesSave = MPDT->
dominates(Restore, Save)) ||
410 if (!SaveDominatesRestore) {
415 if (!RestorePostDominatesSave)
435 IPdom = FindIDom<>(*IPdom, LoopExitBB->successors(), *MPDT);
467 if (skipFunction(MF.
getFunction()) || MF.
empty() || !isShrinkWrapEnabled(MF))
475 if (containsIrreducibleCFG<MachineBasicBlock *>(RPOT, *MLI)) {
483 "Irreducible CFGs are not supported yet.",
488 std::unique_ptr<RegScavenger> RS(
497 "EH Funclets are not supported yet.",
506 updateSaveRestorePoints(
MBB, RS.get());
507 if (!ArePointsInteresting()) {
508 LLVM_DEBUG(
dbgs() <<
"EHPad/inlineasm_br prevents shrink-wrapping\n");
515 if (!useOrDefCSROrFI(
MI, RS.get()))
519 updateSaveRestorePoints(
MBB, RS.get());
522 if (!ArePointsInteresting()) {
531 if (!ArePointsInteresting()) {
535 assert(!Save && !Restore &&
"We miss a shrink-wrap opportunity?!");
540 LLVM_DEBUG(
dbgs() <<
"\n ** Results **\nFrequency of the Entry: " << EntryFreq
545 LLVM_DEBUG(
dbgs() <<
"Shrink wrap candidates (#, Name, Freq):\nSave: "
548 <<
"\nRestore: " << Restore->
getNumber() <<
' '
552 bool IsSaveCheap, TargetCanUseSaveAsPrologue =
false;
559 dbgs() <<
"New points are too expensive or invalid for the target\n");
561 if (!IsSaveCheap || !TargetCanUseSaveAsPrologue) {
568 Restore = FindIDom<>(*Restore, Restore->
successors(), *MPDT);
573 updateSaveRestorePoints(*NewBB, RS.get());
574 }
while (Save && Restore);
576 if (!ArePointsInteresting()) {
577 ++NumCandidatesDropped;
583 <<
"\nRestore: " << Restore->
getNumber() <<
' '
584 << Restore->
getName() <<
'\n');
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B)
findNearestCommonDominator - Find nearest common dominator basic block for basic block A and B.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
static MachineBasicBlock * FindIDom(MachineBasicBlock &Block, ListOfBBs BBs, DominanceAnalysis &Dom)
Helper function to find the immediate (post) dominator.
This is an optimization pass for GlobalISel generic memory operations.
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
Information about stack frame layout on the target.
virtual const TargetInstrInfo * getInstrInfo() const
bool isEHFuncletEntry() const
Returns true if this is the entry block of an EH funclet.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
DISubprogram * getSubprogram() const
Get the attached subprogram.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Properties which a MachineFunction may have at a given point in time.
static bool giveUpWithRemarks(MachineOptimizationRemarkEmitter *ORE, StringRef RemarkName, StringRef RemarkMessage, const DiagnosticLocation &Loc, const MachineBasicBlock *MBB)
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
iterator_range< iterator > terminators()
unsigned const TargetRegisterInfo * TRI
BlockFrequency getBlockFreq(const MachineBasicBlock *MBB) const
getblockFreq - Return block frequency.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineBasicBlock & front() const
TargetInstrInfo - Interface to description of machine instruction set.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual bool enableShrinkWrapping(const MachineFunction &MF) const
Returns true if the target will correctly handle shrink wrapping.
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
virtual bool canUseAsEpilogue(const MachineBasicBlock &MBB) const
Check whether or not the given MBB can be used as a epilogue for the target.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
virtual bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const
Some targets have non-allocatable registers that aren't technically part of the explicit callee saved...
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineFunctionProperties & set(Property P)
STATISTIC(NumFunctions, "Total number of functions")
void getExitingBlocks(SmallVectorImpl< BlockT * > &ExitingBlocks) const
Return all blocks inside the loop that have successors outside of the loop.
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
uint64_t getFrequency() const
Returns the frequency as a fixpoint number scaled by the entry frequency.
initializer< Ty > init(const Ty &Val)
void setRestorePoint(MachineBasicBlock *NewRestore)
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
iterator_range< pred_iterator > predecessors()
void setSavePoint(MachineBasicBlock *NewSave)
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
iterator_range< succ_iterator > successors()
bool isEHPad() const
Returns true if the block is a landing pad.
StringRef - Represent a constant reference to a string, i.e.
This would be a win on but not x86 or ppc64 Shrink
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
void initializeShrinkWrapPass(PassRegistry &)
TargetSubtargetInfo - Generic base class for all target subtargets.
MachinePostDominatorTree - an analysis pass wrapper for DominatorTree used to compute the post-domina...
Wrapper class representing virtual and physical registers.
virtual bool canUseAsPrologue(const MachineBasicBlock &MBB) const
Check whether or not the given MBB can be used as a prologue for the target.
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Function & getFunction()
Return the LLVM function that this machine code represents.
virtual const TargetFrameLowering * getFrameLowering() const
void setPreservesAll()
Set by analyses that do not transform their input at all.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
unsigned getLoopDepth(const MachineBasicBlock *BB) const
Return the loop nesting level of the specified block.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg,...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Pass interface - Implemented by all 'passes'.
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
virtual const TargetLowering * getTargetLowering() const
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
Returns true if the target requires (and can make use of) the register scavenger.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
A SetVector that performs no allocations if smaller than a certain size.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
AnalysisUsage & addRequired()
MachineBasicBlock * findNearestCommonDominator(MachineBasicBlock *A, MachineBasicBlock *B) const
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
uint64_t getEntryFreq() const
Divide a block's BlockFrequency::getFrequency() value by this value to obtain the entry block - relat...
bool usesWindowsCFI() const
static cl::opt< cl::boolOrDefault > EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden, cl::desc("enable the shrink-wrapping pass"))
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.