LLVM  15.0.0git
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10 // instructions after register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13 
16 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/InitializePasses.h"
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "postrapseudos"
27 
28 namespace {
29 struct ExpandPostRA : public MachineFunctionPass {
30 private:
31  const TargetRegisterInfo *TRI;
32  const TargetInstrInfo *TII;
33 
34 public:
35  static char ID; // Pass identification, replacement for typeid
36  ExpandPostRA() : MachineFunctionPass(ID) {}
37 
38  void getAnalysisUsage(AnalysisUsage &AU) const override {
39  AU.setPreservesCFG();
43  }
44 
45  /// runOnMachineFunction - pass entry point
46  bool runOnMachineFunction(MachineFunction&) override;
47 
48 private:
49  bool LowerSubregToReg(MachineInstr *MI);
50  bool LowerCopy(MachineInstr *MI);
51 
52  void TransferImplicitOperands(MachineInstr *MI);
53 };
54 } // end anonymous namespace
55 
56 char ExpandPostRA::ID = 0;
58 
60  "Post-RA pseudo instruction expansion pass", false, false)
61 
62 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
63 /// replacement instructions immediately precede it. Copy any implicit
64 /// operands from MI to the replacement instruction.
65 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
67  --CopyMI;
68 
69  Register DstReg = MI->getOperand(0).getReg();
70  for (const MachineOperand &MO : MI->implicit_operands()) {
71  CopyMI->addOperand(MO);
72 
73  // Be conservative about preserving kills when subregister defs are
74  // involved. If there was implicit kill of a super-register overlapping the
75  // copy result, we would kill the subregisters previous copies defined.
76  if (MO.isKill() && TRI->regsOverlap(DstReg, MO.getReg()))
77  CopyMI->getOperand(CopyMI->getNumOperands() - 1).setIsKill(false);
78  }
79 }
80 
81 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
82  MachineBasicBlock *MBB = MI->getParent();
83  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
84  MI->getOperand(1).isImm() &&
85  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
86  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
87 
88  Register DstReg = MI->getOperand(0).getReg();
89  Register InsReg = MI->getOperand(2).getReg();
90  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
91  unsigned SubIdx = MI->getOperand(3).getImm();
92 
93  assert(SubIdx != 0 && "Invalid index for insert_subreg");
94  Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
95 
97  "Insert destination must be in a physical register");
99  "Inserted value must be in a physical register");
100 
101  LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
102 
103  if (MI->allDefsAreDead()) {
104  MI->setDesc(TII->get(TargetOpcode::KILL));
105  MI->removeOperand(3); // SubIdx
106  MI->removeOperand(1); // Imm
107  LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
108  return true;
109  }
110 
111  if (DstSubReg == InsReg) {
112  // No need to insert an identity copy instruction.
113  // Watch out for case like this:
114  // %rax = SUBREG_TO_REG 0, killed %eax, 3
115  // We must leave %rax live.
116  if (DstReg != InsReg) {
117  MI->setDesc(TII->get(TargetOpcode::KILL));
118  MI->removeOperand(3); // SubIdx
119  MI->removeOperand(1); // Imm
120  LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
121  return true;
122  }
123  LLVM_DEBUG(dbgs() << "subreg: eliminated!");
124  } else {
125  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
126  MI->getOperand(2).isKill());
127 
128  // Implicitly define DstReg for subsequent uses.
130  --CopyMI;
131  CopyMI->addRegisterDefined(DstReg);
132  LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
133  }
134 
135  LLVM_DEBUG(dbgs() << '\n');
136  MBB->erase(MI);
137  return true;
138 }
139 
140 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
141 
142  if (MI->allDefsAreDead()) {
143  LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
144  MI->setDesc(TII->get(TargetOpcode::KILL));
145  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
146  return true;
147  }
148 
149  MachineOperand &DstMO = MI->getOperand(0);
150  MachineOperand &SrcMO = MI->getOperand(1);
151 
152  bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
153  if (IdentityCopy || SrcMO.isUndef()) {
154  LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ")
155  << *MI);
156  // No need to insert an identity copy instruction, but replace with a KILL
157  // if liveness is changed.
158  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
159  // We must make sure the super-register gets killed. Replace the
160  // instruction with KILL.
161  MI->setDesc(TII->get(TargetOpcode::KILL));
162  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
163  return true;
164  }
165  // Vanilla identity copy.
166  MI->eraseFromParent();
167  return true;
168  }
169 
170  LLVM_DEBUG(dbgs() << "real copy: " << *MI);
171  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
172  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
173 
174  if (MI->getNumOperands() > 2)
175  TransferImplicitOperands(MI);
176  LLVM_DEBUG({
178  dbgs() << "replaced by: " << *(--dMI);
179  });
180  MI->eraseFromParent();
181  return true;
182 }
183 
184 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
185 /// copies.
186 ///
187 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
188  LLVM_DEBUG(dbgs() << "Machine Function\n"
189  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
190  << "********** Function: " << MF.getName() << '\n');
192  TII = MF.getSubtarget().getInstrInfo();
193 
194  bool MadeChange = false;
195 
196  for (MachineBasicBlock &MBB : MF) {
198  // Only expand pseudos.
199  if (!MI.isPseudo())
200  continue;
201 
202  // Give targets a chance to expand even standard pseudos.
203  if (TII->expandPostRAPseudo(MI)) {
204  MadeChange = true;
205  continue;
206  }
207 
208  // Expand standard pseudos.
209  switch (MI.getOpcode()) {
210  case TargetOpcode::SUBREG_TO_REG:
211  MadeChange |= LowerSubregToReg(&MI);
212  break;
213  case TargetOpcode::COPY:
214  MadeChange |= LowerCopy(&MI);
215  break;
216  case TargetOpcode::DBG_VALUE:
217  continue;
218  case TargetOpcode::INSERT_SUBREG:
219  case TargetOpcode::EXTRACT_SUBREG:
220  llvm_unreachable("Sub-register pseudos should have been eliminated.");
221  }
222  }
223  }
224 
225  return MadeChange;
226 }
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
DEBUG_TYPE
#define DEBUG_TYPE
Definition: ExpandPostRAPseudos.cpp:26
INITIALIZE_PASS
INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, "Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
Definition: ExpandPostRAPseudos.cpp:59
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::ExpandPostRAPseudosID
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition: ExpandPostRAPseudos.cpp:57
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
TargetInstrInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:103
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:389
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::TargetRegisterInfo::regsOverlap
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:419
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:618
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:565
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::HexagonInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
Definition: HexagonInstrInfo.cpp:1044
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:263
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
TargetSubtargetInfo.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
raw_ostream.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:854
InitializePasses.h
TargetRegisterInfo.h
Debug.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38