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26 #define DEBUG_TYPE "postrapseudos"
60 "Post-RA pseudo instruction expansion pass",
false,
false)
71 CopyMI->addOperand(MO);
77 CopyMI->getOperand(CopyMI->getNumOperands() - 1).setIsKill(
false);
83 assert((
MI->getOperand(0).isReg() &&
MI->getOperand(0).isDef()) &&
84 MI->getOperand(1).isImm() &&
85 (
MI->getOperand(2).isReg() &&
MI->getOperand(2).isUse()) &&
86 MI->getOperand(3).isImm() &&
"Invalid subreg_to_reg");
90 assert(!
MI->getOperand(2).getSubReg() &&
"SubIdx on physreg?");
91 unsigned SubIdx =
MI->getOperand(3).getImm();
93 assert(SubIdx != 0 &&
"Invalid index for insert_subreg");
97 "Insert destination must be in a physical register");
99 "Inserted value must be in a physical register");
103 if (
MI->allDefsAreDead()) {
104 MI->setDesc(
TII->get(TargetOpcode::KILL));
105 MI->removeOperand(3);
106 MI->removeOperand(1);
111 if (DstSubReg == InsReg) {
116 if (DstReg != InsReg) {
117 MI->setDesc(
TII->get(TargetOpcode::KILL));
118 MI->removeOperand(3);
119 MI->removeOperand(1);
126 MI->getOperand(2).isKill());
131 CopyMI->addRegisterDefined(DstReg);
142 if (
MI->allDefsAreDead()) {
144 MI->setDesc(
TII->get(TargetOpcode::KILL));
153 if (IdentityCopy || SrcMO.
isUndef()) {
154 LLVM_DEBUG(
dbgs() << (IdentityCopy ?
"identity copy: " :
"undef copy: ")
158 if (SrcMO.
isUndef() ||
MI->getNumOperands() > 2) {
161 MI->setDesc(
TII->get(TargetOpcode::KILL));
166 MI->eraseFromParent();
174 if (
MI->getNumOperands() > 2)
175 TransferImplicitOperands(
MI);
178 dbgs() <<
"replaced by: " << *(--dMI);
180 MI->eraseFromParent();
189 <<
"********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
190 <<
"********** Function: " << MF.
getName() <<
'\n');
194 bool MadeChange =
false;
209 switch (
MI.getOpcode()) {
210 case TargetOpcode::SUBREG_TO_REG:
211 MadeChange |= LowerSubregToReg(&
MI);
213 case TargetOpcode::COPY:
214 MadeChange |= LowerCopy(&
MI);
216 case TargetOpcode::DBG_VALUE:
218 case TargetOpcode::INSERT_SUBREG:
219 case TargetOpcode::EXTRACT_SUBREG:
This is an optimization pass for GlobalISel generic memory operations.
INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, "Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
virtual const TargetInstrInfo * getInstrInfo() const
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
TargetInstrInfo - Interface to description of machine instruction set.
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
Representation of each machine instruction.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getReg() const
getReg - Returns the register number.
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
AnalysisUsage & addPreservedID(const void *ID)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Wrapper class representing virtual and physical registers.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.