Go to the documentation of this file.
43 #define DEBUG_TYPE "early-ifcvt"
49 cl::desc(
"Maximum number of instructions per speculated block."));
55 STATISTIC(NumDiamondsSeen,
"Number of diamonds");
56 STATISTIC(NumDiamondsConv,
"Number of diamonds converted");
57 STATISTIC(NumTrianglesSeen,
"Number of triangles");
58 STATISTIC(NumTrianglesConv,
"Number of triangles converted");
102 bool isTriangle()
const {
return TBB ==
Tail || FBB ==
Tail; }
113 unsigned TReg = 0, FReg = 0;
115 int CondCycles = 0, TCycles = 0, FCycles = 0;
157 bool findInsertionPoint();
160 void replacePHIInstrs();
163 void rewritePHIOperands();
173 ClobberedRegUnits.
clear();
213 if (
MI.isDebugInstr())
237 bool DontMoveAcrossStore =
true;
238 if (!
MI.isSafeToMove(
nullptr, DontMoveAcrossStore)) {
244 if (!InstrDependenciesAllowIfConv(&
MI))
254 bool SSAIfConv::InstrDependenciesAllowIfConv(
MachineInstr *
I) {
256 if (MO.isRegMask()) {
265 if (MO.isDef() &&
Reg.isPhysical())
268 ClobberedRegUnits.
set(*Units);
270 if (!MO.readsReg() || !
Reg.isVirtual())
279 LLVM_DEBUG(
dbgs() <<
"Can't insert instructions below terminator.\n");
309 if (
I->isDebugInstr())
337 if (!InstrDependenciesAllowIfConv(&(*
I)))
345 auto Condition =
Cond;
346 if (ReversePredicate)
352 if (
I->isDebugInstr())
368 bool SSAIfConv::findInsertionPoint() {
379 if (InsertAfter.
count(&*
I)) {
390 if (!
Reg.isPhysical())
399 Reads.push_back(
Reg.asMCReg());
402 while (!Reads.empty())
405 if (ClobberedRegUnits.
test(*Units))
409 if (
I != FirstTerm &&
I->isTerminator())
416 dbgs() <<
"Would clobber";
419 dbgs() <<
" live before " << *
I;
468 if (!
Tail->livein_empty()) {
495 LLVM_DEBUG(
dbgs() <<
"analyzeBranch didn't find conditional branch.\n");
502 LLVM_DEBUG(
dbgs() <<
"analyzeBranch found an unconditional branch.\n");
508 FBB =
TBB == Succ0 ? Succ1 : Succ0;
515 I !=
E &&
I->isPHI(); ++
I) {
517 PHIInfo &PI = PHIs.back();
519 for (
unsigned i = 1;
i != PI.PHI->getNumOperands();
i += 2) {
520 if (PI.PHI->getOperand(
i+1).getMBB() == TPred)
521 PI.TReg = PI.PHI->getOperand(
i).getReg();
522 if (PI.PHI->getOperand(
i+1).getMBB() == FPred)
523 PI.FReg = PI.PHI->getOperand(
i).getReg();
529 if (!
TII->canInsertSelect(*Head,
Cond, PI.PHI->getOperand(0).getReg(),
530 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
539 ClobberedRegUnits.
reset();
543 if (FBB !=
Tail && !canPredicateInstrs(FBB))
548 if (FBB !=
Tail && !canSpeculateInstrs(FBB))
554 if (!findInsertionPoint())
593 return MO.isReg() && MO.getReg().isPhysical();
598 if (!
TII->produceSameValue(*TDef, *FDef, &
MRI))
604 if (TIdx == -1 || FIdx == -1)
613 void SSAIfConv::replacePHIInstrs() {
614 assert(
Tail->pred_size() == 2 &&
"Cannot replace PHIs");
616 assert(FirstTerm != Head->
end() &&
"No terminators");
617 DebugLoc HeadDL = FirstTerm->getDebugLoc();
620 for (
unsigned i = 0,
e = PHIs.size();
i !=
e; ++
i) {
621 PHIInfo &PI = PHIs[
i];
623 Register DstReg = PI.PHI->getOperand(0).getReg();
627 BuildMI(*Head, FirstTerm, HeadDL,
TII->get(TargetOpcode::COPY), DstReg)
630 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg,
Cond, PI.TReg,
634 PI.PHI->eraseFromParent();
642 void SSAIfConv::rewritePHIOperands() {
644 assert(FirstTerm != Head->
end() &&
"No terminators");
645 DebugLoc HeadDL = FirstTerm->getDebugLoc();
648 for (
unsigned i = 0,
e = PHIs.size();
i !=
e; ++
i) {
649 PHIInfo &PI = PHIs[
i];
658 Register PHIDst = PI.PHI->getOperand(0).getReg();
660 TII->insertSelect(*Head, FirstTerm, HeadDL,
661 DstReg,
Cond, PI.TReg, PI.FReg);
666 for (
unsigned i = PI.PHI->getNumOperands();
i != 1;
i -= 2) {
668 if (
MBB == getTPred()) {
669 PI.PHI->getOperand(
i-1).setMBB(Head);
670 PI.PHI->getOperand(
i-2).setReg(DstReg);
671 }
else if (
MBB == getFPred()) {
672 PI.PHI->removeOperand(
i-1);
673 PI.PHI->removeOperand(
i-2);
687 assert(Head &&
Tail &&
TBB && FBB &&
"Call canConvertIf first.");
698 PredicateBlock(
TBB,
false);
703 PredicateBlock(FBB,
true);
707 bool ExtraPreds =
Tail->pred_size() != 2;
709 rewritePHIOperands();
729 RemovedBlocks.push_back(
TBB);
733 RemovedBlocks.push_back(FBB);
745 RemovedBlocks.push_back(
Tail);
746 Tail->eraseFromParent();
778 StringRef getPassName()
const override {
return "Early If-Conversion"; }
782 void invalidateTraces();
783 bool shouldConvertIf();
791 "Early If Converter",
false,
false)
798 void EarlyIfConverter::getAnalysisUsage(
AnalysisUsage &AU)
const {
817 for (
auto *
B : Removed) {
819 assert(Node != HeadNode &&
"Cannot erase the head node");
820 while (Node->getNumChildren()) {
821 assert(Node->getBlock() == IfConv.Tail &&
"Unexpected children");
835 for (
auto *
B : Removed)
841 void EarlyIfConverter::invalidateTraces() {
842 Traces->verifyAnalysis();
843 Traces->invalidate(IfConv.Head);
844 Traces->invalidate(IfConv.Tail);
845 Traces->invalidate(IfConv.TBB);
846 Traces->invalidate(IfConv.FBB);
847 Traces->verifyAnalysis();
852 if (Delta < 0 && Cyc + Delta > Cyc)
864 return R <<
ore::NV(
C.Key,
C.Value) << (
C.Value == 1 ?
" cycle" :
" cycles");
871 bool EarlyIfConverter::shouldConvertIf() {
886 unsigned CritLimit = SchedModel.MispredictPenalty/2;
895 if (IfConv.TBB != IfConv.Tail)
896 ExtraBlocks.push_back(IfConv.TBB);
899 <<
", minimal critical path " << MinCrit <<
'\n');
900 if (ResLength > MinCrit + CritLimit) {
905 R <<
"did not if-convert branch: the resulting critical path ("
906 << Cycles{
"ResLength", ResLength}
907 <<
") would extend the shorter leg's critical path ("
908 << Cycles{
"MinCrit", MinCrit} <<
") by more than the threshold of "
909 << Cycles{
"CritLimit", CritLimit}
910 <<
", which cannot be hidden by available ILP.";
920 unsigned BranchDepth =
927 struct CriticalPathInfo {
931 CriticalPathInfo
Cond{};
932 CriticalPathInfo TBlock{};
933 CriticalPathInfo FBlock{};
934 bool ShouldConvert =
true;
935 for (
unsigned i = 0,
e = IfConv.PHIs.size();
i !=
e; ++
i) {
936 SSAIfConv::PHIInfo &PI = IfConv.PHIs[
i];
942 unsigned CondDepth =
adjCycles(BranchDepth, PI.CondCycles);
944 unsigned Extra = CondDepth -
MaxDepth;
946 if (Extra >
Cond.Extra)
947 Cond = {Extra, CondDepth};
948 if (Extra > CritLimit) {
950 ShouldConvert =
false;
959 if (Extra > TBlock.Extra)
960 TBlock = {Extra, TDepth};
961 if (Extra > CritLimit) {
963 ShouldConvert =
false;
972 if (Extra > FBlock.Extra)
973 FBlock = {Extra, FDepth};
974 if (Extra > CritLimit) {
976 ShouldConvert =
false;
984 const CriticalPathInfo
Short = TBlock.Extra > FBlock.Extra ? FBlock : TBlock;
985 const CriticalPathInfo
Long = TBlock.Extra > FBlock.Extra ? TBlock : FBlock;
991 R <<
"performing if-conversion on branch: the condition adds "
992 << Cycles{
"CondCycles",
Cond.Extra} <<
" to the critical path";
994 R <<
", and the short leg adds another "
995 << Cycles{
"ShortCycles",
Short.Extra};
997 R <<
", and the long leg adds another "
998 << Cycles{
"LongCycles",
Long.Extra};
999 R <<
", each staying under the threshold of "
1000 << Cycles{
"CritLimit", CritLimit} <<
".";
1007 R <<
"did not if-convert branch: the condition would add "
1008 << Cycles{
"CondCycles",
Cond.Extra} <<
" to the critical path";
1009 if (
Cond.Extra > CritLimit)
1010 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1011 if (
Short.Extra > 0) {
1012 R <<
", and the short leg would add another "
1013 << Cycles{
"ShortCycles",
Short.Extra};
1014 if (
Short.Extra > CritLimit)
1015 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1017 if (
Long.Extra > 0) {
1018 R <<
", and the long leg would add another "
1019 << Cycles{
"LongCycles",
Long.Extra};
1020 if (
Long.Extra > CritLimit)
1021 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1028 return ShouldConvert;
1034 bool Changed =
false;
1035 while (IfConv.canConvertIf(
MBB) && shouldConvertIf()) {
1039 IfConv.convertIf(RemovedBlocks);
1041 updateDomTree(DomTree, IfConv, RemovedBlocks);
1042 updateLoops(
Loops, RemovedBlocks);
1048 LLVM_DEBUG(
dbgs() <<
"********** EARLY IF-CONVERSION **********\n"
1049 <<
"********** Function: " << MF.
getName() <<
'\n');
1062 DomTree = &getAnalysis<MachineDominatorTree>();
1063 Loops = getAnalysisIfAvailable<MachineLoopInfo>();
1064 Traces = &getAnalysis<MachineTraceMetrics>();
1067 bool Changed =
false;
1068 IfConv.runOnMachineFunction(MF);
1075 if (tryConvertIf(DomNode->getBlock()))
1101 StringRef getPassName()
const override {
return "Early If-predicator"; }
1105 bool shouldConvertIf();
1110 #define DEBUG_TYPE "early-if-predicator"
1122 void EarlyIfPredicator::getAnalysisUsage(
AnalysisUsage &AU)
const {
1132 bool EarlyIfPredicator::shouldConvertIf() {
1133 auto TrueProbability = MBPI->getEdgeProbability(IfConv.Head, IfConv.TBB);
1134 if (IfConv.isTriangle()) {
1136 (IfConv.TBB == IfConv.Tail) ? *IfConv.FBB : *IfConv.TBB;
1138 unsigned ExtraPredCost = 0;
1139 unsigned Cycles = 0;
1141 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1143 Cycles += NumCycles - 1;
1144 ExtraPredCost +=
TII->getPredicationCost(
I);
1150 unsigned TExtra = 0;
1151 unsigned FExtra = 0;
1152 unsigned TCycle = 0;
1153 unsigned FCycle = 0;
1155 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1157 TCycle += NumCycles - 1;
1158 TExtra +=
TII->getPredicationCost(
I);
1161 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1163 FCycle += NumCycles - 1;
1164 FExtra +=
TII->getPredicationCost(
I);
1167 FCycle, FExtra, TrueProbability);
1173 bool Changed =
false;
1174 while (IfConv.canConvertIf(
MBB,
true) && shouldConvertIf()) {
1177 IfConv.convertIf(RemovedBlocks,
true);
1179 updateDomTree(DomTree, IfConv, RemovedBlocks);
1180 updateLoops(
Loops, RemovedBlocks);
1186 LLVM_DEBUG(
dbgs() <<
"********** EARLY IF-PREDICATOR **********\n"
1187 <<
"********** Function: " << MF.
getName() <<
'\n');
1195 SchedModel.init(&STI);
1196 DomTree = &getAnalysis<MachineDominatorTree>();
1197 Loops = getAnalysisIfAvailable<MachineLoopInfo>();
1198 MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
1200 bool Changed =
false;
1201 IfConv.runOnMachineFunction(MF);
1208 if (tryConvertIf(DomNode->getBlock()))
unsigned succ_size() const
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
This is an optimization pass for GlobalISel generic memory operations.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
unsigned Depth
Earliest issue cycle as determined by data dependencies and instruction latencies from the beginning ...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
virtual const TargetInstrInfo * getInstrInfo() const
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
void clear()
clear - Removes all bits from the bitvector.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Reg
All possible values of the reg field in the ModR/M byte.
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
@ TS_MinInstrCount
Select the trace through a block that has the fewest instructions.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static unsigned InstrCount
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
INITIALIZE_PASS_BEGIN(EarlyIfConverter, DEBUG_TYPE, "Early If Converter", false, false) INITIALIZE_PASS_END(EarlyIfConverter
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
DiagnosticInfoOptimizationBase::Argument NV
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
bool empty() const
Returns true if the set is empty.
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
unsigned getCriticalPath() const
Return the length of the (data dependency) critical path through the trace.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
InstrCycles getInstrCycles(const MachineInstr &MI) const
Return the depth and height of MI.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
unsigned pred_size() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Represent the analysis usage information of a pass.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
void changeImmediateDominator(MachineBasicBlock *N, MachineBasicBlock *NewIDom)
changeImmediateDominator - This method is used to update the dominator tree information when a node's...
const HexagonInstrInfo * TII
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
STATISTIC(NumFunctions, "Total number of functions")
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
A trace represents a plausible sequence of executed basic blocks that passes through the current basi...
A set of register units used to track register liveness.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Provide an instruction scheduling machine model to CodeGen passes.
Representation of each machine instruction.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
initializer< Ty > init(const Ty &Val)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
succ_iterator succ_begin()
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getResourceLength(ArrayRef< const MachineBasicBlock * > Extrablocks=std::nullopt, ArrayRef< const MCSchedClassDesc * > ExtraInstrs=std::nullopt, ArrayRef< const MCSchedClassDesc * > RemoveInstrs=std::nullopt) const
Return the resource length of the trace.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
void eraseNode(MachineBasicBlock *BB)
eraseNode - Removes a node from the dominator tree.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
SmallVector< MachineOperand, 4 > Cond
StringRef - Represent a constant reference to a string, i.e.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
const MachineBasicBlock * getParent() const
Base class for the actual dominator tree node.
this could be done in SelectionDAGISel along with other special for
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static const unsigned MaxDepth
bool test(unsigned Idx) const
A trace ensemble is a collection of traces selected using the same strategy, for example 'minimum res...
Function & getFunction()
Return the LLVM function that this machine code represents.
static cl::opt< unsigned > BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden, cl::desc("Maximum number of instructions per speculated block."))
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
iterator_range< po_iterator< T > > post_order(const T &G)
static unsigned adjCycles(unsigned Cyc, int Delta)
Machine model for scheduling, bundling, and heuristics.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
bool livein_empty() const
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
unsigned getInstrSlack(const MachineInstr &MI) const
Return the slack of MI.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
static bool hasSameValue(const MachineRegisterInfo &MRI, const TargetInstrInfo *TII, Register TReg, Register FReg)
MachineInstrBuilder MachineInstrBuilder & DefMI
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
void clear()
Clears the set.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
unsigned getPHIDepth(const MachineInstr &PHI) const
Return the Depth of a PHI instruction in a trace center block successor.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
static cl::opt< bool > Stress("stress-early-ifcvt", cl::Hidden, cl::desc("Turn all knobs to 11"))
char & EarlyIfPredicatorID
EarlyIfPredicator - This pass performs if-conversion on SSA form by predicating if/else block and ins...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.