43#define DEBUG_TYPE "early-ifcvt"
49 cl::desc(
"Maximum number of instructions per speculated block."));
56STATISTIC(NumDiamondsConv,
"Number of diamonds converted");
58STATISTIC(NumTrianglesConv,
"Number of triangles converted");
102 bool isTriangle()
const {
return TBB ==
Tail || FBB ==
Tail; }
113 unsigned TReg = 0, FReg = 0;
115 int CondCycles = 0, TCycles = 0, FCycles = 0;
157 bool findInsertionPoint();
160 void replacePHIInstrs();
163 void rewritePHIOperands();
173 ClobberedRegUnits.
clear();
174 ClobberedRegUnits.
resize(
TRI->getNumRegUnits());
186 bool Predicate =
false);
213 if (
MI.isDebugInstr())
237 bool DontMoveAcrossStore =
true;
238 if (!
MI.isSafeToMove(
nullptr, DontMoveAcrossStore)) {
244 if (!InstrDependenciesAllowIfConv(&
MI))
254bool SSAIfConv::InstrDependenciesAllowIfConv(
MachineInstr *
I) {
256 if (MO.isRegMask()) {
265 if (MO.isDef() &&
Reg.isPhysical())
267 ClobberedRegUnits.
set(Unit);
269 if (!MO.readsReg() || !
Reg.isVirtual())
278 LLVM_DEBUG(
dbgs() <<
"Can't insert instructions below terminator.\n");
308 if (
I->isDebugInstr())
336 if (!InstrDependenciesAllowIfConv(&(*
I)))
344 auto Condition =
Cond;
345 if (ReversePredicate) {
347 assert(CanRevCond &&
"Reversed predicate is not supported");
354 if (
I->isDebugInstr())
370bool SSAIfConv::findInsertionPoint() {
381 if (InsertAfter.
count(&*
I)) {
392 if (!
Reg.isPhysical())
403 while (!Reads.
empty())
405 if (ClobberedRegUnits.
test(Unit))
409 if (
I != FirstTerm &&
I->isTerminator())
416 dbgs() <<
"Would clobber";
419 dbgs() <<
" live before " << *
I;
468 if (!
Tail->livein_empty()) {
481 if (!Predicate && (
Tail->empty() || !
Tail->front().isPHI())) {
495 LLVM_DEBUG(
dbgs() <<
"analyzeBranch didn't find conditional branch.\n");
502 LLVM_DEBUG(
dbgs() <<
"analyzeBranch found an unconditional branch.\n");
508 FBB =
TBB == Succ0 ? Succ1 : Succ0;
515 I != E &&
I->isPHI(); ++
I) {
517 PHIInfo &PI = PHIs.
back();
519 for (
unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
520 if (PI.PHI->getOperand(i+1).getMBB() == TPred)
521 PI.TReg = PI.PHI->getOperand(i).getReg();
522 if (PI.PHI->getOperand(i+1).getMBB() == FPred)
523 PI.FReg = PI.PHI->getOperand(i).getReg();
529 if (!
TII->canInsertSelect(*Head,
Cond, PI.PHI->getOperand(0).getReg(),
530 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
539 ClobberedRegUnits.
reset();
543 if (FBB !=
Tail && !canPredicateInstrs(FBB))
548 if (FBB !=
Tail && !canSpeculateInstrs(FBB))
554 if (!findInsertionPoint())
593 return MO.isReg() && MO.getReg().isPhysical();
598 if (!
TII->produceSameValue(*TDef, *FDef, &
MRI))
604 if (TIdx == -1 || FIdx == -1)
613void SSAIfConv::replacePHIInstrs() {
614 assert(
Tail->pred_size() == 2 &&
"Cannot replace PHIs");
616 assert(FirstTerm != Head->
end() &&
"No terminators");
617 DebugLoc HeadDL = FirstTerm->getDebugLoc();
620 for (PHIInfo &PI : PHIs) {
622 Register DstReg = PI.PHI->getOperand(0).getReg();
626 BuildMI(*Head, FirstTerm, HeadDL,
TII->get(TargetOpcode::COPY), DstReg)
629 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg,
Cond, PI.TReg,
633 PI.PHI->eraseFromParent();
641void SSAIfConv::rewritePHIOperands() {
643 assert(FirstTerm != Head->
end() &&
"No terminators");
644 DebugLoc HeadDL = FirstTerm->getDebugLoc();
647 for (PHIInfo &PI : PHIs) {
656 Register PHIDst = PI.PHI->getOperand(0).getReg();
657 DstReg =
MRI->createVirtualRegister(
MRI->getRegClass(PHIDst));
658 TII->insertSelect(*Head, FirstTerm, HeadDL,
659 DstReg,
Cond, PI.TReg, PI.FReg);
664 for (
unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {
666 if (
MBB == getTPred()) {
667 PI.PHI->getOperand(i-1).setMBB(Head);
668 PI.PHI->getOperand(i-2).setReg(DstReg);
669 }
else if (
MBB == getFPred()) {
670 PI.PHI->removeOperand(i-1);
671 PI.PHI->removeOperand(i-2);
685 assert(Head &&
Tail &&
TBB && FBB &&
"Call canConvertIf first.");
696 PredicateBlock(
TBB,
false);
701 PredicateBlock(FBB,
true);
705 bool ExtraPreds =
Tail->pred_size() != 2;
707 rewritePHIOperands();
744 Tail->eraseFromParent();
780 void invalidateTraces();
781 bool shouldConvertIf();
785char EarlyIfConverter::ID = 0;
789 "Early If Converter",
false,
false)
796void EarlyIfConverter::getAnalysisUsage(
AnalysisUsage &AU)
const {
815 for (
auto *
B : Removed) {
817 assert(
Node != HeadNode &&
"Cannot erase the head node");
818 while (
Node->getNumChildren()) {
819 assert(
Node->getBlock() == IfConv.Tail &&
"Unexpected children");
831 for (
auto *
B : Removed)
837void EarlyIfConverter::invalidateTraces() {
838 Traces->verifyAnalysis();
839 Traces->invalidate(IfConv.Head);
840 Traces->invalidate(IfConv.Tail);
841 Traces->invalidate(IfConv.TBB);
842 Traces->invalidate(IfConv.FBB);
843 Traces->verifyAnalysis();
848 if (Delta < 0 && Cyc + Delta > Cyc)
860 return R <<
ore::NV(
C.Key,
C.Value) << (
C.Value == 1 ?
" cycle" :
" cycles");
867bool EarlyIfConverter::shouldConvertIf() {
881 if (!MO.isReg() || !MO.isUse())
883 Register Reg = MO.getReg();
884 if (Register::isPhysicalRegister(Reg))
887 MachineInstr *Def = MRI->getVRegDef(Reg);
888 return CurrentLoop->isLoopInvariant(*Def) ||
889 all_of(Def->operands(), [&](MachineOperand &Op) {
892 if (!MO.isReg() || !MO.isUse())
894 Register Reg = MO.getReg();
895 if (Register::isPhysicalRegister(Reg))
898 MachineInstr *Def = MRI->getVRegDef(Reg);
899 return CurrentLoop->isLoopInvariant(*Def);
905 MinInstr = Traces->getEnsemble(MachineTraceStrategy::TS_MinInstrCount);
914 unsigned CritLimit = SchedModel.MispredictPenalty/2;
923 if (IfConv.TBB != IfConv.Tail)
927 <<
", minimal critical path " << MinCrit <<
'\n');
928 if (ResLength > MinCrit + CritLimit) {
933 R <<
"did not if-convert branch: the resulting critical path ("
934 << Cycles{
"ResLength", ResLength}
935 <<
") would extend the shorter leg's critical path ("
936 << Cycles{
"MinCrit", MinCrit} <<
") by more than the threshold of "
937 << Cycles{
"CritLimit", CritLimit}
938 <<
", which cannot be hidden by available ILP.";
948 unsigned BranchDepth =
955 struct CriticalPathInfo {
959 CriticalPathInfo
Cond{};
960 CriticalPathInfo TBlock{};
961 CriticalPathInfo FBlock{};
962 bool ShouldConvert =
true;
963 for (SSAIfConv::PHIInfo &PI : IfConv.PHIs) {
969 unsigned CondDepth =
adjCycles(BranchDepth, PI.CondCycles);
971 unsigned Extra = CondDepth -
MaxDepth;
973 if (Extra >
Cond.Extra)
974 Cond = {Extra, CondDepth};
975 if (Extra > CritLimit) {
977 ShouldConvert =
false;
986 if (Extra > TBlock.Extra)
987 TBlock = {Extra, TDepth};
988 if (Extra > CritLimit) {
990 ShouldConvert =
false;
999 if (Extra > FBlock.Extra)
1000 FBlock = {Extra, FDepth};
1001 if (Extra > CritLimit) {
1003 ShouldConvert =
false;
1011 const CriticalPathInfo
Short = TBlock.Extra > FBlock.Extra ? FBlock : TBlock;
1012 const CriticalPathInfo
Long = TBlock.Extra > FBlock.Extra ? TBlock : FBlock;
1014 if (ShouldConvert) {
1018 R <<
"performing if-conversion on branch: the condition adds "
1019 << Cycles{
"CondCycles",
Cond.Extra} <<
" to the critical path";
1020 if (
Short.Extra > 0)
1021 R <<
", and the short leg adds another "
1022 << Cycles{
"ShortCycles",
Short.Extra};
1024 R <<
", and the long leg adds another "
1025 << Cycles{
"LongCycles",
Long.Extra};
1026 R <<
", each staying under the threshold of "
1027 << Cycles{
"CritLimit", CritLimit} <<
".";
1034 R <<
"did not if-convert branch: the condition would add "
1035 << Cycles{
"CondCycles",
Cond.Extra} <<
" to the critical path";
1036 if (
Cond.Extra > CritLimit)
1037 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1038 if (
Short.Extra > 0) {
1039 R <<
", and the short leg would add another "
1040 << Cycles{
"ShortCycles",
Short.Extra};
1041 if (
Short.Extra > CritLimit)
1042 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1044 if (
Long.Extra > 0) {
1045 R <<
", and the long leg would add another "
1046 << Cycles{
"LongCycles",
Long.Extra};
1047 if (
Long.Extra > CritLimit)
1048 R <<
" exceeding the limit of " << Cycles{
"CritLimit", CritLimit};
1055 return ShouldConvert;
1061 bool Changed =
false;
1062 while (IfConv.canConvertIf(
MBB) && shouldConvertIf()) {
1066 IfConv.convertIf(RemovedBlocks);
1068 updateDomTree(DomTree, IfConv, RemovedBlocks);
1069 updateLoops(
Loops, RemovedBlocks);
1075 LLVM_DEBUG(
dbgs() <<
"********** EARLY IF-CONVERSION **********\n"
1076 <<
"********** Function: " << MF.
getName() <<
'\n');
1089 DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1090 Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
1091 Traces = &getAnalysis<MachineTraceMetrics>();
1094 bool Changed =
false;
1095 IfConv.runOnMachineFunction(MF);
1102 if (tryConvertIf(DomNode->getBlock()))
1132 bool shouldConvertIf();
1137#define DEBUG_TYPE "early-if-predicator"
1139char EarlyIfPredicator::ID = 0;
1149void EarlyIfPredicator::getAnalysisUsage(
AnalysisUsage &AU)
const {
1159bool EarlyIfPredicator::shouldConvertIf() {
1160 auto TrueProbability = MBPI->getEdgeProbability(IfConv.Head, IfConv.TBB);
1161 if (IfConv.isTriangle()) {
1163 (IfConv.TBB == IfConv.Tail) ? *IfConv.FBB : *IfConv.TBB;
1165 unsigned ExtraPredCost = 0;
1166 unsigned Cycles = 0;
1168 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1170 Cycles += NumCycles - 1;
1171 ExtraPredCost +=
TII->getPredicationCost(
I);
1177 unsigned TExtra = 0;
1178 unsigned FExtra = 0;
1179 unsigned TCycle = 0;
1180 unsigned FCycle = 0;
1182 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1184 TCycle += NumCycles - 1;
1185 TExtra +=
TII->getPredicationCost(
I);
1188 unsigned NumCycles = SchedModel.computeInstrLatency(&
I,
false);
1190 FCycle += NumCycles - 1;
1191 FExtra +=
TII->getPredicationCost(
I);
1194 FCycle, FExtra, TrueProbability);
1200 bool Changed =
false;
1201 while (IfConv.canConvertIf(
MBB,
true) && shouldConvertIf()) {
1204 IfConv.convertIf(RemovedBlocks,
true);
1206 updateDomTree(DomTree, IfConv, RemovedBlocks);
1207 updateLoops(
Loops, RemovedBlocks);
1213 LLVM_DEBUG(
dbgs() <<
"********** EARLY IF-PREDICATOR **********\n"
1214 <<
"********** Function: " << MF.
getName() <<
'\n');
1222 SchedModel.init(&STI);
1223 DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
1224 Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
1225 MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
1227 bool Changed =
false;
1228 IfConv.runOnMachineFunction(MF);
1235 if (tryConvertIf(DomNode->getBlock()))
unsigned const MachineRegisterInfo * MRI
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
MachineInstrBuilder MachineInstrBuilder & DefMI
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static unsigned InstrCount
static bool hasSameValue(const MachineRegisterInfo &MRI, const TargetInstrInfo *TII, Register TReg, Register FReg)
static unsigned adjCycles(unsigned Cyc, int Delta)
static cl::opt< bool > Stress("stress-early-ifcvt", cl::Hidden, cl::desc("Turn all knobs to 11"))
static cl::opt< unsigned > BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden, cl::desc("Maximum number of instructions per speculated block."))
const HexagonInstrInfo * TII
static const unsigned MaxDepth
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SparseSet class derived from the version described in Briggs,...
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
Represent the analysis usage information of a pass.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
Base class for the actual dominator tree node.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Remove the branching code at the end of the specific MBB.
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Reverses the branch condition of the specified condition list, returning false on success and true if...
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override
Convert the instruction into a predicated instruction.
bool isPredicable(const MachineInstr &MI) const override
Return true if the specified instruction can be predicated.
A set of register units used to track register liveness.
bool empty() const
Returns true if the set is empty.
void clear()
Clears the set.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
unsigned pred_size() const
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
succ_iterator succ_begin()
bool livein_empty() const
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
Analysis pass which computes a MachineDominatorTree.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
void eraseNode(MachineBasicBlock *BB)
eraseNode - Removes a node from the dominator tree.
void changeImmediateDominator(MachineBasicBlock *N, MachineBasicBlock *NewIDom)
changeImmediateDominator - This method is used to update the dominator tree information when a node's...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
const MachineBasicBlock * getParent() const
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
iterator_range< mop_iterator > uses()
Returns a range that includes all operands that are register uses.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, bool isDead=false, bool Overlap=false) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A trace ensemble is a collection of traces selected using the same strategy, for example 'minimum res...
A trace represents a plausible sequence of executed basic blocks that passes through the current basi...
InstrCycles getInstrCycles(const MachineInstr &MI) const
Return the depth and height of MI.
unsigned getInstrSlack(const MachineInstr &MI) const
Return the slack of MI.
unsigned getResourceLength(ArrayRef< const MachineBasicBlock * > Extrablocks=std::nullopt, ArrayRef< const MCSchedClassDesc * > ExtraInstrs=std::nullopt, ArrayRef< const MCSchedClassDesc * > RemoveInstrs=std::nullopt) const
Return the resource length of the trace.
unsigned getCriticalPath() const
Return the length of the (data dependency) critical path through the trace.
unsigned getPHIDepth(const MachineInstr &PHI) const
Return the Depth of a PHI instruction in a trace center block successor.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
SparseSet - Fast set implementation for objects that can be identified by small unsigned keys.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual bool enableEarlyIfConversion() const
Enable the use of the early if conversion pass.
LLVM Value Representation.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
@ C
The default llvm calling convention, compatible with C.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
iterator_range< po_iterator< T > > post_order(const T &G)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
char & EarlyIfPredicatorID
EarlyIfPredicator - This pass performs if-conversion on SSA form by predicating if/else block and ins...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Machine model for scheduling, bundling, and heuristics.
unsigned Depth
Earliest issue cycle as determined by data dependencies and instruction latencies from the beginning ...