LLVM  14.0.0git
HexagonHardwareLoops.cpp
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1 //===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This pass identifies loops where we can generate the Hexagon hardware
10 // loop instruction. The hardware loop can perform loop branches with a
11 // zero-cycle overhead.
12 //
13 // The pattern that defines the induction variable can changed depending on
14 // prior optimizations. For example, the IndVarSimplify phase run by 'opt'
15 // normalizes induction variables, and the Loop Strength Reduction pass
16 // run by 'llc' may also make changes to the induction variable.
17 // The pattern detected by this phase is due to running Strength Reduction.
18 //
19 // Criteria for hardware loops:
20 // - Countable loops (w/ ind. var for a trip count)
21 // - Assumes loops are normalized by IndVarSimplify
22 // - Try inner-most loops first
23 // - No function calls in loops.
24 //
25 //===----------------------------------------------------------------------===//
26 
27 #include "HexagonInstrInfo.h"
28 #include "HexagonSubtarget.h"
29 #include "llvm/ADT/ArrayRef.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/StringRef.h"
45 #include "llvm/IR/Constants.h"
46 #include "llvm/IR/DebugLoc.h"
47 #include "llvm/InitializePasses.h"
48 #include "llvm/Pass.h"
50 #include "llvm/Support/Debug.h"
54 #include <cassert>
55 #include <cstdint>
56 #include <cstdlib>
57 #include <iterator>
58 #include <map>
59 #include <set>
60 #include <string>
61 #include <utility>
62 #include <vector>
63 
64 using namespace llvm;
65 
66 #define DEBUG_TYPE "hwloops"
67 
68 #ifndef NDEBUG
69 static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1));
70 
71 // Option to create preheader only for a specific function.
72 static cl::opt<std::string> PHFn("hexagon-hwloop-phfn", cl::Hidden,
73  cl::init(""));
74 #endif
75 
76 // Option to create a preheader if one doesn't exist.
77 static cl::opt<bool> HWCreatePreheader("hexagon-hwloop-preheader",
78  cl::Hidden, cl::init(true),
79  cl::desc("Add a preheader to a hardware loop if one doesn't exist"));
80 
81 // Turn it off by default. If a preheader block is not created here, the
82 // software pipeliner may be unable to find a block suitable to serve as
83 // a preheader. In that case SWP will not run.
84 static cl::opt<bool> SpecPreheader("hwloop-spec-preheader", cl::init(false),
85  cl::Hidden, cl::ZeroOrMore, cl::desc("Allow speculation of preheader "
86  "instructions"));
87 
88 STATISTIC(NumHWLoops, "Number of loops converted to hardware loops");
89 
90 namespace llvm {
91 
94 
95 } // end namespace llvm
96 
97 namespace {
98 
99  class CountValue;
100 
101  struct HexagonHardwareLoops : public MachineFunctionPass {
102  MachineLoopInfo *MLI;
105  const HexagonInstrInfo *TII;
106  const HexagonRegisterInfo *TRI;
107 #ifndef NDEBUG
108  static int Counter;
109 #endif
110 
111  public:
112  static char ID;
113 
114  HexagonHardwareLoops() : MachineFunctionPass(ID) {}
115 
116  bool runOnMachineFunction(MachineFunction &MF) override;
117 
118  StringRef getPassName() const override { return "Hexagon Hardware Loops"; }
119 
120  void getAnalysisUsage(AnalysisUsage &AU) const override {
124  }
125 
126  private:
127  using LoopFeederMap = std::map<unsigned, MachineInstr *>;
128 
129  /// Kinds of comparisons in the compare instructions.
130  struct Comparison {
131  enum Kind {
132  EQ = 0x01,
133  NE = 0x02,
134  L = 0x04,
135  G = 0x08,
136  U = 0x40,
137  LTs = L,
138  LEs = L | EQ,
139  GTs = G,
140  GEs = G | EQ,
141  LTu = L | U,
142  LEu = L | EQ | U,
143  GTu = G | U,
144  GEu = G | EQ | U
145  };
146 
147  static Kind getSwappedComparison(Kind Cmp) {
148  assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator");
149  if ((Cmp & L) || (Cmp & G))
150  return (Kind)(Cmp ^ (L|G));
151  return Cmp;
152  }
153 
154  static Kind getNegatedComparison(Kind Cmp) {
155  if ((Cmp & L) || (Cmp & G))
156  return (Kind)((Cmp ^ (L | G)) ^ EQ);
157  if ((Cmp & NE) || (Cmp & EQ))
158  return (Kind)(Cmp ^ (EQ | NE));
159  return (Kind)0;
160  }
161 
162  static bool isSigned(Kind Cmp) {
163  return (Cmp & (L | G) && !(Cmp & U));
164  }
165 
166  static bool isUnsigned(Kind Cmp) {
167  return (Cmp & U);
168  }
169  };
170 
171  /// Find the register that contains the loop controlling
172  /// induction variable.
173  /// If successful, it will return true and set the \p Reg, \p IVBump
174  /// and \p IVOp arguments. Otherwise it will return false.
175  /// The returned induction register is the register R that follows the
176  /// following induction pattern:
177  /// loop:
178  /// R = phi ..., [ R.next, LatchBlock ]
179  /// R.next = R + #bump
180  /// if (R.next < #N) goto loop
181  /// IVBump is the immediate value added to R, and IVOp is the instruction
182  /// "R.next = R + #bump".
183  bool findInductionRegister(MachineLoop *L, unsigned &Reg,
184  int64_t &IVBump, MachineInstr *&IVOp) const;
185 
186  /// Return the comparison kind for the specified opcode.
187  Comparison::Kind getComparisonKind(unsigned CondOpc,
188  MachineOperand *InitialValue,
189  const MachineOperand *Endvalue,
190  int64_t IVBump) const;
191 
192  /// Analyze the statements in a loop to determine if the loop
193  /// has a computable trip count and, if so, return a value that represents
194  /// the trip count expression.
195  CountValue *getLoopTripCount(MachineLoop *L,
197 
198  /// Return the expression that represents the number of times
199  /// a loop iterates. The function takes the operands that represent the
200  /// loop start value, loop end value, and induction value. Based upon
201  /// these operands, the function attempts to compute the trip count.
202  /// If the trip count is not directly available (as an immediate value,
203  /// or a register), the function will attempt to insert computation of it
204  /// to the loop's preheader.
205  CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start,
206  const MachineOperand *End, unsigned IVReg,
207  int64_t IVBump, Comparison::Kind Cmp) const;
208 
209  /// Return true if the instruction is not valid within a hardware
210  /// loop.
211  bool isInvalidLoopOperation(const MachineInstr *MI,
212  bool IsInnerHWLoop) const;
213 
214  /// Return true if the loop contains an instruction that inhibits
215  /// using the hardware loop.
216  bool containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const;
217 
218  /// Given a loop, check if we can convert it to a hardware loop.
219  /// If so, then perform the conversion and return true.
220  bool convertToHardwareLoop(MachineLoop *L, bool &L0used, bool &L1used);
221 
222  /// Return true if the instruction is now dead.
223  bool isDead(const MachineInstr *MI,
224  SmallVectorImpl<MachineInstr *> &DeadPhis) const;
225 
226  /// Remove the instruction if it is now dead.
227  void removeIfDead(MachineInstr *MI);
228 
229  /// Make sure that the "bump" instruction executes before the
230  /// compare. We need that for the IV fixup, so that the compare
231  /// instruction would not use a bumped value that has not yet been
232  /// defined. If the instructions are out of order, try to reorder them.
233  bool orderBumpCompare(MachineInstr *BumpI, MachineInstr *CmpI);
234 
235  /// Return true if MO and MI pair is visited only once. If visited
236  /// more than once, this indicates there is recursion. In such a case,
237  /// return false.
238  bool isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI,
239  const MachineOperand *MO,
240  LoopFeederMap &LoopFeederPhi) const;
241 
242  /// Return true if the Phi may generate a value that may underflow,
243  /// or may wrap.
244  bool phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal,
246  LoopFeederMap &LoopFeederPhi) const;
247 
248  /// Return true if the induction variable may underflow an unsigned
249  /// value in the first iteration.
250  bool loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal,
251  const MachineOperand *EndVal,
253  LoopFeederMap &LoopFeederPhi) const;
254 
255  /// Check if the given operand has a compile-time known constant
256  /// value. Return true if yes, and false otherwise. When returning true, set
257  /// Val to the corresponding constant value.
258  bool checkForImmediate(const MachineOperand &MO, int64_t &Val) const;
259 
260  /// Check if the operand has a compile-time known constant value.
261  bool isImmediate(const MachineOperand &MO) const {
262  int64_t V;
263  return checkForImmediate(MO, V);
264  }
265 
266  /// Return the immediate for the specified operand.
267  int64_t getImmediate(const MachineOperand &MO) const {
268  int64_t V;
269  if (!checkForImmediate(MO, V))
270  llvm_unreachable("Invalid operand");
271  return V;
272  }
273 
274  /// Reset the given machine operand to now refer to a new immediate
275  /// value. Assumes that the operand was already referencing an immediate
276  /// value, either directly, or via a register.
277  void setImmediate(MachineOperand &MO, int64_t Val);
278 
279  /// Fix the data flow of the induction variable.
280  /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
281  /// |
282  /// +-> back to phi
283  /// where "bump" is the increment of the induction variable:
284  /// iv = iv + #const.
285  /// Due to some prior code transformations, the actual flow may look
286  /// like this:
287  /// phi -+-> bump ---> back to phi
288  /// |
289  /// +-> comparison-in-latch (against upper_bound-bump),
290  /// i.e. the comparison that controls the loop execution may be using
291  /// the value of the induction variable from before the increment.
292  ///
293  /// Return true if the loop's flow is the desired one (i.e. it's
294  /// either been fixed, or no fixing was necessary).
295  /// Otherwise, return false. This can happen if the induction variable
296  /// couldn't be identified, or if the value in the latch's comparison
297  /// cannot be adjusted to reflect the post-bump value.
298  bool fixupInductionVariable(MachineLoop *L);
299 
300  /// Given a loop, if it does not have a preheader, create one.
301  /// Return the block that is the preheader.
302  MachineBasicBlock *createPreheaderForLoop(MachineLoop *L);
303  };
304 
305  char HexagonHardwareLoops::ID = 0;
306 #ifndef NDEBUG
307  int HexagonHardwareLoops::Counter = 0;
308 #endif
309 
310  /// Abstraction for a trip count of a loop. A smaller version
311  /// of the MachineOperand class without the concerns of changing the
312  /// operand representation.
313  class CountValue {
314  public:
315  enum CountValueType {
316  CV_Register,
317  CV_Immediate
318  };
319 
320  private:
321  CountValueType Kind;
322  union Values {
323  struct {
324  unsigned Reg;
325  unsigned Sub;
326  } R;
327  unsigned ImmVal;
328  } Contents;
329 
330  public:
331  explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {
332  Kind = t;
333  if (Kind == CV_Register) {
334  Contents.R.Reg = v;
335  Contents.R.Sub = u;
336  } else {
337  Contents.ImmVal = v;
338  }
339  }
340 
341  bool isReg() const { return Kind == CV_Register; }
342  bool isImm() const { return Kind == CV_Immediate; }
343 
344  unsigned getReg() const {
345  assert(isReg() && "Wrong CountValue accessor");
346  return Contents.R.Reg;
347  }
348 
349  unsigned getSubReg() const {
350  assert(isReg() && "Wrong CountValue accessor");
351  return Contents.R.Sub;
352  }
353 
354  unsigned getImm() const {
355  assert(isImm() && "Wrong CountValue accessor");
356  return Contents.ImmVal;
357  }
358 
359  void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
360  if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
361  if (isImm()) { OS << Contents.ImmVal; }
362  }
363  };
364 
365 } // end anonymous namespace
366 
367 INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops",
368  "Hexagon Hardware Loops", false, false)
371 INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops",
372  "Hexagon Hardware Loops", false, false)
373 
375  return new HexagonHardwareLoops();
376 }
377 
378 bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
379  LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n");
380  if (skipFunction(MF.getFunction()))
381  return false;
382 
383  bool Changed = false;
384 
385  MLI = &getAnalysis<MachineLoopInfo>();
386  MRI = &MF.getRegInfo();
387  MDT = &getAnalysis<MachineDominatorTree>();
389  TII = HST.getInstrInfo();
390  TRI = HST.getRegisterInfo();
391 
392  for (auto &L : *MLI)
393  if (L->isOutermost()) {
394  bool L0Used = false;
395  bool L1Used = false;
396  Changed |= convertToHardwareLoop(L, L0Used, L1Used);
397  }
398 
399  return Changed;
400 }
401 
402 bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
403  unsigned &Reg,
404  int64_t &IVBump,
405  MachineInstr *&IVOp
406  ) const {
407  MachineBasicBlock *Header = L->getHeader();
408  MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
409  MachineBasicBlock *Latch = L->getLoopLatch();
410  MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
411  if (!Header || !Preheader || !Latch || !ExitingBlock)
412  return false;
413 
414  // This pair represents an induction register together with an immediate
415  // value that will be added to it in each loop iteration.
416  using RegisterBump = std::pair<unsigned, int64_t>;
417 
418  // Mapping: R.next -> (R, bump), where R, R.next and bump are derived
419  // from an induction operation
420  // R.next = R + bump
421  // where bump is an immediate value.
422  using InductionMap = std::map<unsigned, RegisterBump>;
423 
424  InductionMap IndMap;
425 
426  using instr_iterator = MachineBasicBlock::instr_iterator;
427 
428  for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
429  I != E && I->isPHI(); ++I) {
430  MachineInstr *Phi = &*I;
431 
432  // Have a PHI instruction. Get the operand that corresponds to the
433  // latch block, and see if is a result of an addition of form "reg+imm",
434  // where the "reg" is defined by the PHI node we are looking at.
435  for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
436  if (Phi->getOperand(i+1).getMBB() != Latch)
437  continue;
438 
439  Register PhiOpReg = Phi->getOperand(i).getReg();
440  MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
441 
442  if (DI->getDesc().isAdd()) {
443  // If the register operand to the add is the PHI we're looking at, this
444  // meets the induction pattern.
445  Register IndReg = DI->getOperand(1).getReg();
446  MachineOperand &Opnd2 = DI->getOperand(2);
447  int64_t V;
448  if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
449  Register UpdReg = DI->getOperand(0).getReg();
450  IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
451  }
452  }
453  } // for (i)
454  } // for (instr)
455 
457  MachineBasicBlock *TB = nullptr, *FB = nullptr;
458  bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
459  if (NotAnalyzed)
460  return false;
461 
462  unsigned PredR, PredPos, PredRegFlags;
463  if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
464  return false;
465 
466  MachineInstr *PredI = MRI->getVRegDef(PredR);
467  if (!PredI->isCompare())
468  return false;
469 
470  Register CmpReg1, CmpReg2;
471  int64_t CmpImm = 0, CmpMask = 0;
472  bool CmpAnalyzed =
473  TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);
474  // Fail if the compare was not analyzed, or it's not comparing a register
475  // with an immediate value. Not checking the mask here, since we handle
476  // the individual compare opcodes (including A4_cmpb*) later on.
477  if (!CmpAnalyzed)
478  return false;
479 
480  // Exactly one of the input registers to the comparison should be among
481  // the induction registers.
482  InductionMap::iterator IndMapEnd = IndMap.end();
483  InductionMap::iterator F = IndMapEnd;
484  if (CmpReg1 != 0) {
485  InductionMap::iterator F1 = IndMap.find(CmpReg1);
486  if (F1 != IndMapEnd)
487  F = F1;
488  }
489  if (CmpReg2 != 0) {
490  InductionMap::iterator F2 = IndMap.find(CmpReg2);
491  if (F2 != IndMapEnd) {
492  if (F != IndMapEnd)
493  return false;
494  F = F2;
495  }
496  }
497  if (F == IndMapEnd)
498  return false;
499 
500  Reg = F->second.first;
501  IVBump = F->second.second;
502  IVOp = MRI->getVRegDef(F->first);
503  return true;
504 }
505 
506 // Return the comparison kind for the specified opcode.
507 HexagonHardwareLoops::Comparison::Kind
508 HexagonHardwareLoops::getComparisonKind(unsigned CondOpc,
509  MachineOperand *InitialValue,
510  const MachineOperand *EndValue,
511  int64_t IVBump) const {
513  switch (CondOpc) {
514  case Hexagon::C2_cmpeq:
515  case Hexagon::C2_cmpeqi:
516  case Hexagon::C2_cmpeqp:
518  break;
519  case Hexagon::C4_cmpneq:
520  case Hexagon::C4_cmpneqi:
522  break;
523  case Hexagon::C2_cmplt:
524  Cmp = Comparison::LTs;
525  break;
526  case Hexagon::C2_cmpltu:
527  Cmp = Comparison::LTu;
528  break;
529  case Hexagon::C4_cmplte:
530  case Hexagon::C4_cmpltei:
531  Cmp = Comparison::LEs;
532  break;
533  case Hexagon::C4_cmplteu:
534  case Hexagon::C4_cmplteui:
535  Cmp = Comparison::LEu;
536  break;
537  case Hexagon::C2_cmpgt:
538  case Hexagon::C2_cmpgti:
539  case Hexagon::C2_cmpgtp:
540  Cmp = Comparison::GTs;
541  break;
542  case Hexagon::C2_cmpgtu:
543  case Hexagon::C2_cmpgtui:
544  case Hexagon::C2_cmpgtup:
545  Cmp = Comparison::GTu;
546  break;
547  case Hexagon::C2_cmpgei:
548  Cmp = Comparison::GEs;
549  break;
550  case Hexagon::C2_cmpgeui:
551  Cmp = Comparison::GEs;
552  break;
553  default:
554  return (Comparison::Kind)0;
555  }
556  return Cmp;
557 }
558 
559 /// Analyze the statements in a loop to determine if the loop has
560 /// a computable trip count and, if so, return a value that represents
561 /// the trip count expression.
562 ///
563 /// This function iterates over the phi nodes in the loop to check for
564 /// induction variable patterns that are used in the calculation for
565 /// the number of time the loop is executed.
566 CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
568  MachineBasicBlock *TopMBB = L->getTopBlock();
570  assert(PI != TopMBB->pred_end() &&
571  "Loop must have more than one incoming edge!");
572  MachineBasicBlock *Backedge = *PI++;
573  if (PI == TopMBB->pred_end()) // dead loop?
574  return nullptr;
575  MachineBasicBlock *Incoming = *PI++;
576  if (PI != TopMBB->pred_end()) // multiple backedges?
577  return nullptr;
578 
579  // Make sure there is one incoming and one backedge and determine which
580  // is which.
581  if (L->contains(Incoming)) {
582  if (L->contains(Backedge))
583  return nullptr;
584  std::swap(Incoming, Backedge);
585  } else if (!L->contains(Backedge))
586  return nullptr;
587 
588  // Look for the cmp instruction to determine if we can get a useful trip
589  // count. The trip count can be either a register or an immediate. The
590  // location of the value depends upon the type (reg or imm).
591  MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
592  if (!ExitingBlock)
593  return nullptr;
594 
595  unsigned IVReg = 0;
596  int64_t IVBump = 0;
597  MachineInstr *IVOp;
598  bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
599  if (!FoundIV)
600  return nullptr;
601 
602  MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
603 
604  MachineOperand *InitialValue = nullptr;
605  MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
606  MachineBasicBlock *Latch = L->getLoopLatch();
607  for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
608  MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
609  if (MBB == Preheader)
610  InitialValue = &IV_Phi->getOperand(i);
611  else if (MBB == Latch)
612  IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
613  }
614  if (!InitialValue)
615  return nullptr;
616 
618  MachineBasicBlock *TB = nullptr, *FB = nullptr;
619  bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
620  if (NotAnalyzed)
621  return nullptr;
622 
623  MachineBasicBlock *Header = L->getHeader();
624  // TB must be non-null. If FB is also non-null, one of them must be
625  // the header. Otherwise, branch to TB could be exiting the loop, and
626  // the fall through can go to the header.
627  assert (TB && "Exit block without a branch?");
628  if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
629  MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
631  bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
632  if (NotAnalyzed)
633  return nullptr;
634  if (TB == Latch)
635  TB = (LTB == Header) ? LTB : LFB;
636  else
637  FB = (LTB == Header) ? LTB: LFB;
638  }
639  assert ((!FB || TB == Header || FB == Header) && "Branches not to header?");
640  if (!TB || (FB && TB != Header && FB != Header))
641  return nullptr;
642 
643  // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch
644  // to put imm(0), followed by P in the vector Cond.
645  // If TB is not the header, it means that the "not-taken" path must lead
646  // to the header.
647  bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
648  unsigned PredReg, PredPos, PredRegFlags;
649  if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
650  return nullptr;
651  MachineInstr *CondI = MRI->getVRegDef(PredReg);
652  unsigned CondOpc = CondI->getOpcode();
653 
654  Register CmpReg1, CmpReg2;
655  int64_t Mask = 0, ImmValue = 0;
656  bool AnalyzedCmp =
657  TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);
658  if (!AnalyzedCmp)
659  return nullptr;
660 
661  // The comparison operator type determines how we compute the loop
662  // trip count.
663  OldInsts.push_back(CondI);
664  OldInsts.push_back(IVOp);
665 
666  // Sadly, the following code gets information based on the position
667  // of the operands in the compare instruction. This has to be done
668  // this way, because the comparisons check for a specific relationship
669  // between the operands (e.g. is-less-than), rather than to find out
670  // what relationship the operands are in (as on PPC).
672  bool isSwapped = false;
673  const MachineOperand &Op1 = CondI->getOperand(1);
674  const MachineOperand &Op2 = CondI->getOperand(2);
675  const MachineOperand *EndValue = nullptr;
676 
677  if (Op1.isReg()) {
678  if (Op2.isImm() || Op1.getReg() == IVReg)
679  EndValue = &Op2;
680  else {
681  EndValue = &Op1;
682  isSwapped = true;
683  }
684  }
685 
686  if (!EndValue)
687  return nullptr;
688 
689  Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);
690  if (!Cmp)
691  return nullptr;
692  if (Negated)
693  Cmp = Comparison::getNegatedComparison(Cmp);
694  if (isSwapped)
695  Cmp = Comparison::getSwappedComparison(Cmp);
696 
697  if (InitialValue->isReg()) {
698  Register R = InitialValue->getReg();
699  MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
700  if (!MDT->properlyDominates(DefBB, Header)) {
701  int64_t V;
702  if (!checkForImmediate(*InitialValue, V))
703  return nullptr;
704  }
705  OldInsts.push_back(MRI->getVRegDef(R));
706  }
707  if (EndValue->isReg()) {
708  Register R = EndValue->getReg();
709  MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
710  if (!MDT->properlyDominates(DefBB, Header)) {
711  int64_t V;
712  if (!checkForImmediate(*EndValue, V))
713  return nullptr;
714  }
715  OldInsts.push_back(MRI->getVRegDef(R));
716  }
717 
718  return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
719 }
720 
721 /// Helper function that returns the expression that represents the
722 /// number of times a loop iterates. The function takes the operands that
723 /// represent the loop start value, loop end value, and induction value.
724 /// Based upon these operands, the function attempts to compute the trip count.
725 CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
726  const MachineOperand *Start,
727  const MachineOperand *End,
728  unsigned IVReg,
729  int64_t IVBump,
730  Comparison::Kind Cmp) const {
731  // Cannot handle comparison EQ, i.e. while (A == B).
732  if (Cmp == Comparison::EQ)
733  return nullptr;
734 
735  // Check if either the start or end values are an assignment of an immediate.
736  // If so, use the immediate value rather than the register.
737  if (Start->isReg()) {
738  const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
739  if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
740  StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
741  Start = &StartValInstr->getOperand(1);
742  }
743  if (End->isReg()) {
744  const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
745  if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
746  EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
747  End = &EndValInstr->getOperand(1);
748  }
749 
750  if (!Start->isReg() && !Start->isImm())
751  return nullptr;
752  if (!End->isReg() && !End->isImm())
753  return nullptr;
754 
755  bool CmpLess = Cmp & Comparison::L;
756  bool CmpGreater = Cmp & Comparison::G;
757  bool CmpHasEqual = Cmp & Comparison::EQ;
758 
759  // Avoid certain wrap-arounds. This doesn't detect all wrap-arounds.
760  if (CmpLess && IVBump < 0)
761  // Loop going while iv is "less" with the iv value going down. Must wrap.
762  return nullptr;
763 
764  if (CmpGreater && IVBump > 0)
765  // Loop going while iv is "greater" with the iv value going up. Must wrap.
766  return nullptr;
767 
768  // Phis that may feed into the loop.
769  LoopFeederMap LoopFeederPhi;
770 
771  // Check if the initial value may be zero and can be decremented in the first
772  // iteration. If the value is zero, the endloop instruction will not decrement
773  // the loop counter, so we shouldn't generate a hardware loop in this case.
774  if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop,
775  LoopFeederPhi))
776  return nullptr;
777 
778  if (Start->isImm() && End->isImm()) {
779  // Both, start and end are immediates.
780  int64_t StartV = Start->getImm();
781  int64_t EndV = End->getImm();
782  int64_t Dist = EndV - StartV;
783  if (Dist == 0)
784  return nullptr;
785 
786  bool Exact = (Dist % IVBump) == 0;
787 
788  if (Cmp == Comparison::NE) {
789  if (!Exact)
790  return nullptr;
791  if ((Dist < 0) ^ (IVBump < 0))
792  return nullptr;
793  }
794 
795  // For comparisons that include the final value (i.e. include equality
796  // with the final value), we need to increase the distance by 1.
797  if (CmpHasEqual)
798  Dist = Dist > 0 ? Dist+1 : Dist-1;
799 
800  // For the loop to iterate, CmpLess should imply Dist > 0. Similarly,
801  // CmpGreater should imply Dist < 0. These conditions could actually
802  // fail, for example, in unreachable code (which may still appear to be
803  // reachable in the CFG).
804  if ((CmpLess && Dist < 0) || (CmpGreater && Dist > 0))
805  return nullptr;
806 
807  // "Normalized" distance, i.e. with the bump set to +-1.
808  int64_t Dist1 = (IVBump > 0) ? (Dist + (IVBump - 1)) / IVBump
809  : (-Dist + (-IVBump - 1)) / (-IVBump);
810  assert (Dist1 > 0 && "Fishy thing. Both operands have the same sign.");
811 
812  uint64_t Count = Dist1;
813 
814  if (Count > 0xFFFFFFFFULL)
815  return nullptr;
816 
817  return new CountValue(CountValue::CV_Immediate, Count);
818  }
819 
820  // A general case: Start and End are some values, but the actual
821  // iteration count may not be available. If it is not, insert
822  // a computation of it into the preheader.
823 
824  // If the induction variable bump is not a power of 2, quit.
825  // Othwerise we'd need a general integer division.
826  if (!isPowerOf2_64(std::abs(IVBump)))
827  return nullptr;
828 
829  MachineBasicBlock *PH = MLI->findLoopPreheader(Loop, SpecPreheader);
830  assert (PH && "Should have a preheader by now");
832  DebugLoc DL;
833  if (InsertPos != PH->end())
834  DL = InsertPos->getDebugLoc();
835 
836  // If Start is an immediate and End is a register, the trip count
837  // will be "reg - imm". Hexagon's "subtract immediate" instruction
838  // is actually "reg + -imm".
839 
840  // If the loop IV is going downwards, i.e. if the bump is negative,
841  // then the iteration count (computed as End-Start) will need to be
842  // negated. To avoid the negation, just swap Start and End.
843  if (IVBump < 0) {
844  std::swap(Start, End);
845  IVBump = -IVBump;
846  }
847  // Cmp may now have a wrong direction, e.g. LEs may now be GEs.
848  // Signedness, and "including equality" are preserved.
849 
850  bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)
851  bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
852 
853  int64_t StartV = 0, EndV = 0;
854  if (Start->isImm())
855  StartV = Start->getImm();
856  if (End->isImm())
857  EndV = End->getImm();
858 
859  int64_t AdjV = 0;
860  // To compute the iteration count, we would need this computation:
861  // Count = (End - Start + (IVBump-1)) / IVBump
862  // or, when CmpHasEqual:
863  // Count = (End - Start + (IVBump-1)+1) / IVBump
864  // The "IVBump-1" part is the adjustment (AdjV). We can avoid
865  // generating an instruction specifically to add it if we can adjust
866  // the immediate values for Start or End.
867 
868  if (CmpHasEqual) {
869  // Need to add 1 to the total iteration count.
870  if (Start->isImm())
871  StartV--;
872  else if (End->isImm())
873  EndV++;
874  else
875  AdjV += 1;
876  }
877 
878  if (Cmp != Comparison::NE) {
879  if (Start->isImm())
880  StartV -= (IVBump-1);
881  else if (End->isImm())
882  EndV += (IVBump-1);
883  else
884  AdjV += (IVBump-1);
885  }
886 
887  unsigned R = 0, SR = 0;
888  if (Start->isReg()) {
889  R = Start->getReg();
890  SR = Start->getSubReg();
891  } else {
892  R = End->getReg();
893  SR = End->getSubReg();
894  }
895  const TargetRegisterClass *RC = MRI->getRegClass(R);
896  // Hardware loops cannot handle 64-bit registers. If it's a double
897  // register, it has to have a subregister.
898  if (!SR && RC == &Hexagon::DoubleRegsRegClass)
899  return nullptr;
900  const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
901 
902  // Compute DistR (register with the distance between Start and End).
903  unsigned DistR, DistSR;
904 
905  // Avoid special case, where the start value is an imm(0).
906  if (Start->isImm() && StartV == 0) {
907  DistR = End->getReg();
908  DistSR = End->getSubReg();
909  } else {
910  const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
911  (RegToImm ? TII->get(Hexagon::A2_subri) :
912  TII->get(Hexagon::A2_addi));
913  if (RegToReg || RegToImm) {
914  Register SubR = MRI->createVirtualRegister(IntRC);
915  MachineInstrBuilder SubIB =
916  BuildMI(*PH, InsertPos, DL, SubD, SubR);
917 
918  if (RegToReg)
919  SubIB.addReg(End->getReg(), 0, End->getSubReg())
920  .addReg(Start->getReg(), 0, Start->getSubReg());
921  else
922  SubIB.addImm(EndV)
923  .addReg(Start->getReg(), 0, Start->getSubReg());
924  DistR = SubR;
925  } else {
926  // If the loop has been unrolled, we should use the original loop count
927  // instead of recalculating the value. This will avoid additional
928  // 'Add' instruction.
929  const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
930  if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
931  EndValInstr->getOperand(1).getSubReg() == 0 &&
932  EndValInstr->getOperand(2).getImm() == StartV) {
933  DistR = EndValInstr->getOperand(1).getReg();
934  } else {
935  Register SubR = MRI->createVirtualRegister(IntRC);
936  MachineInstrBuilder SubIB =
937  BuildMI(*PH, InsertPos, DL, SubD, SubR);
938  SubIB.addReg(End->getReg(), 0, End->getSubReg())
939  .addImm(-StartV);
940  DistR = SubR;
941  }
942  }
943  DistSR = 0;
944  }
945 
946  // From DistR, compute AdjR (register with the adjusted distance).
947  unsigned AdjR, AdjSR;
948 
949  if (AdjV == 0) {
950  AdjR = DistR;
951  AdjSR = DistSR;
952  } else {
953  // Generate CountR = ADD DistR, AdjVal
954  Register AddR = MRI->createVirtualRegister(IntRC);
955  MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
956  BuildMI(*PH, InsertPos, DL, AddD, AddR)
957  .addReg(DistR, 0, DistSR)
958  .addImm(AdjV);
959 
960  AdjR = AddR;
961  AdjSR = 0;
962  }
963 
964  // From AdjR, compute CountR (register with the final count).
965  unsigned CountR, CountSR;
966 
967  if (IVBump == 1) {
968  CountR = AdjR;
969  CountSR = AdjSR;
970  } else {
971  // The IV bump is a power of two. Log_2(IV bump) is the shift amount.
972  unsigned Shift = Log2_32(IVBump);
973 
974  // Generate NormR = LSR DistR, Shift.
975  Register LsrR = MRI->createVirtualRegister(IntRC);
976  const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
977  BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
978  .addReg(AdjR, 0, AdjSR)
979  .addImm(Shift);
980 
981  CountR = LsrR;
982  CountSR = 0;
983  }
984 
985  return new CountValue(CountValue::CV_Register, CountR, CountSR);
986 }
987 
988 /// Return true if the operation is invalid within hardware loop.
989 bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
990  bool IsInnerHWLoop) const {
991  // Call is not allowed because the callee may use a hardware loop except for
992  // the case when the call never returns.
993  if (MI->getDesc().isCall())
994  return !TII->doesNotReturn(*MI);
995 
996  // Check if the instruction defines a hardware loop register.
997  using namespace Hexagon;
998 
999  static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
1000  static const unsigned Regs1[] = { LC1, SA1 };
1001  auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
1002  : makeArrayRef(Regs1, array_lengthof(Regs1));
1003  for (unsigned R : CheckRegs)
1004  if (MI->modifiesRegister(R, TRI))
1005  return true;
1006 
1007  return false;
1008 }
1009 
1010 /// Return true if the loop contains an instruction that inhibits
1011 /// the use of the hardware loop instruction.
1012 bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
1013  bool IsInnerHWLoop) const {
1014  LLVM_DEBUG(dbgs() << "\nhw_loop head, "
1015  << printMBBReference(**L->block_begin()));
1016  for (MachineBasicBlock *MBB : L->getBlocks()) {
1018  MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
1019  const MachineInstr *MI = &*MII;
1020  if (isInvalidLoopOperation(MI, IsInnerHWLoop)) {
1021  LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:";
1022  MI->dump(););
1023  return true;
1024  }
1025  }
1026  }
1027  return false;
1028 }
1029 
1030 /// Returns true if the instruction is dead. This was essentially
1031 /// copied from DeadMachineInstructionElim::isDead, but with special cases
1032 /// for inline asm, physical registers and instructions with side effects
1033 /// removed.
1034 bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
1035  SmallVectorImpl<MachineInstr *> &DeadPhis) const {
1036  // Examine each operand.
1037  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1038  const MachineOperand &MO = MI->getOperand(i);
1039  if (!MO.isReg() || !MO.isDef())
1040  continue;
1041 
1042  Register Reg = MO.getReg();
1043  if (MRI->use_nodbg_empty(Reg))
1044  continue;
1045 
1046  using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
1047 
1048  // This instruction has users, but if the only user is the phi node for the
1049  // parent block, and the only use of that phi node is this instruction, then
1050  // this instruction is dead: both it (and the phi node) can be removed.
1051  use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
1052  use_nodbg_iterator End = MRI->use_nodbg_end();
1053  if (std::next(I) != End || !I->getParent()->isPHI())
1054  return false;
1055 
1056  MachineInstr *OnePhi = I->getParent();
1057  for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
1058  const MachineOperand &OPO = OnePhi->getOperand(j);
1059  if (!OPO.isReg() || !OPO.isDef())
1060  continue;
1061 
1062  Register OPReg = OPO.getReg();
1063  use_nodbg_iterator nextJ;
1064  for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
1065  J != End; J = nextJ) {
1066  nextJ = std::next(J);
1067  MachineOperand &Use = *J;
1068  MachineInstr *UseMI = Use.getParent();
1069 
1070  // If the phi node has a user that is not MI, bail.
1071  if (MI != UseMI)
1072  return false;
1073  }
1074  }
1075  DeadPhis.push_back(OnePhi);
1076  }
1077 
1078  // If there are no defs with uses, the instruction is dead.
1079  return true;
1080 }
1081 
1082 void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
1083  // This procedure was essentially copied from DeadMachineInstructionElim.
1084 
1086  if (isDead(MI, DeadPhis)) {
1087  LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI);
1088 
1089  // It is possible that some DBG_VALUE instructions refer to this
1090  // instruction. Examine each def operand for such references;
1091  // if found, mark the DBG_VALUE as undef (but don't delete it).
1092  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1093  const MachineOperand &MO = MI->getOperand(i);
1094  if (!MO.isReg() || !MO.isDef())
1095  continue;
1096  Register Reg = MO.getReg();
1099  E = MRI->use_end(); I != E; I = nextI) {
1100  nextI = std::next(I); // I is invalidated by the setReg
1101  MachineInstr *UseMI = I->getParent();
1102  if (UseMI == MI)
1103  continue;
1104  if (I->isDebug())
1105  I->setReg(0U);
1106  }
1107  }
1108 
1109  MI->eraseFromParent();
1110  for (unsigned i = 0; i < DeadPhis.size(); ++i)
1111  DeadPhis[i]->eraseFromParent();
1112  }
1113 }
1114 
1115 /// Check if the loop is a candidate for converting to a hardware
1116 /// loop. If so, then perform the transformation.
1117 ///
1118 /// This function works on innermost loops first. A loop can be converted
1119 /// if it is a counting loop; either a register value or an immediate.
1120 ///
1121 /// The code makes several assumptions about the representation of the loop
1122 /// in llvm.
1123 bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
1124  bool &RecL0used,
1125  bool &RecL1used) {
1126  // This is just for sanity.
1127  assert(L->getHeader() && "Loop without a header?");
1128 
1129  bool Changed = false;
1130  bool L0Used = false;
1131  bool L1Used = false;
1132 
1133  // Process nested loops first.
1134  for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
1135  Changed |= convertToHardwareLoop(*I, RecL0used, RecL1used);
1136  L0Used |= RecL0used;
1137  L1Used |= RecL1used;
1138  }
1139 
1140  // If a nested loop has been converted, then we can't convert this loop.
1141  if (Changed && L0Used && L1Used)
1142  return Changed;
1143 
1144  unsigned LOOP_i;
1145  unsigned LOOP_r;
1146  unsigned ENDLOOP;
1147 
1148  // Flag used to track loopN instruction:
1149  // 1 - Hardware loop is being generated for the inner most loop.
1150  // 0 - Hardware loop is being generated for the outer loop.
1151  unsigned IsInnerHWLoop = 1;
1152 
1153  if (L0Used) {
1154  LOOP_i = Hexagon::J2_loop1i;
1155  LOOP_r = Hexagon::J2_loop1r;
1156  ENDLOOP = Hexagon::ENDLOOP1;
1157  IsInnerHWLoop = 0;
1158  } else {
1159  LOOP_i = Hexagon::J2_loop0i;
1160  LOOP_r = Hexagon::J2_loop0r;
1161  ENDLOOP = Hexagon::ENDLOOP0;
1162  }
1163 
1164 #ifndef NDEBUG
1165  // Stop trying after reaching the limit (if any).
1166  int Limit = HWLoopLimit;
1167  if (Limit >= 0) {
1168  if (Counter >= HWLoopLimit)
1169  return false;
1170  Counter++;
1171  }
1172 #endif
1173 
1174  // Does the loop contain any invalid instructions?
1175  if (containsInvalidInstruction(L, IsInnerHWLoop))
1176  return false;
1177 
1178  MachineBasicBlock *LastMBB = L->findLoopControlBlock();
1179  // Don't generate hw loop if the loop has more than one exit.
1180  if (!LastMBB)
1181  return false;
1182 
1184  if (LastI == LastMBB->end())
1185  return false;
1186 
1187  // Is the induction variable bump feeding the latch condition?
1188  if (!fixupInductionVariable(L))
1189  return false;
1190 
1191  // Ensure the loop has a preheader: the loop instruction will be
1192  // placed there.
1193  MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
1194  if (!Preheader) {
1195  Preheader = createPreheaderForLoop(L);
1196  if (!Preheader)
1197  return false;
1198  }
1199 
1200  MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
1201 
1203  // Are we able to determine the trip count for the loop?
1204  CountValue *TripCount = getLoopTripCount(L, OldInsts);
1205  if (!TripCount)
1206  return false;
1207 
1208  // Is the trip count available in the preheader?
1209  if (TripCount->isReg()) {
1210  // There will be a use of the register inserted into the preheader,
1211  // so make sure that the register is actually defined at that point.
1212  MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());
1213  MachineBasicBlock *BBDef = TCDef->getParent();
1214  if (!MDT->dominates(BBDef, Preheader))
1215  return false;
1216  }
1217 
1218  // Determine the loop start.
1219  MachineBasicBlock *TopBlock = L->getTopBlock();
1220  MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1221  MachineBasicBlock *LoopStart = nullptr;
1222  if (ExitingBlock != L->getLoopLatch()) {
1223  MachineBasicBlock *TB = nullptr, *FB = nullptr;
1225 
1226  if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false))
1227  return false;
1228 
1229  if (L->contains(TB))
1230  LoopStart = TB;
1231  else if (L->contains(FB))
1232  LoopStart = FB;
1233  else
1234  return false;
1235  }
1236  else
1237  LoopStart = TopBlock;
1238 
1239  // Convert the loop to a hardware loop.
1240  LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump());
1241  DebugLoc DL;
1242  if (InsertPos != Preheader->end())
1243  DL = InsertPos->getDebugLoc();
1244 
1245  if (TripCount->isReg()) {
1246  // Create a copy of the loop count register.
1247  Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1248  BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1249  .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
1250  // Add the Loop instruction to the beginning of the loop.
1251  BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1252  .addReg(CountReg);
1253  } else {
1254  assert(TripCount->isImm() && "Expecting immediate value for trip count");
1255  // Add the Loop immediate instruction to the beginning of the loop,
1256  // if the immediate fits in the instructions. Otherwise, we need to
1257  // create a new virtual register.
1258  int64_t CountImm = TripCount->getImm();
1259  if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) {
1260  Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1261  BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
1262  .addImm(CountImm);
1263  BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
1264  .addMBB(LoopStart).addReg(CountReg);
1265  } else
1266  BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
1267  .addMBB(LoopStart).addImm(CountImm);
1268  }
1269 
1270  // Make sure the loop start always has a reference in the CFG. We need
1271  // to create a BlockAddress operand to get this mechanism to work both the
1272  // MachineBasicBlock and BasicBlock objects need the flag set.
1273  LoopStart->setHasAddressTaken();
1274  // This line is needed to set the hasAddressTaken flag on the BasicBlock
1275  // object.
1276  BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
1277 
1278  // Replace the loop branch with an endloop instruction.
1279  DebugLoc LastIDL = LastI->getDebugLoc();
1280  BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
1281 
1282  // The loop ends with either:
1283  // - a conditional branch followed by an unconditional branch, or
1284  // - a conditional branch to the loop start.
1285  if (LastI->getOpcode() == Hexagon::J2_jumpt ||
1286  LastI->getOpcode() == Hexagon::J2_jumpf) {
1287  // Delete one and change/add an uncond. branch to out of the loop.
1288  MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
1289  LastI = LastMBB->erase(LastI);
1290  if (!L->contains(BranchTarget)) {
1291  if (LastI != LastMBB->end())
1292  LastI = LastMBB->erase(LastI);
1294  TII->insertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);
1295  }
1296  } else {
1297  // Conditional branch to loop start; just delete it.
1298  LastMBB->erase(LastI);
1299  }
1300  delete TripCount;
1301 
1302  // The induction operation and the comparison may now be
1303  // unneeded. If these are unneeded, then remove them.
1304  for (unsigned i = 0; i < OldInsts.size(); ++i)
1305  removeIfDead(OldInsts[i]);
1306 
1307  ++NumHWLoops;
1308 
1309  // Set RecL1used and RecL0used only after hardware loop has been
1310  // successfully generated. Doing it earlier can cause wrong loop instruction
1311  // to be used.
1312  if (L0Used) // Loop0 was already used. So, the correct loop must be loop1.
1313  RecL1used = true;
1314  else
1315  RecL0used = true;
1316 
1317  return true;
1318 }
1319 
1320 bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
1321  MachineInstr *CmpI) {
1322  assert (BumpI != CmpI && "Bump and compare in the same instruction?");
1323 
1324  MachineBasicBlock *BB = BumpI->getParent();
1325  if (CmpI->getParent() != BB)
1326  return false;
1327 
1328  using instr_iterator = MachineBasicBlock::instr_iterator;
1329 
1330  // Check if things are in order to begin with.
1331  for (instr_iterator I(BumpI), E = BB->instr_end(); I != E; ++I)
1332  if (&*I == CmpI)
1333  return true;
1334 
1335  // Out of order.
1336  Register PredR = CmpI->getOperand(0).getReg();
1337  bool FoundBump = false;
1338  instr_iterator CmpIt = CmpI->getIterator(), NextIt = std::next(CmpIt);
1339  for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
1340  MachineInstr *In = &*I;
1341  for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
1342  MachineOperand &MO = In->getOperand(i);
1343  if (MO.isReg() && MO.isUse()) {
1344  if (MO.getReg() == PredR) // Found an intervening use of PredR.
1345  return false;
1346  }
1347  }
1348 
1349  if (In == BumpI) {
1350  BB->splice(++BumpI->getIterator(), BB, CmpI->getIterator());
1351  FoundBump = true;
1352  break;
1353  }
1354  }
1355  assert (FoundBump && "Cannot determine instruction order");
1356  return FoundBump;
1357 }
1358 
1359 /// This function is required to break recursion. Visiting phis in a loop may
1360 /// result in recursion during compilation. We break the recursion by making
1361 /// sure that we visit a MachineOperand and its definition in a
1362 /// MachineInstruction only once. If we attempt to visit more than once, then
1363 /// there is recursion, and will return false.
1364 bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
1365  MachineInstr *MI,
1366  const MachineOperand *MO,
1367  LoopFeederMap &LoopFeederPhi) const {
1368  if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
1369  LLVM_DEBUG(dbgs() << "\nhw_loop head, "
1370  << printMBBReference(**L->block_begin()));
1371  // Ignore all BBs that form Loop.
1372  if (llvm::is_contained(L->getBlocks(), A))
1373  return false;
1374  MachineInstr *Def = MRI->getVRegDef(MO->getReg());
1375  LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def));
1376  return true;
1377  } else
1378  // Already visited node.
1379  return false;
1380 }
1381 
1382 /// Return true if a Phi may generate a value that can underflow.
1383 /// This function calls loopCountMayWrapOrUnderFlow for each Phi operand.
1384 bool HexagonHardwareLoops::phiMayWrapOrUnderflow(
1385  MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB,
1386  MachineLoop *L, LoopFeederMap &LoopFeederPhi) const {
1387  assert(Phi->isPHI() && "Expecting a Phi.");
1388  // Walk through each Phi, and its used operands. Make sure that
1389  // if there is recursion in Phi, we won't generate hardware loops.
1390  for (int i = 1, n = Phi->getNumOperands(); i < n; i += 2)
1391  if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi))
1392  if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal,
1393  Phi->getParent(), L, LoopFeederPhi))
1394  return true;
1395  return false;
1396 }
1397 
1398 /// Return true if the induction variable can underflow in the first iteration.
1399 /// An example, is an initial unsigned value that is 0 and is decrement in the
1400 /// first itertion of a do-while loop. In this case, we cannot generate a
1401 /// hardware loop because the endloop instruction does not decrement the loop
1402 /// counter if it is <= 1. We only need to perform this analysis if the
1403 /// initial value is a register.
1404 ///
1405 /// This function assumes the initial value may underfow unless proven
1406 /// otherwise. If the type is signed, then we don't care because signed
1407 /// underflow is undefined. We attempt to prove the initial value is not
1408 /// zero by perfoming a crude analysis of the loop counter. This function
1409 /// checks if the initial value is used in any comparison prior to the loop
1410 /// and, if so, assumes the comparison is a range check. This is inexact,
1411 /// but will catch the simple cases.
1412 bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
1413  const MachineOperand *InitVal, const MachineOperand *EndVal,
1415  LoopFeederMap &LoopFeederPhi) const {
1416  // Only check register values since they are unknown.
1417  if (!InitVal->isReg())
1418  return false;
1419 
1420  if (!EndVal->isImm())
1421  return false;
1422 
1423  // A register value that is assigned an immediate is a known value, and it
1424  // won't underflow in the first iteration.
1425  int64_t Imm;
1426  if (checkForImmediate(*InitVal, Imm))
1427  return (EndVal->getImm() == Imm);
1428 
1429  Register Reg = InitVal->getReg();
1430 
1431  // We don't know the value of a physical register.
1432  if (!Reg.isVirtual())
1433  return true;
1434 
1436  if (!Def)
1437  return true;
1438 
1439  // If the initial value is a Phi or copy and the operands may not underflow,
1440  // then the definition cannot be underflow either.
1441  if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(),
1442  L, LoopFeederPhi))
1443  return false;
1444  if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1445  EndVal, Def->getParent(),
1446  L, LoopFeederPhi))
1447  return false;
1448 
1449  // Iterate over the uses of the initial value. If the initial value is used
1450  // in a compare, then we assume this is a range check that ensures the loop
1451  // doesn't underflow. This is not an exact test and should be improved.
1453  E = MRI->use_instr_nodbg_end(); I != E; ++I) {
1454  MachineInstr *MI = &*I;
1455  Register CmpReg1, CmpReg2;
1456  int64_t CmpMask = 0, CmpValue = 0;
1457 
1458  if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue))
1459  continue;
1460 
1461  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1463  if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false))
1464  continue;
1465 
1467  getComparisonKind(MI->getOpcode(), nullptr, nullptr, 0);
1468  if (Cmp == 0)
1469  continue;
1470  if (TII->predOpcodeHasNot(Cond) ^ (TBB != MBB))
1471  Cmp = Comparison::getNegatedComparison(Cmp);
1472  if (CmpReg2 != 0 && CmpReg2 == Reg)
1473  Cmp = Comparison::getSwappedComparison(Cmp);
1474 
1475  // Signed underflow is undefined.
1476  if (Comparison::isSigned(Cmp))
1477  return false;
1478 
1479  // Check if there is a comparison of the initial value. If the initial value
1480  // is greater than or not equal to another value, then assume this is a
1481  // range check.
1482  if ((Cmp & Comparison::G) || Cmp == Comparison::NE)
1483  return false;
1484  }
1485 
1486  // OK - this is a hack that needs to be improved. We really need to analyze
1487  // the instructions performed on the initial value. This works on the simplest
1488  // cases only.
1489  if (!Def->isCopy() && !Def->isPHI())
1490  return false;
1491 
1492  return true;
1493 }
1494 
1495 bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
1496  int64_t &Val) const {
1497  if (MO.isImm()) {
1498  Val = MO.getImm();
1499  return true;
1500  }
1501  if (!MO.isReg())
1502  return false;
1503 
1504  // MO is a register. Check whether it is defined as an immediate value,
1505  // and if so, get the value of it in TV. That value will then need to be
1506  // processed to handle potential subregisters in MO.
1507  int64_t TV;
1508 
1509  Register R = MO.getReg();
1510  if (!R.isVirtual())
1511  return false;
1512  MachineInstr *DI = MRI->getVRegDef(R);
1513  unsigned DOpc = DI->getOpcode();
1514  switch (DOpc) {
1515  case TargetOpcode::COPY:
1516  case Hexagon::A2_tfrsi:
1517  case Hexagon::A2_tfrpi:
1518  case Hexagon::CONST32:
1519  case Hexagon::CONST64:
1520  // Call recursively to avoid an extra check whether operand(1) is
1521  // indeed an immediate (it could be a global address, for example),
1522  // plus we can handle COPY at the same time.
1523  if (!checkForImmediate(DI->getOperand(1), TV))
1524  return false;
1525  break;
1526  case Hexagon::A2_combineii:
1527  case Hexagon::A4_combineir:
1528  case Hexagon::A4_combineii:
1529  case Hexagon::A4_combineri:
1530  case Hexagon::A2_combinew: {
1531  const MachineOperand &S1 = DI->getOperand(1);
1532  const MachineOperand &S2 = DI->getOperand(2);
1533  int64_t V1, V2;
1534  if (!checkForImmediate(S1, V1) || !checkForImmediate(S2, V2))
1535  return false;
1536  TV = V2 | (static_cast<uint64_t>(V1) << 32);
1537  break;
1538  }
1539  case TargetOpcode::REG_SEQUENCE: {
1540  const MachineOperand &S1 = DI->getOperand(1);
1541  const MachineOperand &S3 = DI->getOperand(3);
1542  int64_t V1, V3;
1543  if (!checkForImmediate(S1, V1) || !checkForImmediate(S3, V3))
1544  return false;
1545  unsigned Sub2 = DI->getOperand(2).getImm();
1546  unsigned Sub4 = DI->getOperand(4).getImm();
1547  if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
1548  TV = V1 | (V3 << 32);
1549  else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
1550  TV = V3 | (V1 << 32);
1551  else
1552  llvm_unreachable("Unexpected form of REG_SEQUENCE");
1553  break;
1554  }
1555 
1556  default:
1557  return false;
1558  }
1559 
1560  // By now, we should have successfully obtained the immediate value defining
1561  // the register referenced in MO. Handle a potential use of a subregister.
1562  switch (MO.getSubReg()) {
1563  case Hexagon::isub_lo:
1564  Val = TV & 0xFFFFFFFFULL;
1565  break;
1566  case Hexagon::isub_hi:
1567  Val = (TV >> 32) & 0xFFFFFFFFULL;
1568  break;
1569  default:
1570  Val = TV;
1571  break;
1572  }
1573  return true;
1574 }
1575 
1576 void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
1577  if (MO.isImm()) {
1578  MO.setImm(Val);
1579  return;
1580  }
1581 
1582  assert(MO.isReg());
1583  Register R = MO.getReg();
1584  MachineInstr *DI = MRI->getVRegDef(R);
1585 
1586  const TargetRegisterClass *RC = MRI->getRegClass(R);
1587  Register NewR = MRI->createVirtualRegister(RC);
1588  MachineBasicBlock &B = *DI->getParent();
1589  DebugLoc DL = DI->getDebugLoc();
1590  BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
1591  MO.setReg(NewR);
1592 }
1593 
1594 static bool isImmValidForOpcode(unsigned CmpOpc, int64_t Imm) {
1595  // These two instructions are not extendable.
1596  if (CmpOpc == Hexagon::A4_cmpbeqi)
1597  return isUInt<8>(Imm);
1598  if (CmpOpc == Hexagon::A4_cmpbgti)
1599  return isInt<8>(Imm);
1600  // The rest of the comparison-with-immediate instructions are extendable.
1601  return true;
1602 }
1603 
1604 bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
1605  MachineBasicBlock *Header = L->getHeader();
1606  MachineBasicBlock *Latch = L->getLoopLatch();
1607  MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1608 
1609  if (!(Header && Latch && ExitingBlock))
1610  return false;
1611 
1612  // These data structures follow the same concept as the corresponding
1613  // ones in findInductionRegister (where some comments are).
1614  using RegisterBump = std::pair<unsigned, int64_t>;
1615  using RegisterInduction = std::pair<unsigned, RegisterBump>;
1616  using RegisterInductionSet = std::set<RegisterInduction>;
1617 
1618  // Register candidates for induction variables, with their associated bumps.
1619  RegisterInductionSet IndRegs;
1620 
1621  // Look for induction patterns:
1622  // %1 = PHI ..., [ latch, %2 ]
1623  // %2 = ADD %1, imm
1624  using instr_iterator = MachineBasicBlock::instr_iterator;
1625 
1626  for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1627  I != E && I->isPHI(); ++I) {
1628  MachineInstr *Phi = &*I;
1629 
1630  // Have a PHI instruction.
1631  for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
1632  if (Phi->getOperand(i+1).getMBB() != Latch)
1633  continue;
1634 
1635  Register PhiReg = Phi->getOperand(i).getReg();
1636  MachineInstr *DI = MRI->getVRegDef(PhiReg);
1637 
1638  if (DI->getDesc().isAdd()) {
1639  // If the register operand to the add/sub is the PHI we are looking
1640  // at, this meets the induction pattern.
1641  Register IndReg = DI->getOperand(1).getReg();
1642  MachineOperand &Opnd2 = DI->getOperand(2);
1643  int64_t V;
1644  if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
1645  Register UpdReg = DI->getOperand(0).getReg();
1646  IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
1647  }
1648  }
1649  } // for (i)
1650  } // for (instr)
1651 
1652  if (IndRegs.empty())
1653  return false;
1654 
1655  MachineBasicBlock *TB = nullptr, *FB = nullptr;
1657  // analyzeBranch returns true if it fails to analyze branch.
1658  bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
1659  if (NotAnalyzed || Cond.empty())
1660  return false;
1661 
1662  if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
1663  MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
1665  bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
1666  if (NotAnalyzed)
1667  return false;
1668 
1669  // Since latch is not the exiting block, the latch branch should be an
1670  // unconditional branch to the loop header.
1671  if (TB == Latch)
1672  TB = (LTB == Header) ? LTB : LFB;
1673  else
1674  FB = (LTB == Header) ? LTB : LFB;
1675  }
1676  if (TB != Header) {
1677  if (FB != Header) {
1678  // The latch/exit block does not go back to the header.
1679  return false;
1680  }
1681  // FB is the header (i.e., uncond. jump to branch header)
1682  // In this case, the LoopBody -> TB should not be a back edge otherwise
1683  // it could result in an infinite loop after conversion to hw_loop.
1684  // This case can happen when the Latch has two jumps like this:
1685  // Jmp_c OuterLoopHeader <-- TB
1686  // Jmp InnerLoopHeader <-- FB
1687  if (MDT->dominates(TB, FB))
1688  return false;
1689  }
1690 
1691  // Expecting a predicate register as a condition. It won't be a hardware
1692  // predicate register at this point yet, just a vreg.
1693  // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0)
1694  // into Cond, followed by the predicate register. For non-negated branches
1695  // it's just the register.
1696  unsigned CSz = Cond.size();
1697  if (CSz != 1 && CSz != 2)
1698  return false;
1699 
1700  if (!Cond[CSz-1].isReg())
1701  return false;
1702 
1703  Register P = Cond[CSz - 1].getReg();
1704  MachineInstr *PredDef = MRI->getVRegDef(P);
1705 
1706  if (!PredDef->isCompare())
1707  return false;
1708 
1709  SmallSet<unsigned,2> CmpRegs;
1710  MachineOperand *CmpImmOp = nullptr;
1711 
1712  // Go over all operands to the compare and look for immediate and register
1713  // operands. Assume that if the compare has a single register use and a
1714  // single immediate operand, then the register is being compared with the
1715  // immediate value.
1716  for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1717  MachineOperand &MO = PredDef->getOperand(i);
1718  if (MO.isReg()) {
1719  // Skip all implicit references. In one case there was:
1720  // %140 = FCMPUGT32_rr %138, %139, implicit %usr
1721  if (MO.isImplicit())
1722  continue;
1723  if (MO.isUse()) {
1724  if (!isImmediate(MO)) {
1725  CmpRegs.insert(MO.getReg());
1726  continue;
1727  }
1728  // Consider the register to be the "immediate" operand.
1729  if (CmpImmOp)
1730  return false;
1731  CmpImmOp = &MO;
1732  }
1733  } else if (MO.isImm()) {
1734  if (CmpImmOp) // A second immediate argument? Confusing. Bail out.
1735  return false;
1736  CmpImmOp = &MO;
1737  }
1738  }
1739 
1740  if (CmpRegs.empty())
1741  return false;
1742 
1743  // Check if the compared register follows the order we want. Fix if needed.
1744  for (RegisterInductionSet::iterator I = IndRegs.begin(), E = IndRegs.end();
1745  I != E; ++I) {
1746  // This is a success. If the register used in the comparison is one that
1747  // we have identified as a bumped (updated) induction register, there is
1748  // nothing to do.
1749  if (CmpRegs.count(I->first))
1750  return true;
1751 
1752  // Otherwise, if the register being compared comes out of a PHI node,
1753  // and has been recognized as following the induction pattern, and is
1754  // compared against an immediate, we can fix it.
1755  const RegisterBump &RB = I->second;
1756  if (CmpRegs.count(RB.first)) {
1757  if (!CmpImmOp) {
1758  // If both operands to the compare instruction are registers, see if
1759  // it can be changed to use induction register as one of the operands.
1760  MachineInstr *IndI = nullptr;
1761  MachineInstr *nonIndI = nullptr;
1762  MachineOperand *IndMO = nullptr;
1763  MachineOperand *nonIndMO = nullptr;
1764 
1765  for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) {
1766  MachineOperand &MO = PredDef->getOperand(i);
1767  if (MO.isReg() && MO.getReg() == RB.first) {
1768  LLVM_DEBUG(dbgs() << "\n DefMI(" << i
1769  << ") = " << *(MRI->getVRegDef(I->first)));
1770  if (IndI)
1771  return false;
1772 
1773  IndI = MRI->getVRegDef(I->first);
1774  IndMO = &MO;
1775  } else if (MO.isReg()) {
1776  LLVM_DEBUG(dbgs() << "\n DefMI(" << i
1777  << ") = " << *(MRI->getVRegDef(MO.getReg())));
1778  if (nonIndI)
1779  return false;
1780 
1781  nonIndI = MRI->getVRegDef(MO.getReg());
1782  nonIndMO = &MO;
1783  }
1784  }
1785  if (IndI && nonIndI &&
1786  nonIndI->getOpcode() == Hexagon::A2_addi &&
1787  nonIndI->getOperand(2).isImm() &&
1788  nonIndI->getOperand(2).getImm() == - RB.second) {
1789  bool Order = orderBumpCompare(IndI, PredDef);
1790  if (Order) {
1791  IndMO->setReg(I->first);
1792  nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1793  return true;
1794  }
1795  }
1796  return false;
1797  }
1798 
1799  // It is not valid to do this transformation on an unsigned comparison
1800  // because it may underflow.
1802  getComparisonKind(PredDef->getOpcode(), nullptr, nullptr, 0);
1803  if (!Cmp || Comparison::isUnsigned(Cmp))
1804  return false;
1805 
1806  // If the register is being compared against an immediate, try changing
1807  // the compare instruction to use induction register and adjust the
1808  // immediate operand.
1809  int64_t CmpImm = getImmediate(*CmpImmOp);
1810  int64_t V = RB.second;
1811  // Handle Overflow (64-bit).
1812  if (((V > 0) && (CmpImm > INT64_MAX - V)) ||
1813  ((V < 0) && (CmpImm < INT64_MIN - V)))
1814  return false;
1815  CmpImm += V;
1816  // Most comparisons of register against an immediate value allow
1817  // the immediate to be constant-extended. There are some exceptions
1818  // though. Make sure the new combination will work.
1819  if (CmpImmOp->isImm())
1820  if (!isImmValidForOpcode(PredDef->getOpcode(), CmpImm))
1821  return false;
1822 
1823  // Make sure that the compare happens after the bump. Otherwise,
1824  // after the fixup, the compare would use a yet-undefined register.
1825  MachineInstr *BumpI = MRI->getVRegDef(I->first);
1826  bool Order = orderBumpCompare(BumpI, PredDef);
1827  if (!Order)
1828  return false;
1829 
1830  // Finally, fix the compare instruction.
1831  setImmediate(*CmpImmOp, CmpImm);
1832  for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1833  MachineOperand &MO = PredDef->getOperand(i);
1834  if (MO.isReg() && MO.getReg() == RB.first) {
1835  MO.setReg(I->first);
1836  return true;
1837  }
1838  }
1839  }
1840  }
1841 
1842  return false;
1843 }
1844 
1845 /// createPreheaderForLoop - Create a preheader for a given loop.
1846 MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
1847  MachineLoop *L) {
1848  if (MachineBasicBlock *TmpPH = MLI->findLoopPreheader(L, SpecPreheader))
1849  return TmpPH;
1850  if (!HWCreatePreheader)
1851  return nullptr;
1852 
1853  MachineBasicBlock *Header = L->getHeader();
1854  MachineBasicBlock *Latch = L->getLoopLatch();
1855  MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1856  MachineFunction *MF = Header->getParent();
1857  DebugLoc DL;
1858 
1859 #ifndef NDEBUG
1860  if ((!PHFn.empty()) && (PHFn != MF->getName()))
1861  return nullptr;
1862 #endif
1863 
1864  if (!Latch || !ExitingBlock || Header->hasAddressTaken())
1865  return nullptr;
1866 
1867  using instr_iterator = MachineBasicBlock::instr_iterator;
1868 
1869  // Verify that all existing predecessors have analyzable branches
1870  // (or no branches at all).
1871  using MBBVector = std::vector<MachineBasicBlock *>;
1872 
1873  MBBVector Preds(Header->pred_begin(), Header->pred_end());
1875  MachineBasicBlock *TB = nullptr, *FB = nullptr;
1876 
1877  if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
1878  return nullptr;
1879 
1880  for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1881  MachineBasicBlock *PB = *I;
1882  bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
1883  if (NotAnalyzed)
1884  return nullptr;
1885  }
1886 
1888  MF->insert(Header->getIterator(), NewPH);
1889 
1890  if (Header->pred_size() > 2) {
1891  // Ensure that the header has only two predecessors: the preheader and
1892  // the loop latch. Any additional predecessors of the header should
1893  // join at the newly created preheader. Inspect all PHI nodes from the
1894  // header and create appropriate corresponding PHI nodes in the preheader.
1895 
1896  for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1897  I != E && I->isPHI(); ++I) {
1898  MachineInstr *PN = &*I;
1899 
1900  const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
1901  MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
1902  NewPH->insert(NewPH->end(), NewPN);
1903 
1904  Register PR = PN->getOperand(0).getReg();
1905  const TargetRegisterClass *RC = MRI->getRegClass(PR);
1906  Register NewPR = MRI->createVirtualRegister(RC);
1907  NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1908 
1909  // Copy all non-latch operands of a header's PHI node to the newly
1910  // created PHI node in the preheader.
1911  for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1912  Register PredR = PN->getOperand(i).getReg();
1913  unsigned PredRSub = PN->getOperand(i).getSubReg();
1914  MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1915  if (PredB == Latch)
1916  continue;
1917 
1918  MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1919  MO.setSubReg(PredRSub);
1920  NewPN->addOperand(MO);
1921  NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1922  }
1923 
1924  // Remove copied operands from the old PHI node and add the value
1925  // coming from the preheader's PHI.
1926  for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
1927  MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1928  if (PredB != Latch) {
1929  PN->RemoveOperand(i+1);
1930  PN->RemoveOperand(i);
1931  }
1932  }
1933  PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1935  }
1936  } else {
1937  assert(Header->pred_size() == 2);
1938 
1939  // The header has only two predecessors, but the non-latch predecessor
1940  // is not a preheader (e.g. it has other successors, etc.)
1941  // In such a case we don't need any extra PHI nodes in the new preheader,
1942  // all we need is to adjust existing PHIs in the header to now refer to
1943  // the new preheader.
1944  for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1945  I != E && I->isPHI(); ++I) {
1946  MachineInstr *PN = &*I;
1947  for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1948  MachineOperand &MO = PN->getOperand(i+1);
1949  if (MO.getMBB() != Latch)
1950  MO.setMBB(NewPH);
1951  }
1952  }
1953  }
1954 
1955  // "Reroute" the CFG edges to link in the new preheader.
1956  // If any of the predecessors falls through to the header, insert a branch
1957  // to the new preheader in that place.
1960 
1961  TB = FB = nullptr;
1962 
1963  for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1964  MachineBasicBlock *PB = *I;
1965  if (PB != Latch) {
1966  Tmp2.clear();
1967  bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);
1968  (void)NotAnalyzed; // suppress compiler warning
1969  assert (!NotAnalyzed && "Should be analyzable!");
1970  if (TB != Header && (Tmp2.empty() || FB != Header))
1971  TII->insertBranch(*PB, NewPH, nullptr, EmptyCond, DL);
1972  PB->ReplaceUsesOfBlockWith(Header, NewPH);
1973  }
1974  }
1975 
1976  // It can happen that the latch block will fall through into the header.
1977  // Insert an unconditional branch to the header.
1978  TB = FB = nullptr;
1979  bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false);
1980  (void)LatchNotAnalyzed; // suppress compiler warning
1981  assert (!LatchNotAnalyzed && "Should be analyzable!");
1982  if (!TB && !FB)
1983  TII->insertBranch(*Latch, Header, nullptr, EmptyCond, DL);
1984 
1985  // Finally, the branch from the preheader to the header.
1986  TII->insertBranch(*NewPH, Header, nullptr, EmptyCond, DL);
1987  NewPH->addSuccessor(Header);
1988 
1989  MachineLoop *ParentLoop = L->getParentLoop();
1990  if (ParentLoop)
1991  ParentLoop->addBasicBlockToLoop(NewPH, MLI->getBase());
1992 
1993  // Update the dominator information with the new preheader.
1994  if (MDT) {
1995  if (MachineDomTreeNode *HN = MDT->getNode(Header)) {
1996  if (MachineDomTreeNode *DHN = HN->getIDom()) {
1997  MDT->addNewBlock(NewPH, DHN->getBlock());
1998  MDT->changeImmediateDominator(Header, NewPH);
1999  }
2000  }
2001  }
2002 
2003  return NewPH;
2004 }
i
i
Definition: README.txt:29
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:538
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::AArch64CC::NE
@ NE
Definition: AArch64BaseInfo.h:256
llvm::HexagonInstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: HexagonInstrInfo.cpp:1793
llvm::MachineOperand::CreateReg
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
Definition: MachineOperand.h:791
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Definition: MachineBasicBlock.h:202
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:147
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineDominatorTree::properlyDominates
bool properlyDominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:141
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:530
StringRef.h
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
Pass.h
llvm::LoopBase::contains
bool contains(const LoopT *L) const
Return true if the specified loop is contained within in this loop.
Definition: LoopInfo.h:122
llvm::HexagonInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: HexagonInstrInfo.cpp:391
llvm::MachineInstr::isCompare
bool isCompare(QueryType Type=IgnoreBundle) const
Return true if this instruction is a comparison.
Definition: MachineInstr.h:892
llvm::MachineInstr::RemoveOperand
void RemoveOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
Definition: MachineInstr.cpp:306
Loops
Hexagon Hardware Loops
Definition: HexagonHardwareLoops.cpp:372
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
Statistic.h
llvm::printMBBReference
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
Definition: MachineBasicBlock.cpp:119
HexagonSubtarget.h
llvm::HexagonInstrInfo::predOpcodeHasNot
bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const
Definition: HexagonInstrInfo.cpp:3176
ErrorHandling.h
llvm::MachineRegisterInfo::defusechain_instr_iterator
defusechain_iterator - This class provides iterator support for machine operands in the function that...
Definition: MachineRegisterInfo.h:269
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
MachineBasicBlock.h
isImmValidForOpcode
static bool isImmValidForOpcode(unsigned CmpOpc, int64_t Imm)
Definition: HexagonHardwareLoops.cpp:1594
llvm::X86II::PD
@ PD
Definition: X86BaseInfo.h:782
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MachineOperand::setImm
void setImm(int64_t immVal)
Definition: MachineOperand.h:655
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
Shift
bool Shift
Definition: README.txt:468
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:486
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:831
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::LoopBase::begin
iterator begin() const
Definition: LoopInfo.h:154
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
STLExtras.h
llvm::DomTreeNodeBase::getIDom
DomTreeNodeBase * getIDom() const
Definition: GenericDomTree.h:89
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::RISCVFenceField::R
@ R
Definition: RISCVBaseInfo.h:198
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:90
llvm::MachineRegisterInfo::use_nodbg_begin
use_nodbg_iterator use_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:518
MachineRegisterInfo.h
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:58
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1304
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:751
CommandLine.h
llvm::MachineBasicBlock::pred_size
unsigned pred_size() const
Definition: MachineBasicBlock.h:328
llvm::LoopBase::getParentLoop
LoopT * getParentLoop() const
Return the parent loop if it exists or nullptr for top level loops.
Definition: LoopInfo.h:113
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
llvm::MachineLoop::dump
void dump() const
Definition: MachineLoopInfo.cpp:208
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
MachineLoopInfo.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
Constants.h
llvm::MachineDominatorTree::addNewBlock
MachineDomTreeNode * addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB)
addNewBlock - Add a new node to the dominator tree information.
Definition: MachineDominators.h:177
llvm::HexagonInstrInfo::doesNotReturn
bool doesNotReturn(const MachineInstr &CallMI) const
Definition: HexagonInstrInfo.cpp:3011
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineOperand::isUse
bool isUse() const
Definition: MachineOperand.h:370
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
EQ
#define EQ(a, b)
Definition: regexec.c:112
llvm::MachineOperand::setSubReg
void setSubReg(unsigned subReg)
Definition: MachineOperand.h:471
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
t
bitcast float %x to i32 %s=and i32 %t, 2147483647 %d=bitcast i32 %s to float ret float %d } declare float @fabsf(float %n) define float @bar(float %x) nounwind { %d=call float @fabsf(float %x) ret float %d } This IR(from PR6194):target datalayout="e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple="x86_64-apple-darwin10.0.0" %0=type { double, double } %struct.float3=type { float, float, float } define void @test(%0, %struct.float3 *nocapture %res) nounwind noinline ssp { entry:%tmp18=extractvalue %0 %0, 0 t
Definition: README-SSE.txt:788
llvm::LoopBase::end
iterator end() const
Definition: LoopInfo.h:155
llvm::MachineDominatorTree::changeImmediateDominator
void changeImmediateDominator(MachineBasicBlock *N, MachineBasicBlock *NewIDom)
changeImmediateDominator - This method is used to update the dominator tree information when a node's...
Definition: MachineDominators.h:186
llvm::MachineLoop::findLoopControlBlock
MachineBasicBlock * findLoopControlBlock()
Find the block that contains the loop control variable and the loop test.
Definition: MachineLoopInfo.cpp:91
false
Definition: StackSlotColoring.cpp:142
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:596
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::LoopBase::getBlocks
ArrayRef< BlockT * > getBlocks() const
Get a list of the basic blocks which make up this loop.
Definition: LoopInfo.h:171
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::STATISTIC
STATISTIC(NumFunctions, "Total number of functions")
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::HexagonInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Insert branch code into the end of the specified MachineBasicBlock.
Definition: HexagonInstrInfo.cpp:584
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:52
llvm::MachineRegisterInfo::use_nodbg_end
static use_nodbg_iterator use_nodbg_end()
Definition: MachineRegisterInfo.h:521
INT64_MAX
#define INT64_MAX
Definition: DataTypes.h:71
DebugLoc.h
HexagonInstrInfo.h
SpecPreheader
static cl::opt< bool > SpecPreheader("hwloop-spec-preheader", cl::init(false), cl::Hidden, cl::ZeroOrMore, cl::desc("Allow speculation of preheader " "instructions"))
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1394
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
Definition: MachineRegisterInfo.h:634
llvm::LoopBase::block_begin
block_iterator block_begin() const
Definition: LoopInfo.h:176
llvm::cl::ZeroOrMore
@ ZeroOrMore
Definition: CommandLine.h:120
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
llvm::HexagonSubtarget::getInstrInfo
const HexagonInstrInfo * getInstrInfo() const override
Definition: HexagonSubtarget.h:120
llvm::isInt< 8 >
constexpr bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:367
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:202
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::tgtok::In
@ In
Definition: TGLexer.h:51
hwloops
hwloops
Definition: HexagonHardwareLoops.cpp:371
llvm::cl::opt
Definition: CommandLine.h:1432
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::SmallSet::count
size_type count(const T &V) const
count - Return 1 if the element is in the set, 0 otherwise.
Definition: SmallSet.h:164
llvm::MachineBasicBlock::pred_end
pred_iterator pred_end()
Definition: MachineBasicBlock.h:318
llvm::MCInstrDesc::isAdd
bool isAdd() const
Return true if the instruction is an add instruction.
Definition: MCInstrDesc.h:270
llvm::HexagonISD::CONST32
@ CONST32
Definition: HexagonISelLowering.h:37
PHFn
static cl::opt< std::string > PHFn("hexagon-hwloop-phfn", cl::Hidden, cl::init(""))
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::MachineOperand::CreateMBB
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
Definition: MachineOperand.h:816
llvm::MachineBasicBlock::hasAddressTaken
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
Definition: MachineBasicBlock.h:211
llvm::MachineRegisterInfo::use_nodbg_iterator
defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator
use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...
Definition: MachineRegisterInfo.h:517
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
llvm::MachineDominatorTree::getNode
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
Definition: MachineDominators.h:169
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::LoopBase::getLoopPreheader
BlockT * getLoopPreheader() const
If there is a preheader for this loop, return it.
Definition: LoopInfoImpl.h:167
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:415
ArrayRef.h
MachineFunctionPass.h
llvm::MachineBasicBlock::pred_iterator
std::vector< MachineBasicBlock * >::iterator pred_iterator
Definition: MachineBasicBlock.h:304
llvm::LoopBase::getLoopLatch
BlockT * getLoopLatch() const
If there is a single latch block for this loop, return it.
Definition: LoopInfoImpl.h:216
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::isUInt< 8 >
constexpr bool isUInt< 8 >(uint64_t x)
Definition: MathExtras.h:405
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineBasicBlock::setHasAddressTaken
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
Definition: MachineBasicBlock.h:215
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::X86II::TB
@ TB
Definition: X86BaseInfo.h:800
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1255
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::instr_begin
instr_iterator instr_begin()
Definition: MachineBasicBlock.h:252
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:31
llvm::MachineBasicBlock::instr_end
instr_iterator instr_end()
Definition: MachineBasicBlock.h:254
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::HexagonInstrInfo
Definition: HexagonInstrInfo.h:38
llvm::MachineRegisterInfo::use_nodbg_empty
bool use_nodbg_empty(Register RegNo) const
use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.
Definition: MachineRegisterInfo.h:566
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:242
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MachineRegisterInfo::use_begin
use_iterator use_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:464
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
HWLoopLimit
static cl::opt< int > HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1))
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
llvm::DomTreeNodeBase
Base class for the actual dominator tree node.
Definition: LiveIntervalCalc.h:24
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
j
return j(j<< 16)
llvm::NVPTX::PTXLdStInstCode::V2
@ V2
Definition: NVPTX.h:123
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::HexagonSubtarget::getRegisterInfo
const HexagonRegisterInfo * getRegisterInfo() const override
Definition: HexagonSubtarget.h:121
llvm::X86::FirstMacroFusionInstKind::Cmp
@ Cmp
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1317
llvm::MachineBasicBlock::instr_iterator
Instructions::iterator instr_iterator
Definition: MachineBasicBlock.h:228
llvm::LoopBase::getHeader
BlockT * getHeader() const
Definition: LoopInfo.h:104
LC0
into eax xorps xmm0 xmm0 eax xmm0 eax xmm0 ret esp eax movdqa LC0
Definition: README-SSE.txt:632
llvm::HexagonInstrInfo::isValidOffset
bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const
Definition: HexagonInstrInfo.cpp:2704
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops", "Hexagon Hardware Loops", false, false) INITIALIZE_PASS_END(HexagonHardwareLoops
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:476
HWCreatePreheader
static cl::opt< bool > HWCreatePreheader("hexagon-hwloop-preheader", cl::Hidden, cl::init(true), cl::desc("Add a preheader to a hardware loop if one doesn't exist"))
llvm::MachineRegisterInfo::use_end
static use_iterator use_end()
Definition: MachineRegisterInfo.h:467
llvm::HexagonInstrInfo::getPredReg
bool getPredReg(ArrayRef< MachineOperand > Cond, unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const
Definition: HexagonInstrInfo.cpp:4441
SmallVector.h
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::LoopBase::addBasicBlockToLoop
void addBasicBlockToLoop(BlockT *NewBB, LoopInfoBase< BlockT, LoopT > &LI)
This method is used by other analyses to update loop information.
Definition: LoopInfoImpl.h:242
llvm::LoopBase< MachineBasicBlock, MachineLoop >::iterator
std::vector< MachineLoop * >::const_iterator iterator
Definition: LoopInfo.h:151
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::SmallVectorImpl::iterator
typename SuperClass::iterator iterator
Definition: SmallVector.h:562
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:492
llvm::MachineLoop::getTopBlock
MachineBasicBlock * getTopBlock()
Return the "top" block in the loop, which is the first block in the linear layout,...
Definition: MachineLoopInfo.cpp:61
llvm::MachineInstr::addOperand
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
Definition: MachineInstr.cpp:207
llvm::BlockAddress::get
static BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
Definition: Constants.cpp:1834
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::MachineOperand::setMBB
void setMBB(MachineBasicBlock *MBB)
Definition: MachineOperand.h:689
llvm::MachineRegisterInfo::defusechain_iterator
reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...
Definition: MachineRegisterInfo.h:266
llvm::SmallSet::empty
LLVM_NODISCARD bool empty() const
Definition: SmallSet.h:155
llvm::SmallVectorImpl< MachineInstr * >
MachineOperand.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::HexagonRegisterInfo
Definition: HexagonRegisterInfo.h:29
llvm::MachineFunction::CreateMachineInstr
MachineInstr * CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL, bool NoImplicit=false)
CreateMachineInstr - Allocate a new MachineInstr.
Definition: MachineFunction.cpp:349
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
llvm::createHexagonHardwareLoops
FunctionPass * createHexagonHardwareLoops()
Definition: HexagonHardwareLoops.cpp:374
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
n
The same transformation can work with an even modulo with the addition of a and shrink the compare RHS by the same amount Unless the target supports that transformation probably isn t worthwhile The transformation can also easily be made to work with non zero equality for n
Definition: README.txt:685
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::initializeHexagonHardwareLoopsPass
void initializeHexagonHardwareLoopsPass(PassRegistry &)
InitializePasses.h
TargetRegisterInfo.h
Debug.h
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
MachineDominators.h
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37
INT64_MIN
#define INT64_MIN
Definition: DataTypes.h:74